<div dir="ltr">Hi Roman,<div><br></div><div>I'm seeing significant (5% or more) regressions in Eigen real's benchmarks with this patch on x86 running with sse4.2 on skylake. Likely this means that the previous code was handled in the backend, but not this. I've added Craig here as well for the x86 side of things. Did you end up running any performance analysis on generated code with this?</div><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sat, Jul 4, 2020 at 8:13 AM Roman Lebedev via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Roman Lebedev<br>
Date: 2020-07-04T18:12:04+03:00<br>
New Revision: c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248.diff</a><br>
<br>
LOG: [InstCombine] Always try to invert non-canonical predicate of an icmp<br>
<br>
Summary:<br>
The actual transform i was going after was:<br>
<a href="https://rise4fun.com/Alive/Tp9H" rel="noreferrer" target="_blank">https://rise4fun.com/Alive/Tp9H</a><br>
```<br>
Name: zz<br>
Pre: isPowerOf2(C0) && isPowerOf2(C1) && C1 == C0<br>
%t0 = and i8 %x, C0<br>
%r = icmp eq i8 %t0, C1<br>
=><br>
%t = icmp eq i8 %t0, 0<br>
%r = xor i1 %t, -1<br>
<br>
Name: zz<br>
Pre: isPowerOf2(C0)<br>
%t0 = and i8 %x, C0<br>
%r = icmp ne i8 %t0, 0<br>
=><br>
%t = icmp eq i8 %t0, 0<br>
%r = xor i1 %t, -1<br>
```<br>
but as it can be seen from the current tests, we already canonicalize most of it,<br>
and we are only missing handling multi-use non-canonical icmp predicates.<br>
<br>
If we have both `!=0` and `==0`, even though we can CSE them,<br>
we end up being stuck with them. We should canonicalize to the `==0`.<br>
<br>
I believe this is one of the cleanup steps i'll need after `-scalarizer`<br>
if i end up proceeding with my WIP alloca promotion helper pass.<br>
<br>
Reviewers: spatel, jdoerfert, nikic<br>
<br>
Reviewed By: nikic<br>
<br>
Subscribers: zzheng, hiraditya, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D83139" rel="noreferrer" target="_blank">https://reviews.llvm.org/D83139</a><br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp<br>
llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp<br>
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
llvm/test/ThinLTO/X86/cfi-devirt.ll<br>
llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll<br>
llvm/test/Transforms/InstCombine/icmp-mul-zext.ll<br>
llvm/test/Transforms/InstCombine/logical-select.ll<br>
llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll<br>
llvm/test/Transforms/InstCombine/shift.ll<br>
llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll<br>
llvm/test/Transforms/PGOProfile/chr.ll<br>
llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp<br>
index 53a3af03e46f..31cd8e4510fa 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp<br>
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp<br>
@@ -5283,6 +5283,47 @@ static ICmpInst *canonicalizeCmpWithConstant(ICmpInst &I) {<br>
return new ICmpInst(FlippedStrictness->first, Op0, FlippedStrictness->second);<br>
}<br>
<br>
+/// If we have a comparison with a non-canonical predicate, if we can update<br>
+/// all the users, invert the predicate and adjust all the users.<br>
+static CmpInst *canonicalizeICmpPredicate(CmpInst &I) {<br>
+ // Is the predicate already canonical?<br>
+ CmpInst::Predicate Pred = I.getPredicate();<br>
+ if (isCanonicalPredicate(Pred))<br>
+ return nullptr;<br>
+<br>
+ // Can all users be adjusted to predicate inversion?<br>
+ if (!canFreelyInvertAllUsersOf(&I, /*IgnoredUser=*/nullptr))<br>
+ return nullptr;<br>
+<br>
+ // Ok, we can canonicalize comparison!<br>
+ // Let's first invert the comparison's predicate.<br>
+ I.setPredicate(CmpInst::getInversePredicate(Pred));<br>
+ I.setName(I.getName() + ".not");<br>
+<br>
+ // And now let's adjust every user.<br>
+ for (User *U : I.users()) {<br>
+ switch (cast<Instruction>(U)->getOpcode()) {<br>
+ case Instruction::Select: {<br>
+ auto *SI = cast<SelectInst>(U);<br>
+ SI->swapValues();<br>
+ SI->swapProfMetadata();<br>
+ break;<br>
+ }<br>
+ case Instruction::Br:<br>
+ cast<BranchInst>(U)->swapSuccessors(); // swaps prof metadata too<br>
+ break;<br>
+ case Instruction::Xor:<br>
+ U->replaceAllUsesWith(&I);<br>
+ break;<br>
+ default:<br>
+ llvm_unreachable("Got unexpected user - out of sync with "<br>
+ "canFreelyInvertAllUsersOf() ?");<br>
+ }<br>
+ }<br>
+<br>
+ return &I;<br>
+}<br>
+<br>
/// Integer compare with boolean values can always be turned into bitwise ops.<br>
static Instruction *canonicalizeICmpBool(ICmpInst &I,<br>
InstCombiner::BuilderTy &Builder) {<br>
@@ -5521,8 +5562,11 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {<br>
if (Instruction *Res = canonicalizeICmpBool(I, Builder))<br>
return Res;<br>
<br>
- if (ICmpInst *NewICmp = canonicalizeCmpWithConstant(I))<br>
- return NewICmp;<br>
+ if (Instruction *Res = canonicalizeCmpWithConstant(I))<br>
+ return Res;<br>
+<br>
+ if (Instruction *Res = canonicalizeICmpPredicate(I))<br>
+ return Res;<br>
<br>
if (Instruction *Res = foldICmpWithConstant(I))<br>
return Res;<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
index 8caf580a3fd6..dd2f59be08e9 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
+++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
@@ -215,18 +215,23 @@ static inline bool isFreeToInvert(Value *V, bool WillInvertAllUses) {<br>
}<br>
<br>
/// Given i1 V, can every user of V be freely adapted if V is changed to !V ?<br>
+/// InstCombine's canonicalizeICmpPredicate() must be kept in sync with this fn.<br>
///<br>
/// See also: isFreeToInvert()<br>
static inline bool canFreelyInvertAllUsersOf(Value *V, Value *IgnoredUser) {<br>
// Look at every user of V.<br>
- for (User *U : V->users()) {<br>
- if (U == IgnoredUser)<br>
+ for (Use &U : V->uses()) {<br>
+ if (U.getUser() == IgnoredUser)<br>
continue; // Don't consider this user.<br>
<br>
- auto *I = cast<Instruction>(U);<br>
+ auto *I = cast<Instruction>(U.getUser());<br>
switch (I->getOpcode()) {<br>
case Instruction::Select:<br>
+ if (U.getOperandNo() != 0) // Only if the value is used as select cond.<br>
+ return false;<br>
+ break;<br>
case Instruction::Br:<br>
+ assert(U.getOperandNo() == 0 && "Must be branching on that value.");<br>
break; // Free to invert by swapping true/false values/destinations.<br>
case Instruction::Xor: // Can invert 'xor' if it's a 'not', by ignoring it.<br>
if (!match(I, m_Not(m_Value())))<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp<br>
index 8200310afa43..233fb3878ba7 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp<br>
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp<br>
@@ -2532,21 +2532,7 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {<br>
if (Instruction *I = canonicalizeScalarSelectOfVecs(SI, *this))<br>
return I;<br>
<br>
- // Canonicalize a one-use integer compare with a non-canonical predicate by<br>
- // inverting the predicate and swapping the select operands. This matches a<br>
- // compare canonicalization for conditional branches.<br>
- // TODO: Should we do the same for FP compares?<br>
CmpInst::Predicate Pred;<br>
- if (match(CondVal, m_OneUse(m_ICmp(Pred, m_Value(), m_Value()))) &&<br>
- !isCanonicalPredicate(Pred)) {<br>
- // Swap true/false values and condition.<br>
- CmpInst *Cond = cast<CmpInst>(CondVal);<br>
- Cond->setPredicate(CmpInst::getInversePredicate(Pred));<br>
- SI.swapValues();<br>
- SI.swapProfMetadata();<br>
- Worklist.push(Cond);<br>
- return &SI;<br>
- }<br>
<br>
if (SelType->isIntOrIntVectorTy(1) &&<br>
TrueVal->getType() == CondVal->getType()) {<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
index 28dd92924b60..d1c1e5418825 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
@@ -2755,9 +2755,9 @@ Instruction *InstCombiner::visitBranchInst(BranchInst &BI) {<br>
return replaceOperand(<br>
BI, 0, ConstantInt::getFalse(BI.getCondition()->getType()));<br>
<br>
- // Canonicalize, for example, icmp_ne -> icmp_eq or fcmp_one -> fcmp_oeq.<br>
+ // Canonicalize, for example, fcmp_one -> fcmp_oeq.<br>
CmpInst::Predicate Pred;<br>
- if (match(&BI, m_Br(m_OneUse(m_Cmp(Pred, m_Value(), m_Value())),<br>
+ if (match(&BI, m_Br(m_OneUse(m_FCmp(Pred, m_Value(), m_Value())),<br>
m_BasicBlock(), m_BasicBlock())) &&<br>
!isCanonicalPredicate(Pred)) {<br>
// Swap destinations and condition.<br>
<br>
diff --git a/llvm/test/ThinLTO/X86/cfi-devirt.ll b/llvm/test/ThinLTO/X86/cfi-devirt.ll<br>
index 311bed084dee..61e0c166812c 100644<br>
--- a/llvm/test/ThinLTO/X86/cfi-devirt.ll<br>
+++ b/llvm/test/ThinLTO/X86/cfi-devirt.ll<br>
@@ -110,10 +110,10 @@ cont2:<br>
<br>
; Check that traps are conditional. Invalid TYPE_ID can cause<br>
; unconditional traps.<br>
- ; CHECK-IR: br i1 {{.*}}, label %trap<br>
+ ; CHECK-IR: br i1 {{.*}}, label %trap, label %cont2<br>
<br>
; We still have to call it as virtual.<br>
- ; CHECK-IR: %call3 = tail call i32 %8<br>
+ ; CHECK-IR: %call3 = tail call i32 %7<br>
%call3 = tail call i32 %8(%struct.A* nonnull %obj, i32 %call)<br>
ret i32 %call3<br>
}<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll<br>
index c4419a82c115..57390b376b50 100644<br>
--- a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll<br>
+++ b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll<br>
@@ -8,8 +8,8 @@ declare void @use1(i1)<br>
define i8 @p0(i8 %x, i8 %v0, i8 %v1) {<br>
; CHECK-LABEL: @p0(<br>
; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1<br>
-; CHECK-NEXT: [[T1:%.*]] = icmp eq i8 [[T0]], 0<br>
-; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V1:%.*]], i8 [[V0:%.*]], !prof !0<br>
+; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0<br>
+; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]], !prof !0<br>
; CHECK-NEXT: ret i8 [[R]]<br>
;<br>
%t0 = and i8 %x, 1<br>
@@ -20,8 +20,8 @@ define i8 @p0(i8 %x, i8 %v0, i8 %v1) {<br>
define i8 @p1(i8 %x, i8 %v0, i8 %v1) {<br>
; CHECK-LABEL: @p1(<br>
; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1<br>
-; CHECK-NEXT: [[T1:%.*]] = icmp eq i8 [[T0]], 0<br>
-; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V1:%.*]], i8 [[V0:%.*]]<br>
+; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0<br>
+; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]]<br>
; CHECK-NEXT: ret i8 [[R]]<br>
;<br>
%t0 = and i8 %x, 1<br>
@@ -51,14 +51,14 @@ define i8 @t3(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8 %v3, i8* %out, i1 %c) {<br>
; CHECK-LABEL: @t3(<br>
; CHECK-NEXT: bb0:<br>
; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1<br>
-; CHECK-NEXT: [[T1:%.*]] = icmp ne i8 [[T0]], 0<br>
+; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0<br>
; CHECK-NEXT: br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]<br>
; CHECK: bb1:<br>
-; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8 [[V1:%.*]]<br>
+; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]]<br>
; CHECK-NEXT: store i8 [[R0]], i8* [[OUT:%.*]], align 1<br>
; CHECK-NEXT: br label [[BB2]]<br>
; CHECK: bb2:<br>
-; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1]], i8 [[V2:%.*]], i8 [[V3:%.*]]<br>
+; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1_NOT]], i8 [[V3:%.*]], i8 [[V2:%.*]]<br>
; CHECK-NEXT: ret i8 [[R1]]<br>
;<br>
bb0:<br>
@@ -76,10 +76,10 @@ bb2:<br>
define i8 @t4(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8 %v3, i8* %out) {<br>
; CHECK-LABEL: @t4(<br>
; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1<br>
-; CHECK-NEXT: [[T1:%.*]] = icmp ne i8 [[T0]], 0<br>
-; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8 [[V1:%.*]]<br>
+; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0<br>
+; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]]<br>
; CHECK-NEXT: store i8 [[R0]], i8* [[OUT:%.*]], align 1<br>
-; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1]], i8 [[V2:%.*]], i8 [[V3:%.*]]<br>
+; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1_NOT]], i8 [[V3:%.*]], i8 [[V2:%.*]]<br>
; CHECK-NEXT: ret i8 [[R1]]<br>
;<br>
%t0 = and i8 %x, 1<br>
@@ -112,8 +112,8 @@ define i8 @n6(i8 %x, i8 %v0, i8 %v1) {<br>
define i8 @n7(i8 %x, i8 %v0, i8 %v1) {<br>
; CHECK-LABEL: @n7(<br>
; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1<br>
-; CHECK-NEXT: [[T1:%.*]] = icmp eq i8 [[T0]], 0<br>
-; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8 [[V1:%.*]]<br>
+; CHECK-NEXT: [[T1_NOT_NOT:%.*]] = icmp eq i8 [[T0]], 0<br>
+; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT_NOT]], i8 [[V0:%.*]], i8 [[V1:%.*]]<br>
; CHECK-NEXT: ret i8 [[R]]<br>
;<br>
%t0 = and i8 %x, 1<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll<br>
index a5b148ebd796..31540e600f9f 100644<br>
--- a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll<br>
+++ b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll<br>
@@ -13,16 +13,16 @@ define i32 @sterix(i32, i8, i64) {<br>
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], [[SH_PROM]]<br>
; CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[SHR]] to i64<br>
; CHECK-NEXT: [[MUL3:%.*]] = mul nuw nsw i64 [[CONV]], [[CONV2]]<br>
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[MUL3]], 4294967295<br>
-; CHECK-NEXT: br i1 [[TMP3]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[MUL3]], 4294967296<br>
+; CHECK-NEXT: br i1 [[TMP3]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]<br>
; CHECK: lor.rhs:<br>
; CHECK-NEXT: [[AND:%.*]] = and i64 [[MUL3]], [[TMP2]]<br>
; CHECK-NEXT: [[CONV4:%.*]] = trunc i64 [[AND]] to i32<br>
-; CHECK-NEXT: [[TOBOOL7:%.*]] = icmp eq i32 [[CONV4]], 0<br>
-; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL7]] to i32<br>
+; CHECK-NEXT: [[TOBOOL7_NOT:%.*]] = icmp eq i32 [[CONV4]], 0<br>
+; CHECK-NEXT: [[PHITMP:%.*]] = zext i1 [[TOBOOL7_NOT]] to i32<br>
; CHECK-NEXT: br label [[LOR_END]]<br>
; CHECK: lor.end:<br>
-; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[PHI_CAST]], [[LOR_RHS]] ]<br>
+; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[PHITMP]], [[LOR_RHS]] ]<br>
; CHECK-NEXT: ret i32 [[TMP4]]<br>
;<br>
entry:<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll<br>
index e14e2bf964d9..2f532be03fbf 100644<br>
--- a/llvm/test/Transforms/InstCombine/logical-select.ll<br>
+++ b/llvm/test/Transforms/InstCombine/logical-select.ll<br>
@@ -19,8 +19,8 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {<br>
<br>
define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d) {<br>
; CHECK-LABEL: @bar(<br>
-; CHECK-NEXT: [[E:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]<br>
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[E]], i32 [[C:%.*]], i32 [[D:%.*]]<br>
+; CHECK-NEXT: [[E_NOT:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[E_NOT]], i32 [[C:%.*]], i32 [[D:%.*]]<br>
; CHECK-NEXT: ret i32 [[TMP1]]<br>
;<br>
%e = icmp slt i32 %a, %b<br>
@@ -69,8 +69,8 @@ define i32 @fold_inverted_icmp_preds(i32 %a, i32 %b, i32 %c, i32 %d) {<br>
; CHECK-LABEL: @fold_inverted_icmp_preds(<br>
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]<br>
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 [[C:%.*]], i32 0<br>
-; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B]]<br>
-; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 0, i32 [[D:%.*]]<br>
+; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp slt i32 [[A]], [[B]]<br>
+; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2_NOT]], i32 0, i32 [[D:%.*]]<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]<br>
; CHECK-NEXT: ret i32 [[OR]]<br>
;<br>
@@ -88,8 +88,8 @@ define i32 @fold_inverted_icmp_preds_reverse(i32 %a, i32 %b, i32 %c, i32 %d) {<br>
; CHECK-LABEL: @fold_inverted_icmp_preds_reverse(<br>
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]<br>
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 [[C:%.*]]<br>
-; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B]]<br>
-; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 [[D:%.*]], i32 0<br>
+; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp slt i32 [[A]], [[B]]<br>
+; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2_NOT]], i32 [[D:%.*]], i32 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]<br>
; CHECK-NEXT: ret i32 [[OR]]<br>
;<br>
@@ -124,8 +124,8 @@ define i32 @fold_inverted_fcmp_preds(float %a, float %b, i32 %c, i32 %d) {<br>
<br>
define <2 x i32> @fold_inverted_icmp_vector_preds(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {<br>
; CHECK-LABEL: @fold_inverted_icmp_vector_preds(<br>
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq <2 x i32> [[A:%.*]], [[B:%.*]]<br>
-; CHECK-NEXT: [[SEL1:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> zeroinitializer, <2 x i32> [[C:%.*]]<br>
+; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq <2 x i32> [[A:%.*]], [[B:%.*]]<br>
+; CHECK-NEXT: [[SEL1:%.*]] = select <2 x i1> [[CMP1_NOT]], <2 x i32> zeroinitializer, <2 x i32> [[C:%.*]]<br>
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq <2 x i32> [[A]], [[B]]<br>
; CHECK-NEXT: [[SEL2:%.*]] = select <2 x i1> [[CMP2]], <2 x i32> [[D:%.*]], <2 x i32> zeroinitializer<br>
; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[SEL1]], [[SEL2]]<br>
@@ -535,9 +535,9 @@ define <4 x i32> @vec_sel_xor_multi_use(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c)<br>
<br>
define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) {<br>
; CHECK-LABEL: @allSignBits(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[COND:%.*]], -1<br>
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[FVAL:%.*]], i32 [[TVAL:%.*]]<br>
-; CHECK-NEXT: ret i32 [[TMP2]]<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp slt i32 [[COND:%.*]], 0<br>
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[DOTNOT]], i32 [[TVAL:%.*]], i32 [[FVAL:%.*]]<br>
+; CHECK-NEXT: ret i32 [[TMP1]]<br>
;<br>
%bitmask = ashr i32 %cond, 31<br>
%not_bitmask = xor i32 %bitmask, -1<br>
@@ -549,9 +549,9 @@ define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) {<br>
<br>
define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) {<br>
; CHECK-LABEL: @allSignBits_vec(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1><br>
-; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]]<br>
-; CHECK-NEXT: ret <4 x i8> [[TMP2]]<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1><br>
+; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[DOTNOT]], <4 x i8> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]]<br>
+; CHECK-NEXT: ret <4 x i8> [[TMP1]]<br>
;<br>
%bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7><br>
%not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1><br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll<br>
index d46227d74db3..6eccbecd1d4d 100644<br>
--- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll<br>
+++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll<br>
@@ -153,9 +153,9 @@ define <2 x i32> @select_icmp_ne_0_and_4096_or_4096_vec(<2 x i32> %x, <2 x i32><br>
define i32 @select_icmp_ne_0_and_4096_xor_4096(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_4096_xor_4096(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 4096<br>
@@ -168,9 +168,9 @@ define i32 @select_icmp_ne_0_and_4096_xor_4096(i32 %x, i32 %y) {<br>
define i32 @select_icmp_ne_0_and_4096_and_not_4096(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_4096_and_not_4096(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 4096<br>
@@ -311,9 +311,9 @@ define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {<br>
define i32 @select_icmp_ne_0_and_4096_xor_32(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_4096_xor_32(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 32<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 4096<br>
@@ -326,9 +326,9 @@ define i32 @select_icmp_ne_0_and_4096_xor_32(i32 %x, i32 %y) {<br>
define i32 @select_icmp_ne_0_and_4096_and_not_32(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_4096_and_not_32(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -33<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 4096<br>
@@ -371,9 +371,9 @@ define <2 x i32> @select_icmp_ne_0_and_32_or_4096_vec(<2 x i32> %x, <2 x i32> %y<br>
define i32 @select_icmp_ne_0_and_32_xor_4096(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_32_xor_4096(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 32<br>
@@ -386,9 +386,9 @@ define i32 @select_icmp_ne_0_and_32_xor_4096(i32 %x, i32 %y) {<br>
define i32 @select_icmp_ne_0_and_32_and_not_4096(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_32_and_not_4096(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 32<br>
@@ -401,9 +401,9 @@ define i32 @select_icmp_ne_0_and_32_and_not_4096(i32 %x, i32 %y) {<br>
define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_or_8(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], 8<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[OR]], i8 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i8 [[OR]], i8 [[Y]]<br>
; CHECK-NEXT: ret i8 [[SELECT]]<br>
;<br>
%and = and i32 %x, 1073741824<br>
@@ -416,9 +416,9 @@ define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) {<br>
define i8 @select_icmp_ne_0_and_1073741824_xor_8(i32 %x, i8 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_xor_8(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[Y:%.*]], 8<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[XOR]], i8 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i8 [[XOR]], i8 [[Y]]<br>
; CHECK-NEXT: ret i8 [[SELECT]]<br>
;<br>
%and = and i32 %x, 1073741824<br>
@@ -431,9 +431,9 @@ define i8 @select_icmp_ne_0_and_1073741824_xor_8(i32 %x, i8 %y) {<br>
define i8 @select_icmp_ne_0_and_1073741824_and_not_8(i32 %x, i8 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_and_not_8(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i8 [[Y:%.*]], -9<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[AND2]], i8 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i8 [[AND2]], i8 [[Y]]<br>
; CHECK-NEXT: ret i8 [[SELECT]]<br>
;<br>
%and = and i32 %x, 1073741824<br>
@@ -446,9 +446,9 @@ define i8 @select_icmp_ne_0_and_1073741824_and_not_8(i32 %x, i8 %y) {<br>
define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_8_or_1073741824(<br>
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i8 [[AND]], 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 1073741824<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i8 %x, 8<br>
@@ -461,9 +461,9 @@ define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) {<br>
define i32 @select_icmp_ne_0_and_8_xor_1073741824(i8 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_8_xor_1073741824(<br>
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i8 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 1073741824<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i8 %x, 8<br>
@@ -476,9 +476,9 @@ define i32 @select_icmp_ne_0_and_8_xor_1073741824(i8 %x, i32 %y) {<br>
define i32 @select_icmp_ne_0_and_8_and_not_1073741824(i8 %x, i32 %y) {<br>
; CHECK-LABEL: @select_icmp_ne_0_and_8_and_not_1073741824(<br>
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i8 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -1073741825<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i8 %x, 8<br>
@@ -731,9 +731,9 @@ define <2 x i32> @test69vec(<2 x i32> %x, <2 x i32> %y) {<br>
define i32 @test69_xor(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @test69_xor(<br>
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp sgt i8 [[TMP1]], -1<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 128<br>
@@ -746,9 +746,9 @@ define i32 @test69_xor(i32 %x, i32 %y) {<br>
define i32 @test69_and(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @test69_and(<br>
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp sgt i8 [[TMP1]], -1<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], 2<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: ret i32 [[SELECT]]<br>
;<br>
%and = and i32 %x, 128<br>
@@ -892,9 +892,9 @@ define i32 @no_shift_xor_multiuse_or(i32 %x, i32 %y) {<br>
define i32 @no_shift_xor_multiuse_xor(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_xor(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -909,9 +909,9 @@ define i32 @no_shift_xor_multiuse_xor(i32 %x, i32 %y) {<br>
define i32 @no_shift_xor_multiuse_and(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_and(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -926,9 +926,9 @@ define i32 @no_shift_xor_multiuse_and(i32 %x, i32 %y) {<br>
define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @shift_xor_multiuse_or(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]], i32 [[Y]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -943,9 +943,9 @@ define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) {<br>
define i32 @shift_xor_multiuse_xor(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @shift_xor_multiuse_xor(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -960,9 +960,9 @@ define i32 @shift_xor_multiuse_xor(i32 %x, i32 %y) {<br>
define i32 @shift_xor_multiuse_and(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @shift_xor_multiuse_and(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2049<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1090,10 +1090,10 @@ define i32 @no_shift_no_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w<br>
define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_cmp(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096<br>
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1109,10 +1109,10 @@ define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @no_shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_cmp_with_xor(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1128,10 +1128,10 @@ define i32 @no_shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @no_shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_cmp_with_and(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1147,10 +1147,10 @@ define i32 @no_shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @shift_xor_multiuse_cmp(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1166,10 +1166,10 @@ define i32 @shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @shift_xor_multiuse_cmp_with_xor(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1185,10 +1185,10 @@ define i32 @shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @shift_xor_multiuse_cmp_with_and(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2049<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: ret i32 [[RES]]<br>
;<br>
@@ -1330,10 +1330,10 @@ define i32 @no_shift_no_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @no_shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_cmp_or(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]<br>
; CHECK-NEXT: ret i32 [[RES2]]<br>
@@ -1351,10 +1351,10 @@ define i32 @no_shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @no_shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_cmp_xor(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]<br>
; CHECK-NEXT: ret i32 [[RES2]]<br>
@@ -1372,10 +1372,10 @@ define i32 @no_shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @no_shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @no_shift_xor_multiuse_cmp_and(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]<br>
; CHECK-NEXT: ret i32 [[RES2]]<br>
@@ -1393,10 +1393,10 @@ define i32 @no_shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @shift_xor_multiuse_cmp_or(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]<br>
; CHECK-NEXT: ret i32 [[RES2]]<br>
@@ -1414,10 +1414,10 @@ define i32 @shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @shift_xor_multiuse_cmp_xor(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]<br>
; CHECK-NEXT: ret i32 [[RES2]]<br>
@@ -1435,10 +1435,10 @@ define i32 @shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
define i32 @shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {<br>
; CHECK-LABEL: @shift_xor_multiuse_cmp_and(<br>
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096<br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0<br>
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0<br>
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], 2048<br>
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]<br>
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]<br>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[AND2]], i32 [[Y]]<br>
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]<br>
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]<br>
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]<br>
; CHECK-NEXT: ret i32 [[RES2]]<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll<br>
index 52b7c87cb063..714a08d247a2 100644<br>
--- a/llvm/test/Transforms/InstCombine/shift.ll<br>
+++ b/llvm/test/Transforms/InstCombine/shift.ll<br>
@@ -428,8 +428,8 @@ define i8 @test28a(i8 %x, i8 %y) {<br>
; CHECK-LABEL: @test28a(<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[I1:%.*]] = lshr i8 [[X:%.*]], 7<br>
-; CHECK-NEXT: [[COND1:%.*]] = icmp slt i8 [[X]], 0<br>
-; CHECK-NEXT: br i1 [[COND1]], label [[BB1:%.*]], label [[BB2:%.*]]<br>
+; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X]], -1<br>
+; CHECK-NEXT: br i1 [[COND1_NOT]], label [[BB2:%.*]], label [[BB1:%.*]]<br>
; CHECK: bb1:<br>
; CHECK-NEXT: ret i8 [[I1]]<br>
; CHECK: bb2:<br>
<br>
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll<br>
index 75bad6813b0e..7be217b06aae 100644<br>
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll<br>
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll<br>
@@ -1,8 +1,8 @@<br>
; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -S | FileCheck %s -check-prefix=EPILOG-NO-IC<br>
; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S | FileCheck %s -check-prefix=EPILOG<br>
-; RUN: opt < %s -loop-unroll -unroll-runtime -unroll-count=2 -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine<br>
+; RUN: opt < %s -loop-unroll -unroll-runtime -unroll-count=2 -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S<br>
; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=false -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S | FileCheck %s -check-prefix=PROLOG<br>
-; RUN: opt < %s -loop-unroll -unroll-runtime -unroll-runtime-epilog=false -unroll-count=2 -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine<br>
+; RUN: opt < %s -loop-unroll -unroll-runtime -unroll-runtime-epilog=false -unroll-count=2 -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S<br>
<br>
; REQUIRES: asserts<br>
<br>
@@ -23,12 +23,12 @@ define void @test1(i64 %trip, i1 %cond) {<br>
; EPILOG-NEXT: br label [[LOOP_HEADER:%.*]]<br>
; EPILOG: loop_latch.epil:<br>
; EPILOG-NEXT: %epil.iter.sub = add i64 %epil.iter, -1<br>
-; EPILOG-NEXT: %epil.iter.cmp = icmp eq i64 %epil.iter.sub, 0<br>
-; EPILOG-NEXT: br i1 %epil.iter.cmp, label %exit2.loopexit.epilog-lcssa, label %loop_header.epil<br>
+; EPILOG-NEXT: %epil.iter.cmp.not = icmp eq i64 %epil.iter.sub, 0<br>
+; EPILOG-NEXT: br i1 %epil.iter.cmp.not, label %exit2.loopexit.epilog-lcssa, label %loop_header.epil<br>
; EPILOG: loop_latch.7:<br>
; EPILOG-NEXT: %niter.nsub.7 = add i64 %niter, -8<br>
-; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.nsub.7, 0<br>
-; EPILOG-NEXT: br i1 %niter.ncmp.7, label %exit2.loopexit.unr-lcssa.loopexit, label %loop_header<br>
+; EPILOG-NEXT: %niter.ncmp.7.not = icmp eq i64 %niter.nsub.7, 0<br>
+; EPILOG-NEXT: br i1 %niter.ncmp.7.not, label %exit2.loopexit.unr-lcssa.loopexit, label %loop_header<br>
<br>
; PROLOG: test1(<br>
; PROLOG-NEXT: entry:<br>
@@ -43,12 +43,12 @@ define void @test1(i64 %trip, i1 %cond) {<br>
; PROLOG: loop_latch.prol:<br>
; PROLOG-NEXT: %iv_next.prol = add i64 %iv.prol, 1<br>
; PROLOG-NEXT: %prol.iter.sub = add i64 %prol.iter, -1<br>
-; PROLOG-NEXT: %prol.iter.cmp = icmp eq i64 %prol.iter.sub, 0<br>
-; PROLOG-NEXT: br i1 %prol.iter.cmp, label %loop_header.prol.loopexit.unr-lcssa, label %loop_header.prol<br>
+; PROLOG-NEXT: %prol.iter.cmp.not = icmp eq i64 %prol.iter.sub, 0<br>
+; PROLOG-NEXT: br i1 %prol.iter.cmp.not, label %loop_header.prol.loopexit.unr-lcssa, label %loop_header.prol<br>
; PROLOG: loop_latch.7:<br>
; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8<br>
-; PROLOG-NEXT: %cmp.7 = icmp eq i64 %iv_next.7, %trip<br>
-; PROLOG-NEXT: br i1 %cmp.7, label %exit2.loopexit.unr-lcssa, label %loop_header<br>
+; PROLOG-NEXT: %cmp.7.not = icmp eq i64 %iv_next.7, %trip<br>
+; PROLOG-NEXT: br i1 %cmp.7.not, label %exit2.loopexit.unr-lcssa, label %loop_header<br>
entry:<br>
br label %loop_header<br>
<br>
@@ -157,8 +157,8 @@ define void @test3(i64 %trip, i64 %add) {<br>
; EPILOG: loop_latch.7:<br>
; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add<br>
; EPILOG-NEXT: %niter.nsub.7 = add i64 %niter, -8<br>
-; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.nsub.7, 0<br>
-; EPILOG-NEXT: br i1 %niter.ncmp.7, label %exit2.loopexit.unr-lcssa.loopexit, label %loop_header<br>
+; EPILOG-NEXT: %niter.ncmp.7.not = icmp eq i64 %niter.nsub.7, 0<br>
+; EPILOG-NEXT: br i1 %niter.ncmp.7.not, label %exit2.loopexit.unr-lcssa.loopexit, label %loop_header<br>
<br>
; PROLOG: test3(<br>
; PROLOG-NEXT: entry:<br>
@@ -174,8 +174,8 @@ define void @test3(i64 %trip, i64 %add) {<br>
; PROLOG: loop_latch.7:<br>
; PROLOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8<br>
; PROLOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add<br>
-; PROLOG-NEXT: %cmp.7 = icmp eq i64 %iv_next.7, %trip<br>
-; PROLOG-NEXT: br i1 %cmp.7, label %exit2.loopexit.unr-lcssa, label %loop_header<br>
+; PROLOG-NEXT: %cmp.7.not = icmp eq i64 %iv_next.7, %trip<br>
+; PROLOG-NEXT: br i1 %cmp.7.not, label %exit2.loopexit.unr-lcssa, label %loop_header<br>
entry:<br>
br label %loop_header<br>
<br>
@@ -575,8 +575,8 @@ define void @test8() {<br>
; PROLOG: test8(<br>
; PROLOG: outerloop:<br>
; PROLOG-NEXT: phi i64 [ 3, %bb ], [ 0, %outerloop.loopexit ]<br>
-; PROLOG: %lcmp.mod = icmp eq i64<br>
-; PROLOG-NEXT: br i1 %lcmp.mod, label %innerH.prol.loopexit, label %innerH.prol.preheader<br>
+; PROLOG: %lcmp.mod.not = icmp eq i64<br>
+; PROLOG-NEXT: br i1 %lcmp.mod.not, label %innerH.prol.loopexit, label %innerH.prol.preheader<br>
; PROLOG: latch.6:<br>
; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label %latch.7<br>
; PROLOG: latch.7:<br>
@@ -613,7 +613,7 @@ define i8 addrspace(1)* @test9(i8* nocapture readonly %arg, i32 %n) {<br>
; PROLOG-NEXT: %phi.prol = phi i64 [ 0, %header.prol.preheader ], [ %iv.next.prol, %latch.prol ]<br>
; PROLOG: latch.prol:<br>
; PROLOG-NOT: trip<br>
-; PROLOG: br i1 %prol.iter.cmp, label %header.prol.loopexit.unr-lcssa, label %header.prol<br>
+; PROLOG: br i1 %prol.iter.cmp.not, label %header.prol.loopexit.unr-lcssa, label %header.prol<br>
bb:<br>
br label %outerloopHdr<br>
<br>
<br>
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll b/llvm/test/Transforms/PGOProfile/chr.ll<br>
index 9a6477aeb101..e2161d617022 100644<br>
--- a/llvm/test/Transforms/PGOProfile/chr.ll<br>
+++ b/llvm/test/Transforms/PGOProfile/chr.ll<br>
@@ -36,15 +36,15 @@ define void @test_chr_1(i32* %i) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
; CHECK: bb1.nonchr:<br>
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB3]]<br>
@@ -109,22 +109,22 @@ define void @test_chr_1_1(i32* %i) !prof !14 {<br>
; CHECK-NEXT: br label [[BB5:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
; CHECK: bb1.nonchr:<br>
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB2_NONCHR:%.*]], label [[BB3_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB3_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
; CHECK-NEXT: call void @bar()<br>
; CHECK-NEXT: br label [[BB3_NONCHR]]<br>
; CHECK: bb3.nonchr:<br>
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 4<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0<br>
-; CHECK-NEXT: br i1 [[TMP8]], label [[BB5]], label [[BB4_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 4<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB5]], label [[BB4_NONCHR:%.*]], !prof !16<br>
; CHECK: bb4.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB5]]<br>
@@ -195,16 +195,16 @@ define void @test_chr_2(i32* %i) !prof !14 {<br>
; CHECK-NEXT: br label [[BB4:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[BB4]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB4]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB2_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 1<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0<br>
-; CHECK-NEXT: br i1 [[TMP8]], label [[BB4]], label [[BB3_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB4]], label [[BB3_NONCHR:%.*]], !prof !16<br>
; CHECK: bb3.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB4]]<br>
@@ -288,38 +288,38 @@ define void @test_chr_3(i32* %i) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
; CHECK: bb1.nonchr:<br>
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4<br>
-; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 12<br>
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 12<br>
-; CHECK-NEXT: br i1 [[TMP9]], label [[BB4:%.*]], label [[BB3_SPLIT_NONCHR:%.*]], !prof !15<br>
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4<br>
+; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 12<br>
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 12<br>
+; CHECK-NEXT: br i1 [[TMP8]], label [[BB4:%.*]], label [[BB3_SPLIT_NONCHR:%.*]], !prof !15<br>
; CHECK: bb4:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB7:%.*]]<br>
; CHECK: bb3.split.nonchr:<br>
-; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP7]], 4<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0<br>
-; CHECK-NEXT: br i1 [[TMP11]], label [[BB5_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP6]], 4<br>
+; CHECK-NEXT: [[DOTNOT1:%.*]] = icmp eq i32 [[TMP9]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT1]], label [[BB5_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof !16<br>
; CHECK: bb4.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB5_NONCHR]]<br>
; CHECK: bb5.nonchr:<br>
-; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP7]], 8<br>
-; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0<br>
-; CHECK-NEXT: br i1 [[TMP13]], label [[BB7]], label [[BB6_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP6]], 8<br>
+; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0<br>
+; CHECK-NEXT: br i1 [[TMP11]], label [[BB7]], label [[BB6_NONCHR:%.*]], !prof !16<br>
; CHECK: bb6.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB7]]<br>
@@ -396,12 +396,12 @@ define i32 @test_chr_4(i32* %i, i32 %sum0) !prof !14 {<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SUM0]], 42<br>
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP4]], !prof !16<br>
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[SUM1_NONCHR]], 43<br>
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP8]], i32 [[SUM1_NONCHR]], i32 [[TMP9]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0<br>
+; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[DOTNOT]], i32 [[SUM0]], i32 [[TMP4]], !prof !16<br>
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1_NONCHR]], 43<br>
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM1_NONCHR]], i32 [[TMP8]], !prof !16<br>
; CHECK-NEXT: ret i32 [[SUM2_NONCHR]]<br>
;<br>
entry:<br>
@@ -455,24 +455,24 @@ define i32 @test_chr_5(i32* %i, i32 %sum0) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[SUM0]], 42<br>
-; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP8]], i32 [[SUM0]], i32 [[TMP9]], !prof !16<br>
-; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[SUM1_NONCHR]], 43<br>
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP11]], i32 [[SUM1_NONCHR]], i32 [[TMP12]], !prof !16<br>
-; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP0]], 4<br>
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0<br>
-; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[TMP0]], 8<br>
-; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0<br>
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44, i32 88<br>
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 1<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM0]], 42<br>
+; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM0]], i32 [[TMP8]], !prof !16<br>
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[SUM1_NONCHR]], 43<br>
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP10]], i32 [[SUM1_NONCHR]], i32 [[TMP11]], !prof !16<br>
+; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP0]], 4<br>
+; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0<br>
+; CHECK-NEXT: [[TMP14:%.*]] = and i32 [[TMP0]], 8<br>
+; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0<br>
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP15]], i32 44, i32 88<br>
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]<br>
-; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP14]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16<br>
+; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP13]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]<br>
@@ -555,24 +555,24 @@ define i32 @test_chr_5_1(i32* %i, i32 %sum0) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0<br>
-; CHECK-NEXT: br i1 [[TMP9]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP8]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
-; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[SUM0]], 42<br>
-; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP11]], i32 [[SUM0]], i32 [[TMP12]], !prof !16<br>
-; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0<br>
-; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[SUM1_NONCHR]], 43<br>
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP14]], i32 [[SUM1_NONCHR]], i32 [[TMP15]], !prof !16<br>
-; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[SUM0]], 4<br>
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 0<br>
-; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP0]], 8<br>
-; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[TMP18]], 0<br>
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP19]], i32 44, i32 88<br>
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP0]], 1<br>
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[SUM0]], 42<br>
+; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP10]], i32 [[SUM0]], i32 [[TMP11]], !prof !16<br>
+; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0<br>
+; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[SUM1_NONCHR]], 43<br>
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP13]], i32 [[SUM1_NONCHR]], i32 [[TMP14]], !prof !16<br>
+; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[SUM0]], 4<br>
+; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0<br>
+; CHECK-NEXT: [[TMP17:%.*]] = and i32 [[TMP0]], 8<br>
+; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 0<br>
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP18]], i32 44, i32 88<br>
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]<br>
-; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP17]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16<br>
+; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP16]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[TMP7]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]<br>
@@ -656,8 +656,8 @@ define i32 @test_chr_6(i32* %i, i32* %j, i32 %sum0) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[V1:%.*]] = and i32 [[I0]], 255<br>
-; CHECK-NEXT: [[V2:%.*]] = icmp eq i32 [[V1]], 0<br>
-; CHECK-NEXT: br i1 [[V2]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[V2_NOT:%.*]] = icmp eq i32 [[V1]], 0<br>
+; CHECK-NEXT: br i1 [[V2_NOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: [[V3_NONCHR:%.*]] = and i32 [[I0]], 2<br>
; CHECK-NEXT: [[V4_NONCHR:%.*]] = icmp eq i32 [[V3_NONCHR]], 0<br>
@@ -807,8 +807,8 @@ define i32 @test_chr_7_1(i32* %i, i32* %j, i32 %sum0) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[V9:%.*]] = and i32 [[J0]], 4<br>
-; CHECK-NEXT: [[V10:%.*]] = icmp eq i32 [[V9]], 0<br>
-; CHECK-NEXT: br i1 [[V10]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[V10_NOT:%.*]] = icmp eq i32 [[V9]], 0<br>
+; CHECK-NEXT: br i1 [[V10_NOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
@@ -948,22 +948,22 @@ define i32 @test_chr_9(i32* %i, i32* %j) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
-; CHECK-NEXT: br i1 [[TMP5]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
; CHECK: bb1.nonchr:<br>
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4<br>
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
-; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[TMP0]], [[BB1_NONCHR]] ], [ [[TMP8]], [[BB2_NONCHR]] ]<br>
-; CHECK-NEXT: ret i32 [[TMP9]]<br>
+; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[TMP0]], [[BB1_NONCHR]] ], [ [[TMP7]], [[BB2_NONCHR]] ]<br>
+; CHECK-NEXT: ret i32 [[TMP8]]<br>
;<br>
entry:<br>
%0 = load i32, i32* %i<br>
@@ -1029,25 +1029,25 @@ define i32 @test_chr_10(i32* %i, i32* %j) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
-; CHECK-NEXT: br i1 [[TMP5]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
; CHECK: bb1.nonchr:<br>
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4<br>
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0<br>
-; CHECK-NEXT: br i1 [[TMP8]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[J]], align 4<br>
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
-; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[TMP6]], [[BB2_NONCHR]] ], [ [[TMP6]], [[BB1_NONCHR]] ]<br>
-; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], 42<br>
-; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], -99<br>
-; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]]<br>
-; CHECK-NEXT: ret i32 [[TMP12]]<br>
+; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[TMP5]], [[BB2_NONCHR]] ], [ [[TMP5]], [[BB1_NONCHR]] ]<br>
+; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 42<br>
+; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], -99<br>
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]]<br>
+; CHECK-NEXT: ret i32 [[TMP11]]<br>
;<br>
entry:<br>
%0 = load i32, i32* %i<br>
@@ -1476,24 +1476,24 @@ define i32 @test_chr_16(i32* %i) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB1_NONCHR]]<br>
; CHECK: bb1.nonchr:<br>
; CHECK-NEXT: [[V40_NONCHR:%.*]] = add i32 [[TMP0]], 44<br>
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0<br>
+; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof !16<br>
; CHECK: bb2.nonchr:<br>
; CHECK-NEXT: [[V41_NONCHR:%.*]] = add i32 [[TMP0]], 99<br>
; CHECK-NEXT: call void @foo()<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
-; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[V40]], [[BB0]] ], [ [[V40_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]<br>
+; CHECK-NEXT: [[TMP6:%.*]] = phi i32 [ [[V40]], [[BB0]] ], [ [[V40_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]<br>
; CHECK-NEXT: [[V42:%.*]] = phi i32 [ [[V41]], [[BB0]] ], [ [[V41_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]<br>
-; CHECK-NEXT: [[V43:%.*]] = add i32 [[V42]], [[TMP7]]<br>
+; CHECK-NEXT: [[V43:%.*]] = add i32 [[V42]], [[TMP6]]<br>
; CHECK-NEXT: ret i32 [[V43]]<br>
;<br>
entry:<br>
@@ -1661,8 +1661,8 @@ define i32 @test_chr_18(i32* %i, i32 %sum0) !prof !14 {<br>
; CHECK-NEXT: br i1 [[CMP4_NONCHR]], label [[BB2]], label [[BB1_NONCHR:%.*]], !prof !16<br>
; CHECK: bb1.nonchr:<br>
; CHECK-NEXT: [[A1:%.*]] = and i32 [[LI]], 1<br>
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A1]], 0<br>
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1]], i32 [[SUM0]], i32 [[SUM1]], !prof !16<br>
+; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[A1]], 0<br>
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1_NOT]], i32 [[SUM0]], i32 [[SUM1]], !prof !16<br>
; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44<br>
; CHECK-NEXT: br label [[BB2]]<br>
; CHECK: bb2:<br>
@@ -1744,18 +1744,18 @@ define i32 @test_chr_19(i32* %i, i32 %sum0) !prof !14 {<br>
; CHECK-NEXT: br label [[BB3:%.*]]<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0<br>
-; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof !16<br>
; CHECK: bb0.nonchr:<br>
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 1<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[SUM0]], 85<br>
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP8]], i32 [[SUM0]], i32 [[TMP9]], !prof !16<br>
-; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP0]], 8<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0<br>
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP11]], i32 44, i32 88<br>
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 1<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM0]], 85<br>
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM0]], i32 [[TMP8]], !prof !16<br>
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP0]], 8<br>
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0<br>
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP10]], i32 44, i32 88<br>
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]<br>
-; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP8]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16<br>
+; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16<br>
; CHECK-NEXT: br label [[BB3]]<br>
; CHECK: bb3:<br>
; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]<br>
@@ -1842,8 +1842,8 @@ define i32 @test_chr_20(i32* %i, i32 %sum0, i1 %j) !prof !14 {<br>
; CHECK: entry.split.nonchr:<br>
; CHECK-NEXT: [[V8:%.*]] = add i32 [[SUM0]], 43<br>
; CHECK-NEXT: [[V3:%.*]] = and i32 [[I0]], 2<br>
-; CHECK-NEXT: [[V4:%.*]] = icmp eq i32 [[V3]], 0<br>
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof !16<br>
+; CHECK-NEXT: [[V4_NOT:%.*]] = icmp eq i32 [[V3]], 0<br>
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4_NOT]], i32 [[SUM0]], i32 [[V8]], !prof !16<br>
; CHECK-NEXT: [[V6_NONCHR:%.*]] = and i32 [[I0]], 4<br>
; CHECK-NEXT: [[V5_NONCHR:%.*]] = icmp eq i32 [[V6_NONCHR]], 0<br>
; CHECK-NEXT: [[V9_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44<br>
@@ -2328,7 +2328,7 @@ define i64 @test_chr_23(i64 %v0) !prof !14 {<br>
; CHECK-LABEL: @test_chr_23(<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[V0:%.*]], 50<br>
-; CHECK-NEXT: [[V10:%.*]] = icmp ne i64 [[TMP0]], -50<br>
+; CHECK-NEXT: [[V10_NOT:%.*]] = icmp eq i64 [[TMP0]], -50<br>
; CHECK-NEXT: ret i64 99<br>
;<br>
entry:<br>
<br>
diff --git a/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll b/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll<br>
index 3439830d6265..60a6ca0d6379 100644<br>
--- a/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll<br>
+++ b/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll<br>
@@ -42,9 +42,9 @@ end:<br>
define void @test_simple_commuted(i32* %p, i32 %a, i32 %b) {<br>
; CHECK-LABEL: @test_simple_commuted(<br>
; CHECK-NEXT: entry:<br>
-; CHECK-NEXT: [[X1:%.*]] = icmp eq i32 [[A:%.*]], 0<br>
+; CHECK-NEXT: [[X1_NOT:%.*]] = icmp eq i32 [[A:%.*]], 0<br>
; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B:%.*]], 0<br>
-; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[X1]], [[X2]]<br>
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[X1_NOT]], [[X2]]<br>
; CHECK-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]]<br>
; CHECK: 1:<br>
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[X2]] to i32<br>
@@ -274,13 +274,13 @@ define i32 @test_diamond_simple(i32* %p, i32* %q, i32 %a, i32 %b) {<br>
; CHECK-NEXT: [[Z2:%.*]] = select i1 [[X1]], i32 [[B:%.*]], i32 0<br>
; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B]], 0<br>
; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[A]], [[B]]<br>
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0<br>
-; CHECK-NEXT: br i1 [[TMP1]], label [[TMP3:%.*]], label [[TMP2:%.*]]<br>
-; CHECK: 2:<br>
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP0]], 0<br>
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[TMP2:%.*]], label [[TMP1:%.*]]<br>
+; CHECK: 1:<br>
; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[X2]], i32 [[Z2]], i32 1<br>
; CHECK-NEXT: store i32 [[SIMPLIFYCFG_MERGE]], i32* [[P:%.*]], align 4<br>
-; CHECK-NEXT: br label [[TMP3]]<br>
-; CHECK: 3:<br>
+; CHECK-NEXT: br label [[TMP2]]<br>
+; CHECK: 2:<br>
; CHECK-NEXT: [[Z4:%.*]] = select i1 [[X2]], i32 [[Z2]], i32 3<br>
; CHECK-NEXT: ret i32 [[Z4]]<br>
;<br>
<br>
<br>
<br>
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</blockquote></div>