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[AMD Official Use Only - Internal Distribution Only]<br>
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This was in the tabelgen shift? Tablegen should be fixed instead?<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> llvm-commits <llvm-commits-bounces@lists.llvm.org> on behalf of Stanislav Mekhanoshin via llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Sent:</b> Monday, June 15, 2020 5:21 PM<br>
<b>To:</b> llvm-commits@lists.llvm.org <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> [llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift</font>
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Author: Stanislav Mekhanoshin<br>
Date: 2020-06-15T17:21:10-07:00<br>
New Revision: 576fa5a50c8509977835031d190f8906e1dbb075<br>
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LOG: [AMDGPU] make ubsan happy with unsigned left shift<br>
<br>
Fixes UBSAN error after rG9ee272f13d88f090817235ef4f91e56bb2a153d6<br>
A trivial signed/unsigned shift.<br>
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Added:<br>
<br>
<br>
Modified:<br>
llvm/lib/Target/AMDGPU/SMInstructions.td<br>
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Removed:<br>
<br>
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################################################################################<br>
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td<br>
index 252f191a2f66..df21c864ccad 100644<br>
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td<br>
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td<br>
@@ -860,7 +860,7 @@ let OtherPredicates = [HasNoSMemTimeInst] in {<br>
def : GCNPat <<br>
(i64 (readcyclecounter)),<br>
(REG_SEQUENCE SReg_64,<br>
- (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,<br>
+ (S_GETREG_B32 -26595), sub0,<br>
(S_MOV_B32 (i32 0)), sub1)<br>
>;<br>
} // let OtherPredicates = [HasNoSMemTimeInst]<br>
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