<div dir="ltr">Ping. Shall I revert the change? </div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Apr 22, 2020 at 4:41 PM Kostya Serebryany <<a href="mailto:kcc@google.com">kcc@google.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Hi, <div><br></div><div>This change causes our build bots to go red, indicating a potential performance regression. </div><div>I've provided details in <a href="https://reviews.llvm.org/D68408" target="_blank">https://reviews.llvm.org/D68408</a></div><div>Please take a look. </div><div><br></div><div>--kcc </div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Apr 21, 2020 at 12:00 PM Roman Lebedev via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Roman Lebedev<br>
Date: 2020-04-21T22:00:23+03:00<br>
New Revision: 352fef3f11f5ccb2ddc8e16cecb7302a54721e9f<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/352fef3f11f5ccb2ddc8e16cecb7302a54721e9f" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/352fef3f11f5ccb2ddc8e16cecb7302a54721e9f</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/352fef3f11f5ccb2ddc8e16cecb7302a54721e9f.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/352fef3f11f5ccb2ddc8e16cecb7302a54721e9f.diff</a><br>
<br>
LOG: [InstCombine] Negator - sink sinkable negations<br>
<br>
Summary:<br>
As we have discussed previously (e.g. in D63992 / D64090 / [[ <a href="https://bugs.llvm.org/show_bug.cgi?id=42457" rel="noreferrer" target="_blank">https://bugs.llvm.org/show_bug.cgi?id=42457</a> | PR42457 ]]), `sub` instruction<br>
can almost be considered non-canonical. While we do convert `sub %x, C` -> `add %x, -C`,<br>
we sparsely do that for non-constants. But we should.<br>
<br>
Here, i propose to interpret `sub %x, %y` as `add (sub 0, %y), %x` IFF the negation can be sinked into the `%y`<br>
<br>
This has some potential to cause endless combine loops (either around PHI's, or if there are some opposite transforms).<br>
For former there's `-instcombine-negator-max-depth` option to mitigate it, should this expose any such issues<br>
For latter, if there are still any such opposing folds, we'd need to remove the colliding fold.<br>
In any case, reproducers welcomed!<br>
<br>
Reviewers: spatel, nikic, efriedma, xbolva00<br>
<br>
Reviewed By: spatel<br>
<br>
Subscribers: xbolva00, mgorny, hiraditya, reames, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D68408" rel="noreferrer" target="_blank">https://reviews.llvm.org/D68408</a><br>
<br>
Added: <br>
llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp<br>
<br>
Modified: <br>
llvm/lib/Transforms/InstCombine/CMakeLists.txt<br>
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp<br>
llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
llvm/test/Transforms/InstCombine/and-or-icmps.ll<br>
llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll<br>
llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll<br>
llvm/test/Transforms/InstCombine/high-bit-signmask.ll<br>
llvm/test/Transforms/InstCombine/sub-of-negatible.ll<br>
llvm/test/Transforms/InstCombine/sub.ll<br>
llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Transforms/InstCombine/CMakeLists.txt b/llvm/lib/Transforms/InstCombine/CMakeLists.txt<br>
index 2f19882c3316..1a34f22f064f 100644<br>
--- a/llvm/lib/Transforms/InstCombine/CMakeLists.txt<br>
+++ b/llvm/lib/Transforms/InstCombine/CMakeLists.txt<br>
@@ -12,6 +12,7 @@ add_llvm_component_library(LLVMInstCombine<br>
InstCombineCompares.cpp<br>
InstCombineLoadStoreAlloca.cpp<br>
InstCombineMulDivRem.cpp<br>
+ InstCombineNegator.cpp<br>
InstCombinePHI.cpp<br>
InstCombineSelect.cpp<br>
InstCombineShifts.cpp<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp<br>
index 7ca287f07a11..16666fe9430e 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp<br>
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp<br>
@@ -1682,12 +1682,10 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {<br>
if (Instruction *X = foldVectorBinop(I))<br>
return X;<br>
<br>
- // (A*B)-(A*C) -> A*(B-C) etc<br>
- if (Value *V = SimplifyUsingDistributiveLaws(I))<br>
- return replaceInstUsesWith(I, V);<br>
+ Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);<br>
<br>
// If this is a 'B = x-(-A)', change to B = x+A.<br>
- Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);<br>
+ // We deal with this without involving Negator to preserve NSW flag.<br>
if (Value *V = dyn_castNegVal(Op1)) {<br>
BinaryOperator *Res = BinaryOperator::CreateAdd(Op0, V);<br>
<br>
@@ -1704,6 +1702,45 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {<br>
return Res;<br>
}<br>
<br>
+ auto TryToNarrowDeduceFlags = [this, &I, &Op0, &Op1]() -> Instruction * {<br>
+ if (Instruction *Ext = narrowMathIfNoOverflow(I))<br>
+ return Ext;<br>
+<br>
+ bool Changed = false;<br>
+ if (!I.hasNoSignedWrap() && willNotOverflowSignedSub(Op0, Op1, I)) {<br>
+ Changed = true;<br>
+ I.setHasNoSignedWrap(true);<br>
+ }<br>
+ if (!I.hasNoUnsignedWrap() && willNotOverflowUnsignedSub(Op0, Op1, I)) {<br>
+ Changed = true;<br>
+ I.setHasNoUnsignedWrap(true);<br>
+ }<br>
+<br>
+ return Changed ? &I : nullptr;<br>
+ };<br>
+<br>
+ // First, let's try to interpret `sub a, b` as `add a, (sub 0, b)`,<br>
+ // and let's try to sink `(sub 0, b)` into `b` itself. But only if this isn't<br>
+ // a pure negation used by a select that looks like abs/nabs.<br>
+ bool IsNegation = match(Op0, m_ZeroInt());<br>
+ if (!IsNegation || none_of(I.users(), [&I, Op1](const User *U) {<br>
+ const Instruction *UI = dyn_cast<Instruction>(U);<br>
+ if (!UI)<br>
+ return false;<br>
+ return match(UI,<br>
+ m_Select(m_Value(), m_Specific(Op1), m_Specific(&I))) ||<br>
+ match(UI, m_Select(m_Value(), m_Specific(&I), m_Specific(Op1)));<br>
+ })) {<br>
+ if (Value *NegOp1 = Negator::Negate(IsNegation, Op1, *this))<br>
+ return BinaryOperator::CreateAdd(NegOp1, Op0);<br>
+ }<br>
+ if (IsNegation)<br>
+ return TryToNarrowDeduceFlags(); // Should have been handled in Negator!<br>
+<br>
+ // (A*B)-(A*C) -> A*(B-C) etc<br>
+ if (Value *V = SimplifyUsingDistributiveLaws(I))<br>
+ return replaceInstUsesWith(I, V);<br>
+<br>
if (I.getType()->isIntOrIntVectorTy(1))<br>
return BinaryOperator::CreateXor(Op0, Op1);<br>
<br>
@@ -1720,22 +1757,7 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {<br>
if (match(Op0, m_OneUse(m_Add(m_Value(X), m_AllOnes()))))<br>
return BinaryOperator::CreateAdd(Builder.CreateNot(Op1), X);<br>
<br>
- // Y - (X + 1) --> ~X + Y<br>
- if (match(Op1, m_OneUse(m_Add(m_Value(X), m_One()))))<br>
- return BinaryOperator::CreateAdd(Builder.CreateNot(X), Op0);<br>
-<br>
- // Y - ~X --> (X + 1) + Y<br>
- if (match(Op1, m_OneUse(m_Not(m_Value(X))))) {<br>
- return BinaryOperator::CreateAdd(<br>
- Builder.CreateAdd(Op0, ConstantInt::get(I.getType(), 1)), X);<br>
- }<br>
-<br>
if (Constant *C = dyn_cast<Constant>(Op0)) {<br>
- // -f(x) -> f(-x) if possible.<br>
- if (match(C, m_Zero()))<br>
- if (Value *Neg = freelyNegateValue(Op1))<br>
- return replaceInstUsesWith(I, Neg);<br>
-<br>
Value *X;<br>
if (match(Op1, m_ZExt(m_Value(X))) && X->getType()->isIntOrIntVectorTy(1))<br>
// C - (zext bool) --> bool ? C - 1 : C<br>
@@ -1770,26 +1792,12 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {<br>
}<br>
<br>
const APInt *Op0C;<br>
- if (match(Op0, m_APInt(Op0C))) {<br>
- if (Op0C->isNullValue() && Op1->hasOneUse()) {<br>
- Value *LHS, *RHS;<br>
- SelectPatternFlavor SPF = matchSelectPattern(Op1, LHS, RHS).Flavor;<br>
- if (SPF == SPF_ABS || SPF == SPF_NABS) {<br>
- // This is a negate of an ABS/NABS pattern. Just swap the operands<br>
- // of the select.<br>
- cast<SelectInst>(Op1)->swapValues();<br>
- // Don't swap prof metadata, we didn't change the branch behavior.<br>
- return replaceInstUsesWith(I, Op1);<br>
- }<br>
- }<br>
-<br>
+ if (match(Op0, m_APInt(Op0C)) && Op0C->isMask()) {<br>
// Turn this into a xor if LHS is 2^n-1 and the remaining bits are known<br>
// zero.<br>
- if (Op0C->isMask()) {<br>
- KnownBits RHSKnown = computeKnownBits(Op1, 0, &I);<br>
- if ((*Op0C | RHSKnown.Zero).isAllOnesValue())<br>
- return BinaryOperator::CreateXor(Op1, Op0);<br>
- }<br>
+ KnownBits RHSKnown = computeKnownBits(Op1, 0, &I);<br>
+ if ((*Op0C | RHSKnown.Zero).isAllOnesValue())<br>
+ return BinaryOperator::CreateXor(Op1, Op0);<br>
}<br>
<br>
{<br>
@@ -1919,49 +1927,6 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {<br>
return BinaryOperator::CreateAnd(<br>
Op0, Builder.CreateNot(Y, Y->getName() + ".not"));<br>
<br>
- if (Op1->hasOneUse()) {<br>
- Value *Y = nullptr, *Z = nullptr;<br>
- Constant *C = nullptr;<br>
-<br>
- // (X - (Y - Z)) --> (X + (Z - Y)).<br>
- if (match(Op1, m_Sub(m_Value(Y), m_Value(Z))))<br>
- return BinaryOperator::CreateAdd(Op0,<br>
- Builder.CreateSub(Z, Y, Op1->getName()));<br>
-<br>
- // Subtracting -1/0 is the same as adding 1/0:<br>
- // sub [nsw] Op0, sext(bool Y) -> add [nsw] Op0, zext(bool Y)<br>
- // 'nuw' is dropped in favor of the canonical form.<br>
- if (match(Op1, m_SExt(m_Value(Y))) &&<br>
- Y->getType()->getScalarSizeInBits() == 1) {<br>
- Value *Zext = Builder.CreateZExt(Y, I.getType());<br>
- BinaryOperator *Add = BinaryOperator::CreateAdd(Op0, Zext);<br>
- Add->setHasNoSignedWrap(I.hasNoSignedWrap());<br>
- return Add;<br>
- }<br>
- // sub [nsw] X, zext(bool Y) -> add [nsw] X, sext(bool Y)<br>
- // 'nuw' is dropped in favor of the canonical form.<br>
- if (match(Op1, m_ZExt(m_Value(Y))) && Y->getType()->isIntOrIntVectorTy(1)) {<br>
- Value *Sext = Builder.CreateSExt(Y, I.getType());<br>
- BinaryOperator *Add = BinaryOperator::CreateAdd(Op0, Sext);<br>
- Add->setHasNoSignedWrap(I.hasNoSignedWrap());<br>
- return Add;<br>
- }<br>
-<br>
- // X - A*-B -> X + A*B<br>
- // X - -A*B -> X + A*B<br>
- Value *A, *B;<br>
- if (match(Op1, m_c_Mul(m_Value(A), m_Neg(m_Value(B)))))<br>
- return BinaryOperator::CreateAdd(Op0, Builder.CreateMul(A, B));<br>
-<br>
- // X - A*C -> X + A*-C<br>
- // No need to handle commuted multiply because multiply handling will<br>
- // ensure constant will be move to the right hand side.<br>
- if (match(Op1, m_Mul(m_Value(A), m_Constant(C))) && !isa<ConstantExpr>(C)) {<br>
- Value *NewMul = Builder.CreateMul(A, ConstantExpr::getNeg(C));<br>
- return BinaryOperator::CreateAdd(Op0, NewMul);<br>
- }<br>
- }<br>
-<br>
{<br>
// ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A<br>
// ~A - Min/Max(O, ~A) -> Max/Min(A, ~O) - A<br>
@@ -2036,20 +2001,7 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {<br>
canonicalizeCondSignextOfHighBitExtractToSignextHighBitExtract(I))<br>
return V;<br>
<br>
- if (Instruction *Ext = narrowMathIfNoOverflow(I))<br>
- return Ext;<br>
-<br>
- bool Changed = false;<br>
- if (!I.hasNoSignedWrap() && willNotOverflowSignedSub(Op0, Op1, I)) {<br>
- Changed = true;<br>
- I.setHasNoSignedWrap(true);<br>
- }<br>
- if (!I.hasNoUnsignedWrap() && willNotOverflowUnsignedSub(Op0, Op1, I)) {<br>
- Changed = true;<br>
- I.setHasNoUnsignedWrap(true);<br>
- }<br>
-<br>
- return Changed ? &I : nullptr;<br>
+ return TryToNarrowDeduceFlags();<br>
}<br>
<br>
/// This eliminates floating-point negation in either 'fneg(X)' or<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
index 6544fd4ee8da..a908349eaff1 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
+++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h<br>
@@ -16,6 +16,7 @@<br>
#define LLVM_LIB_TRANSFORMS_INSTCOMBINE_INSTCOMBINEINTERNAL_H<br>
<br>
#include "llvm/ADT/ArrayRef.h"<br>
+#include "llvm/ADT/Statistic.h"<br>
#include "llvm/Analysis/AliasAnalysis.h"<br>
#include "llvm/Analysis/InstructionSimplify.h"<br>
#include "llvm/Analysis/TargetFolder.h"<br>
@@ -471,7 +472,6 @@ class LLVM_LIBRARY_VISIBILITY InstCombiner<br>
bool shouldChangeType(unsigned FromBitWidth, unsigned ToBitWidth) const;<br>
bool shouldChangeType(Type *From, Type *To) const;<br>
Value *dyn_castNegVal(Value *V) const;<br>
- Value *freelyNegateValue(Value *V);<br>
Type *FindElementAtOffset(PointerType *PtrTy, int64_t Offset,<br>
SmallVectorImpl<Value *> &NewIndices);<br>
<br>
@@ -513,7 +513,7 @@ class LLVM_LIBRARY_VISIBILITY InstCombiner<br>
Instruction *simplifyMaskedStore(IntrinsicInst &II);<br>
Instruction *simplifyMaskedGather(IntrinsicInst &II);<br>
Instruction *simplifyMaskedScatter(IntrinsicInst &II);<br>
- <br>
+<br>
/// Transform (zext icmp) to bitwise / integer operations in order to<br>
/// eliminate it.<br>
///<br>
@@ -1014,6 +1014,55 @@ class LLVM_LIBRARY_VISIBILITY InstCombiner<br>
Value *Descale(Value *Val, APInt Scale, bool &NoSignedWrap);<br>
};<br>
<br>
+namespace {<br>
+<br>
+// As a default, let's assume that we want to be aggressive,<br>
+// and attempt to traverse with no limits in attempt to sink negation.<br>
+static constexpr unsigned NegatorDefaultMaxDepth = ~0U;<br>
+<br>
+// Let's guesstimate that most often we will end up visiting/producing<br>
+// fairly small number of new instructions.<br>
+static constexpr unsigned NegatorMaxNodesSSO = 16;<br>
+<br>
+} // namespace<br>
+<br>
+class Negator final {<br>
+ /// Top-to-bottom, def-to-use negated instruction tree we produced.<br>
+ SmallVector<Instruction *, NegatorMaxNodesSSO> NewInstructions;<br>
+<br>
+ using BuilderTy = IRBuilder<TargetFolder, IRBuilderCallbackInserter>;<br>
+ BuilderTy Builder;<br>
+<br>
+ const bool IsTrulyNegation;<br>
+<br>
+ Negator(LLVMContext &C, const DataLayout &DL, bool IsTrulyNegation);<br>
+<br>
+#if LLVM_ENABLE_STATS<br>
+ unsigned NumValuesVisitedInThisNegator = 0;<br>
+ ~Negator();<br>
+#endif<br>
+<br>
+ using Result = std::pair<ArrayRef<Instruction *> /*NewInstructions*/,<br>
+ Value * /*NegatedRoot*/>;<br>
+<br>
+ LLVM_NODISCARD Value *visit(Value *V, unsigned Depth);<br>
+<br>
+ /// Recurse depth-first and attempt to sink the negation.<br>
+ /// FIXME: use worklist?<br>
+ LLVM_NODISCARD Optional<Result> run(Value *Root);<br>
+<br>
+ Negator(const Negator &) = delete;<br>
+ Negator(Negator &&) = delete;<br>
+ Negator &operator=(const Negator &) = delete;<br>
+ Negator &operator=(Negator &&) = delete;<br>
+<br>
+public:<br>
+ /// Attempt to negate \p Root. Retuns nullptr if negation can't be performed,<br>
+ /// otherwise returns negated value.<br>
+ LLVM_NODISCARD static Value *Negate(bool LHSIsZero, Value *Root,<br>
+ InstCombiner &IC);<br>
+};<br>
+<br>
} // end namespace llvm<br>
<br>
#undef DEBUG_TYPE<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp<br>
new file mode 100644<br>
index 000000000000..2655ef304787<br>
--- /dev/null<br>
+++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp<br>
@@ -0,0 +1,377 @@<br>
+//===- InstCombineNegator.cpp -----------------------------------*- C++ -*-===//<br>
+//<br>
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.<br>
+// See <a href="https://llvm.org/LICENSE.txt" rel="noreferrer" target="_blank">https://llvm.org/LICENSE.txt</a> for license information.<br>
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file implements sinking of negation into expression trees,<br>
+// as long as that can be done without increasing instruction count.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "InstCombineInternal.h"<br>
+#include "llvm/ADT/APInt.h"<br>
+#include "llvm/ADT/ArrayRef.h"<br>
+#include "llvm/ADT/None.h"<br>
+#include "llvm/ADT/Optional.h"<br>
+#include "llvm/ADT/STLExtras.h"<br>
+#include "llvm/ADT/SmallVector.h"<br>
+#include "llvm/ADT/Statistic.h"<br>
+#include "llvm/ADT/StringRef.h"<br>
+#include "llvm/ADT/Twine.h"<br>
+#include "llvm/ADT/iterator_range.h"<br>
+#include "llvm/Analysis/TargetFolder.h"<br>
+#include "llvm/Analysis/ValueTracking.h"<br>
+#include "llvm/IR/Constant.h"<br>
+#include "llvm/IR/Constants.h"<br>
+#include "llvm/IR/DebugLoc.h"<br>
+#include "llvm/IR/DerivedTypes.h"<br>
+#include "llvm/IR/IRBuilder.h"<br>
+#include "llvm/IR/Instruction.h"<br>
+#include "llvm/IR/Instructions.h"<br>
+#include "llvm/IR/PatternMatch.h"<br>
+#include "llvm/IR/Type.h"<br>
+#include "llvm/IR/Use.h"<br>
+#include "llvm/IR/User.h"<br>
+#include "llvm/IR/Value.h"<br>
+#include "llvm/Support/Casting.h"<br>
+#include "llvm/Support/CommandLine.h"<br>
+#include "llvm/Support/Compiler.h"<br>
+#include "llvm/Support/DebugCounter.h"<br>
+#include "llvm/Support/ErrorHandling.h"<br>
+#include "llvm/Support/raw_ostream.h"<br>
+#include <functional><br>
+#include <tuple><br>
+#include <utility><br>
+<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "instcombine"<br>
+<br>
+STATISTIC(NegatorTotalNegationsAttempted,<br>
+ "Negator: Number of negations attempted to be sinked");<br>
+STATISTIC(NegatorNumTreesNegated,<br>
+ "Negator: Number of negations successfully sinked");<br>
+STATISTIC(NegatorMaxDepthVisited, "Negator: Maximal traversal depth ever "<br>
+ "reached while attempting to sink negation");<br>
+STATISTIC(NegatorTimesDepthLimitReached,<br>
+ "Negator: How many times did the traversal depth limit was reached "<br>
+ "during sinking");<br>
+STATISTIC(<br>
+ NegatorNumValuesVisited,<br>
+ "Negator: Total number of values visited during attempts to sink negation");<br>
+STATISTIC(NegatorMaxTotalValuesVisited,<br>
+ "Negator: Maximal number of values ever visited while attempting to "<br>
+ "sink negation");<br>
+STATISTIC(NegatorNumInstructionsCreatedTotal,<br>
+ "Negator: Number of new negated instructions created, total");<br>
+STATISTIC(NegatorMaxInstructionsCreated,<br>
+ "Negator: Maximal number of new instructions created during negation "<br>
+ "attempt");<br>
+STATISTIC(NegatorNumInstructionsNegatedSuccess,<br>
+ "Negator: Number of new negated instructions created in successful "<br>
+ "negation sinking attempts");<br>
+<br>
+DEBUG_COUNTER(NegatorCounter, "instcombine-negator",<br>
+ "Controls Negator transformations in InstCombine pass");<br>
+<br>
+static cl::opt<bool><br>
+ NegatorEnabled("instcombine-negator-enabled", cl::init(true),<br>
+ cl::desc("Should we attempt to sink negations?"));<br>
+<br>
+static cl::opt<unsigned><br>
+ NegatorMaxDepth("instcombine-negator-max-depth",<br>
+ cl::init(NegatorDefaultMaxDepth),<br>
+ cl::desc("What is the maximal lookup depth when trying to "<br>
+ "check for viability of negation sinking."));<br>
+<br>
+Negator::Negator(LLVMContext &C, const DataLayout &DL, bool IsTrulyNegation_)<br>
+ : Builder(C, TargetFolder(DL),<br>
+ IRBuilderCallbackInserter([&](Instruction *I) {<br>
+ ++NegatorNumInstructionsCreatedTotal;<br>
+ NewInstructions.push_back(I);<br>
+ })),<br>
+ IsTrulyNegation(IsTrulyNegation_) {}<br>
+<br>
+#if LLVM_ENABLE_STATS<br>
+Negator::~Negator() {<br>
+ NegatorMaxTotalValuesVisited.updateMax(NumValuesVisitedInThisNegator);<br>
+}<br>
+#endif<br>
+<br>
+// FIXME: can this be reworked into a worklist-based algorithm while preserving<br>
+// the depth-first, early bailout traversal?<br>
+LLVM_NODISCARD Value *Negator::visit(Value *V, unsigned Depth) {<br>
+ NegatorMaxDepthVisited.updateMax(Depth);<br>
+ ++NegatorNumValuesVisited;<br>
+<br>
+#if LLVM_ENABLE_STATS<br>
+ ++NumValuesVisitedInThisNegator;<br>
+#endif<br>
+<br>
+ // In i1, negation can simply be ignored.<br>
+ if (V->getType()->isIntOrIntVectorTy(1))<br>
+ return V;<br>
+<br>
+ Value *X;<br>
+<br>
+ // -(-(X)) -> X.<br>
+ if (match(V, m_Neg(m_Value(X))))<br>
+ return X;<br>
+<br>
+ // Integral constants can be freely negated.<br>
+ if (match(V, m_AnyIntegralConstant()))<br>
+ return ConstantExpr::getNeg(cast<Constant>(V), /*HasNUW=*/false,<br>
+ /*HasNSW=*/false);<br>
+<br>
+ // If we have a non-instruction, then give up.<br>
+ if (!isa<Instruction>(V))<br>
+ return nullptr;<br>
+<br>
+ // If we have started with a true negation (i.e. `sub 0, %y`), then if we've<br>
+ // got instruction that does not require recursive reasoning, we can still<br>
+ // negate it even if it has other uses, without increasing instruction count.<br>
+ if (!V->hasOneUse() && !IsTrulyNegation)<br>
+ return nullptr;<br>
+<br>
+ auto *I = cast<Instruction>(V);<br>
+ unsigned BitWidth = I->getType()->getScalarSizeInBits();<br>
+<br>
+ // We must preserve the insertion point and debug info that is set in the<br>
+ // builder at the time this function is called.<br>
+ InstCombiner::BuilderTy::InsertPointGuard Guard(Builder);<br>
+ // And since we are trying to negate instruction I, that tells us about the<br>
+ // insertion point and the debug info that we need to keep.<br>
+ Builder.SetInsertPoint(I);<br>
+<br>
+ // In some cases we can give the answer without further recursion.<br>
+ switch (I->getOpcode()) {<br>
+ case Instruction::Sub:<br>
+ // `sub` is always negatible.<br>
+ return Builder.CreateSub(I->getOperand(1), I->getOperand(0),<br>
+ I->getName() + ".neg");<br>
+ case Instruction::Add:<br>
+ // `inc` is always negatible.<br>
+ if (match(I->getOperand(1), m_One()))<br>
+ return Builder.CreateNot(I->getOperand(0), I->getName() + ".neg");<br>
+ break;<br>
+ case Instruction::Xor:<br>
+ // `not` is always negatible.<br>
+ if (match(I, m_Not(m_Value(X))))<br>
+ return Builder.CreateAdd(X, ConstantInt::get(X->getType(), 1),<br>
+ I->getName() + ".neg");<br>
+ break;<br>
+ case Instruction::AShr:<br>
+ case Instruction::LShr: {<br>
+ // Right-shift sign bit smear is negatible.<br>
+ const APInt *Op1Val;<br>
+ if (match(I->getOperand(1), m_APInt(Op1Val)) && *Op1Val == BitWidth - 1) {<br>
+ Value *BO = I->getOpcode() == Instruction::AShr<br>
+ ? Builder.CreateLShr(I->getOperand(0), I->getOperand(1))<br>
+ : Builder.CreateAShr(I->getOperand(0), I->getOperand(1));<br>
+ if (auto *NewInstr = dyn_cast<Instruction>(BO)) {<br>
+ NewInstr->copyIRFlags(I);<br>
+ NewInstr->setName(I->getName() + ".neg");<br>
+ }<br>
+ return BO;<br>
+ }<br>
+ break;<br>
+ }<br>
+ case Instruction::SDiv:<br>
+ // `sdiv` is negatible if divisor is not undef/INT_MIN/1.<br>
+ // While this is normally not behind a use-check,<br>
+ // let's consider division to be special since it's costly.<br>
+ if (!I->hasOneUse())<br>
+ break;<br>
+ if (auto *Op1C = dyn_cast<Constant>(I->getOperand(1))) {<br>
+ if (!Op1C->containsUndefElement() && Op1C->isNotMinSignedValue() &&<br>
+ Op1C->isNotOneValue()) {<br>
+ Value *BO =<br>
+ Builder.CreateSDiv(I->getOperand(0), ConstantExpr::getNeg(Op1C),<br>
+ I->getName() + ".neg");<br>
+ if (auto *NewInstr = dyn_cast<Instruction>(BO))<br>
+ NewInstr->setIsExact(I->isExact());<br>
+ return BO;<br>
+ }<br>
+ }<br>
+ break;<br>
+ case Instruction::SExt:<br>
+ case Instruction::ZExt:<br>
+ // `*ext` of i1 is always negatible<br>
+ if (I->getOperand(0)->getType()->isIntOrIntVectorTy(1))<br>
+ return I->getOpcode() == Instruction::SExt<br>
+ ? Builder.CreateZExt(I->getOperand(0), I->getType(),<br>
+ I->getName() + ".neg")<br>
+ : Builder.CreateSExt(I->getOperand(0), I->getType(),<br>
+ I->getName() + ".neg");<br>
+ break;<br>
+ default:<br>
+ break; // Other instructions require recursive reasoning.<br>
+ }<br>
+<br>
+ // Rest of the logic is recursive, and if either the current instruction<br>
+ // has other uses or if it's time to give up then it's time.<br>
+ if (!V->hasOneUse())<br>
+ return nullptr;<br>
+ if (Depth > NegatorMaxDepth) {<br>
+ LLVM_DEBUG(dbgs() << "Negator: reached maximal allowed traversal depth in "<br>
+ << *V << ". Giving up.\n");<br>
+ ++NegatorTimesDepthLimitReached;<br>
+ return nullptr;<br>
+ }<br>
+<br>
+ switch (I->getOpcode()) {<br>
+ case Instruction::PHI: {<br>
+ // `phi` is negatible if all the incoming values are negatible.<br>
+ PHINode *PHI = cast<PHINode>(I);<br>
+ SmallVector<Value *, 4> NegatedIncomingValues(PHI->getNumOperands());<br>
+ for (auto I : zip(PHI->incoming_values(), NegatedIncomingValues)) {<br>
+ if (!(std::get<1>(I) = visit(std::get<0>(I), Depth + 1))) // Early return.<br>
+ return nullptr;<br>
+ }<br>
+ // All incoming values are indeed negatible. Create negated PHI node.<br>
+ PHINode *NegatedPHI = Builder.CreatePHI(<br>
+ PHI->getType(), PHI->getNumOperands(), PHI->getName() + ".neg");<br>
+ for (auto I : zip(NegatedIncomingValues, PHI->blocks()))<br>
+ NegatedPHI->addIncoming(std::get<0>(I), std::get<1>(I));<br>
+ return NegatedPHI;<br>
+ }<br>
+ case Instruction::Select: {<br>
+ {<br>
+ // `abs`/`nabs` is always negatible.<br>
+ Value *LHS, *RHS;<br>
+ SelectPatternFlavor SPF =<br>
+ matchSelectPattern(I, LHS, RHS, /*CastOp=*/nullptr, Depth).Flavor;<br>
+ if (SPF == SPF_ABS || SPF == SPF_NABS) {<br>
+ auto *NewSelect = cast<SelectInst>(I->clone());<br>
+ // Just swap the operands of the select.<br>
+ NewSelect->swapValues();<br>
+ // Don't swap prof metadata, we didn't change the branch behavior.<br>
+ NewSelect->setName(I->getName() + ".neg");<br>
+ Builder.Insert(NewSelect);<br>
+ return NewSelect;<br>
+ }<br>
+ }<br>
+ // `select` is negatible if both hands of `select` are negatible.<br>
+ Value *NegOp1 = visit(I->getOperand(1), Depth + 1);<br>
+ if (!NegOp1) // Early return.<br>
+ return nullptr;<br>
+ Value *NegOp2 = visit(I->getOperand(2), Depth + 1);<br>
+ if (!NegOp2)<br>
+ return nullptr;<br>
+ // Do preserve the metadata!<br>
+ return Builder.CreateSelect(I->getOperand(0), NegOp1, NegOp2,<br>
+ I->getName() + ".neg", /*MDFrom=*/I);<br>
+ }<br>
+ case Instruction::Trunc: {<br>
+ // `trunc` is negatible if its operand is negatible.<br>
+ Value *NegOp = visit(I->getOperand(0), Depth + 1);<br>
+ if (!NegOp) // Early return.<br>
+ return nullptr;<br>
+ return Builder.CreateTrunc(NegOp, I->getType(), I->getName() + ".neg");<br>
+ }<br>
+ case Instruction::Shl: {<br>
+ // `shl` is negatible if the first operand is negatible.<br>
+ Value *NegOp0 = visit(I->getOperand(0), Depth + 1);<br>
+ if (!NegOp0) // Early return.<br>
+ return nullptr;<br>
+ return Builder.CreateShl(NegOp0, I->getOperand(1), I->getName() + ".neg");<br>
+ }<br>
+ case Instruction::Add: {<br>
+ // `add` is negatible if both of its operands are negatible.<br>
+ Value *NegOp0 = visit(I->getOperand(0), Depth + 1);<br>
+ if (!NegOp0) // Early return.<br>
+ return nullptr;<br>
+ Value *NegOp1 = visit(I->getOperand(1), Depth + 1);<br>
+ if (!NegOp1)<br>
+ return nullptr;<br>
+ return Builder.CreateAdd(NegOp0, NegOp1, I->getName() + ".neg");<br>
+ }<br>
+ case Instruction::Xor:<br>
+ // `xor` is negatible if one of its operands is invertible.<br>
+ // FIXME: InstCombineInverter? But how to connect Inverter and Negator?<br>
+ if (auto *C = dyn_cast<Constant>(I->getOperand(1))) {<br>
+ Value *Xor = Builder.CreateXor(I->getOperand(0), ConstantExpr::getNot(C));<br>
+ return Builder.CreateAdd(Xor, ConstantInt::get(Xor->getType(), 1),<br>
+ I->getName() + ".neg");<br>
+ }<br>
+ return nullptr;<br>
+ case Instruction::Mul: {<br>
+ // `mul` is negatible if one of its operands is negatible.<br>
+ Value *NegatedOp, *OtherOp;<br>
+ // First try the second operand, in case it's a constant it will be best to<br>
+ // just invert it instead of sinking the `neg` deeper.<br>
+ if (Value *NegOp1 = visit(I->getOperand(1), Depth + 1)) {<br>
+ NegatedOp = NegOp1;<br>
+ OtherOp = I->getOperand(0);<br>
+ } else if (Value *NegOp0 = visit(I->getOperand(0), Depth + 1)) {<br>
+ NegatedOp = NegOp0;<br>
+ OtherOp = I->getOperand(1);<br>
+ } else<br>
+ // Can't negate either of them.<br>
+ return nullptr;<br>
+ return Builder.CreateMul(NegatedOp, OtherOp, I->getName() + ".neg");<br>
+ }<br>
+ default:<br>
+ return nullptr; // Don't know, likely not negatible for free.<br>
+ }<br>
+<br>
+ llvm_unreachable("Can't get here. We always return from switch.");<br>
+};<br>
+<br>
+LLVM_NODISCARD Optional<Negator::Result> Negator::run(Value *Root) {<br>
+ Value *Negated = visit(Root, /*Depth=*/0);<br>
+ if (!Negated) {<br>
+ // We must cleanup newly-inserted instructions, to avoid any potential<br>
+ // endless combine looping.<br>
+ llvm::for_each(llvm::reverse(NewInstructions),<br>
+ [&](Instruction *I) { I->eraseFromParent(); });<br>
+ return llvm::None;<br>
+ }<br>
+ return std::make_pair(ArrayRef<Instruction *>(NewInstructions), Negated);<br>
+};<br>
+<br>
+LLVM_NODISCARD Value *Negator::Negate(bool LHSIsZero, Value *Root,<br>
+ InstCombiner &IC) {<br>
+ ++NegatorTotalNegationsAttempted;<br>
+ LLVM_DEBUG(dbgs() << "Negator: attempting to sink negation into " << *Root<br>
+ << "\n");<br>
+<br>
+ if (!NegatorEnabled || !DebugCounter::shouldExecute(NegatorCounter))<br>
+ return nullptr;<br>
+<br>
+ Negator N(Root->getContext(), IC.getDataLayout(), LHSIsZero);<br>
+ Optional<Result> Res = N.run(Root);<br>
+ if (!Res) { // Negation failed.<br>
+ LLVM_DEBUG(dbgs() << "Negator: failed to sink negation into " << *Root<br>
+ << "\n");<br>
+ return nullptr;<br>
+ }<br>
+<br>
+ LLVM_DEBUG(dbgs() << "Negator: successfully sunk negation into " << *Root<br>
+ << "\n NEW: " << *Res->second << "\n");<br>
+ ++NegatorNumTreesNegated;<br>
+<br>
+ // We must temporarily unset the 'current' insertion point and DebugLoc of the<br>
+ // InstCombine's IRBuilder so that it won't interfere with the ones we have<br>
+ // already specified when producing negated instructions.<br>
+ InstCombiner::BuilderTy::InsertPointGuard Guard(IC.Builder);<br>
+ IC.Builder.ClearInsertionPoint();<br>
+ IC.Builder.SetCurrentDebugLocation(DebugLoc());<br>
+<br>
+ // And finally, we must add newly-created instructions into the InstCombine's<br>
+ // worklist (in a proper order!) so it can attempt to combine them.<br>
+ LLVM_DEBUG(dbgs() << "Negator: Propagating " << Res->first.size()<br>
+ << " instrs to InstCombine\n");<br>
+ NegatorMaxInstructionsCreated.updateMax(Res->first.size());<br>
+ NegatorNumInstructionsNegatedSuccess += Res->first.size();<br>
+<br>
+ // They are in def-use order, so nothing fancy, just insert them in order.<br>
+ llvm::for_each(Res->first,<br>
+ [&](Instruction *I) { IC.Builder.Insert(I, I->getName()); });<br>
+<br>
+ // And return the new root.<br>
+ return Res->second;<br>
+};<br>
<br>
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
index 4d286f19f919..88cb8d5300b9 100644<br>
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp<br>
@@ -853,120 +853,6 @@ Value *InstCombiner::dyn_castNegVal(Value *V) const {<br>
return nullptr;<br>
}<br>
<br>
-/// Get negated V (that is 0-V) without increasing instruction count,<br>
-/// assuming that the original V will become unused.<br>
-Value *InstCombiner::freelyNegateValue(Value *V) {<br>
- if (Value *NegV = dyn_castNegVal(V))<br>
- return NegV;<br>
-<br>
- Instruction *I = dyn_cast<Instruction>(V);<br>
- if (!I)<br>
- return nullptr;<br>
-<br>
- unsigned BitWidth = I->getType()->getScalarSizeInBits();<br>
- switch (I->getOpcode()) {<br>
- // 0-(zext i1 A) => sext i1 A<br>
- case Instruction::ZExt:<br>
- if (I->getOperand(0)->getType()->isIntOrIntVectorTy(1))<br>
- return Builder.CreateSExtOrBitCast(<br>
- I->getOperand(0), I->getType(), I->getName() + ".neg");<br>
- return nullptr;<br>
-<br>
- // 0-(sext i1 A) => zext i1 A<br>
- case Instruction::SExt:<br>
- if (I->getOperand(0)->getType()->isIntOrIntVectorTy(1))<br>
- return Builder.CreateZExtOrBitCast(<br>
- I->getOperand(0), I->getType(), I->getName() + ".neg");<br>
- return nullptr;<br>
-<br>
- // 0-(A lshr (BW-1)) => A ashr (BW-1)<br>
- case Instruction::LShr:<br>
- if (match(I->getOperand(1), m_SpecificInt(BitWidth - 1)))<br>
- return Builder.CreateAShr(<br>
- I->getOperand(0), I->getOperand(1),<br>
- I->getName() + ".neg", cast<BinaryOperator>(I)->isExact());<br>
- return nullptr;<br>
-<br>
- // 0-(A ashr (BW-1)) => A lshr (BW-1)<br>
- case Instruction::AShr:<br>
- if (match(I->getOperand(1), m_SpecificInt(BitWidth - 1)))<br>
- return Builder.CreateLShr(<br>
- I->getOperand(0), I->getOperand(1),<br>
- I->getName() + ".neg", cast<BinaryOperator>(I)->isExact());<br>
- return nullptr;<br>
-<br>
- // Negation is equivalent to bitwise-not + 1.<br>
- case Instruction::Xor: {<br>
- // Special case for negate of 'not' - replace with increment:<br>
- // 0 - (~A) => ((A ^ -1) ^ -1) + 1 => A + 1<br>
- Value *A;<br>
- if (match(I, m_Not(m_Value(A))))<br>
- return Builder.CreateAdd(A, ConstantInt::get(A->getType(), 1),<br>
- I->getName() + ".neg");<br>
-<br>
- // General case xor (not a 'not') requires creating a new xor, so this has a<br>
- // one-use limitation:<br>
- // 0 - (A ^ C) => ((A ^ C) ^ -1) + 1 => A ^ ~C + 1<br>
- Constant *C;<br>
- if (match(I, m_OneUse(m_Xor(m_Value(A), m_Constant(C))))) {<br>
- Value *Xor = Builder.CreateXor(A, ConstantExpr::getNot(C));<br>
- return Builder.CreateAdd(Xor, ConstantInt::get(Xor->getType(), 1),<br>
- I->getName() + ".neg");<br>
- }<br>
- return nullptr;<br>
- }<br>
-<br>
- default:<br>
- break;<br>
- }<br>
-<br>
- // TODO: The "sub" pattern below could also be applied without the one-use<br>
- // restriction. Not allowing it for now in line with existing behavior.<br>
- if (!I->hasOneUse())<br>
- return nullptr;<br>
-<br>
- switch (I->getOpcode()) {<br>
- // 0-(A-B) => B-A<br>
- case Instruction::Sub:<br>
- return Builder.CreateSub(<br>
- I->getOperand(1), I->getOperand(0), I->getName() + ".neg");<br>
-<br>
- // 0-(A sdiv C) => A sdiv (0-C) provided the negation doesn't overflow.<br>
- case Instruction::SDiv: {<br>
- Constant *C = dyn_cast<Constant>(I->getOperand(1));<br>
- if (C && !C->containsUndefElement() && C->isNotMinSignedValue() &&<br>
- C->isNotOneValue())<br>
- return Builder.CreateSDiv(I->getOperand(0), ConstantExpr::getNeg(C),<br>
- I->getName() + ".neg", cast<BinaryOperator>(I)->isExact());<br>
- return nullptr;<br>
- }<br>
-<br>
- // 0-(A<<B) => (0-A)<<B<br>
- case Instruction::Shl:<br>
- if (Value *NegA = freelyNegateValue(I->getOperand(0)))<br>
- return Builder.CreateShl(NegA, I->getOperand(1), I->getName() + ".neg");<br>
- return nullptr;<br>
-<br>
- // 0-(trunc A) => trunc (0-A)<br>
- case Instruction::Trunc:<br>
- if (Value *NegA = freelyNegateValue(I->getOperand(0)))<br>
- return Builder.CreateTrunc(NegA, I->getType(), I->getName() + ".neg");<br>
- return nullptr;<br>
-<br>
- // 0-(A*B) => (0-A)*B<br>
- // 0-(A*B) => A*(0-B)<br>
- case Instruction::Mul:<br>
- if (Value *NegA = freelyNegateValue(I->getOperand(0)))<br>
- return Builder.CreateMul(NegA, I->getOperand(1), V->getName() + ".neg");<br>
- if (Value *NegB = freelyNegateValue(I->getOperand(1)))<br>
- return Builder.CreateMul(I->getOperand(0), NegB, V->getName() + ".neg");<br>
- return nullptr;<br>
-<br>
- default:<br>
- return nullptr;<br>
- }<br>
-}<br>
-<br>
static Value *foldOperationIntoSelectOperand(Instruction &I, Value *SO,<br>
InstCombiner::BuilderTy &Builder) {<br>
if (auto *Cast = dyn_cast<CastInst>(&I))<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll<br>
index 175103886ff4..efc22068d9ee 100644<br>
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll<br>
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll<br>
@@ -210,12 +210,20 @@ define void @simplify_before_foldAndOfICmps() {<br>
; CHECK-LABEL: @simplify_before_foldAndOfICmps(<br>
; CHECK-NEXT: [[A8:%.*]] = alloca i16, align 2<br>
; CHECK-NEXT: [[L7:%.*]] = load i16, i16* [[A8]], align 2<br>
-; CHECK-NEXT: [[C10:%.*]] = icmp ult i16 [[L7]], 2<br>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[L7]], -1<br>
+; CHECK-NEXT: [[B11:%.*]] = zext i1 [[TMP1]] to i16<br>
+; CHECK-NEXT: [[C10:%.*]] = icmp ugt i16 [[L7]], [[B11]]<br>
+; CHECK-NEXT: [[C5:%.*]] = icmp slt i16 [[L7]], 1<br>
+; CHECK-NEXT: [[C11:%.*]] = icmp ne i16 [[L7]], 0<br>
; CHECK-NEXT: [[C7:%.*]] = icmp slt i16 [[L7]], 0<br>
-; CHECK-NEXT: [[C18:%.*]] = or i1 [[C7]], [[C10]]<br>
-; CHECK-NEXT: [[L7_LOBIT:%.*]] = ashr i16 [[L7]], 15<br>
-; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[L7_LOBIT]] to i64<br>
-; CHECK-NEXT: [[G26:%.*]] = getelementptr i1, i1* null, i64 [[TMP1]]<br>
+; CHECK-NEXT: [[B15:%.*]] = xor i1 [[C7]], [[C10]]<br>
+; CHECK-NEXT: [[B19:%.*]] = xor i1 [[C11]], [[B15]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C10]], [[C5]]<br>
+; CHECK-NEXT: [[C3:%.*]] = and i1 [[TMP2]], [[B19]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[C10]], true<br>
+; CHECK-NEXT: [[C18:%.*]] = or i1 [[C7]], [[TMP3]]<br>
+; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[C3]] to i64<br>
+; CHECK-NEXT: [[G26:%.*]] = getelementptr i1, i1* null, i64 [[TMP4]]<br>
; CHECK-NEXT: store i16 [[L7]], i16* undef, align 2<br>
; CHECK-NEXT: store i1 [[C18]], i1* undef, align 1<br>
; CHECK-NEXT: store i1* [[G26]], i1** undef, align 8<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll b/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll<br>
index cf9d051d125b..49d4ec43768b 100644<br>
--- a/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll<br>
+++ b/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll<br>
@@ -13,8 +13,8 @@<br>
<br>
define i32 @p0_scalar(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @p0_scalar(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 1<br>
-; CHECK-NEXT: [[T1:%.*]] = add i32 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = add i32 [[X:%.*]], 1<br>
+; CHECK-NEXT: [[T1:%.*]] = add i32 [[T0_NEG]], [[Y:%.*]]<br>
; CHECK-NEXT: ret i32 [[T1]]<br>
;<br>
%t0 = xor i32 %x, -1<br>
@@ -28,8 +28,8 @@ define i32 @p0_scalar(i32 %x, i32 %y) {<br>
<br>
define <4 x i32> @p1_vector_splat(<4 x i32> %x, <4 x i32> %y) {<br>
; CHECK-LABEL: @p1_vector_splat(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1, i32 1><br>
-; CHECK-NEXT: [[T1:%.*]] = add <4 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = add <4 x i32> [[X:%.*]], <i32 1, i32 1, i32 1, i32 1><br>
+; CHECK-NEXT: [[T1:%.*]] = add <4 x i32> [[T0_NEG]], [[Y:%.*]]<br>
; CHECK-NEXT: ret <4 x i32> [[T1]]<br>
;<br>
%t0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1><br>
@@ -39,8 +39,8 @@ define <4 x i32> @p1_vector_splat(<4 x i32> %x, <4 x i32> %y) {<br>
<br>
define <4 x i32> @p2_vector_undef(<4 x i32> %x, <4 x i32> %y) {<br>
; CHECK-LABEL: @p2_vector_undef(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1, i32 1><br>
-; CHECK-NEXT: [[T1:%.*]] = add <4 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = add <4 x i32> [[X:%.*]], <i32 1, i32 1, i32 1, i32 1><br>
+; CHECK-NEXT: [[T1:%.*]] = add <4 x i32> [[T0_NEG]], [[Y:%.*]]<br>
; CHECK-NEXT: ret <4 x i32> [[T1]]<br>
;<br>
%t0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 undef, i32 -1><br>
@@ -85,8 +85,8 @@ define i32 @n4(i32 %x, i32 %y) {<br>
<br>
define i32 @n5_is_not_not(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @n5_is_not_not(<br>
-; CHECK-NEXT: [[T0:%.*]] = xor i32 [[X:%.*]], 2147483647<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i32 [[Y:%.*]], [[T0]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = add i32 [[X:%.*]], -2147483647<br>
+; CHECK-NEXT: [[T1:%.*]] = add i32 [[T0_NEG]], [[Y:%.*]]<br>
; CHECK-NEXT: ret i32 [[T1]]<br>
;<br>
%t0 = xor i32 %x, 2147483647 ; not -1<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll b/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll<br>
index 034c285dd1ff..b9bce627d2ab 100644<br>
--- a/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll<br>
+++ b/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll<br>
@@ -3,9 +3,9 @@<br>
<br>
define i32 @t0(i64 %x) {<br>
; CHECK-LABEL: @t0(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = ashr i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32<br>
-; CHECK-NEXT: ret i32 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32<br>
+; CHECK-NEXT: ret i32 [[T1_NEG]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
%t1 = trunc i64 %t0 to i32<br>
@@ -14,9 +14,9 @@ define i32 @t0(i64 %x) {<br>
}<br>
define i32 @t1_exact(i64 %x) {<br>
; CHECK-LABEL: @t1_exact(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32<br>
-; CHECK-NEXT: ret i32 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr exact i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32<br>
+; CHECK-NEXT: ret i32 [[T1_NEG]]<br>
;<br>
%t0 = lshr exact i64 %x, 63<br>
%t1 = trunc i64 %t0 to i32<br>
@@ -25,9 +25,9 @@ define i32 @t1_exact(i64 %x) {<br>
}<br>
define i32 @t2(i64 %x) {<br>
; CHECK-LABEL: @t2(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32<br>
-; CHECK-NEXT: ret i32 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = lshr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32<br>
+; CHECK-NEXT: ret i32 [[T1_NEG]]<br>
;<br>
%t0 = ashr i64 %x, 63<br>
%t1 = trunc i64 %t0 to i32<br>
@@ -36,9 +36,9 @@ define i32 @t2(i64 %x) {<br>
}<br>
define i32 @t3_exact(i64 %x) {<br>
; CHECK-LABEL: @t3_exact(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32<br>
-; CHECK-NEXT: ret i32 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = lshr exact i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32<br>
+; CHECK-NEXT: ret i32 [[T1_NEG]]<br>
;<br>
%t0 = ashr exact i64 %x, 63<br>
%t1 = trunc i64 %t0 to i32<br>
@@ -48,9 +48,9 @@ define i32 @t3_exact(i64 %x) {<br>
<br>
define <2 x i32> @t4(<2 x i64> %x) {<br>
; CHECK-LABEL: @t4(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 63, i64 63><br>
-; CHECK-NEXT: [[R:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32><br>
-; CHECK-NEXT: ret <2 x i32> [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 63, i64 63><br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc <2 x i64> [[T0_NEG]] to <2 x i32><br>
+; CHECK-NEXT: ret <2 x i32> [[T1_NEG]]<br>
;<br>
%t0 = lshr <2 x i64> %x, <i64 63, i64 63><br>
%t1 = trunc <2 x i64> %t0 to <2 x i32><br>
@@ -76,11 +76,11 @@ declare void @use32(i32)<br>
<br>
define i32 @t6(i64 %x) {<br>
; CHECK-LABEL: @t6(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X]], 63<br>
; CHECK-NEXT: call void @use64(i64 [[T0]])<br>
-; CHECK-NEXT: [[TMP1:%.*]] = ashr i64 [[X]], 63<br>
-; CHECK-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32<br>
-; CHECK-NEXT: ret i32 [[R]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32<br>
+; CHECK-NEXT: ret i32 [[T1_NEG]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
call void @use64(i64 %t0)<br>
@@ -136,9 +136,9 @@ define i32 @n9(i64 %x) {<br>
<br>
define i32 @n10(i64 %x) {<br>
; CHECK-LABEL: @n10(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32<br>
-; CHECK-NEXT: [[R:%.*]] = xor i32 [[T1]], 1<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32<br>
+; CHECK-NEXT: [[R:%.*]] = add i32 [[T1_NEG]], 1<br>
; CHECK-NEXT: ret i32 [[R]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/high-bit-signmask.ll b/llvm/test/Transforms/InstCombine/high-bit-signmask.ll<br>
index 4a1b395ca35f..18a87273c021 100644<br>
--- a/llvm/test/Transforms/InstCombine/high-bit-signmask.ll<br>
+++ b/llvm/test/Transforms/InstCombine/high-bit-signmask.ll<br>
@@ -3,8 +3,8 @@<br>
<br>
define i64 @t0(i64 %x) {<br>
; CHECK-LABEL: @t0(<br>
-; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
%r = sub i64 0, %t0<br>
@@ -12,8 +12,8 @@ define i64 @t0(i64 %x) {<br>
}<br>
define i64 @t0_exact(i64 %x) {<br>
; CHECK-LABEL: @t0_exact(<br>
-; CHECK-NEXT: [[R:%.*]] = ashr exact i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr exact i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = lshr exact i64 %x, 63<br>
%r = sub i64 0, %t0<br>
@@ -21,8 +21,8 @@ define i64 @t0_exact(i64 %x) {<br>
}<br>
define i64 @t2(i64 %x) {<br>
; CHECK-LABEL: @t2(<br>
-; CHECK-NEXT: [[R:%.*]] = lshr i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = lshr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = ashr i64 %x, 63<br>
%r = sub i64 0, %t0<br>
@@ -30,8 +30,8 @@ define i64 @t2(i64 %x) {<br>
}<br>
define i64 @t3_exact(i64 %x) {<br>
; CHECK-LABEL: @t3_exact(<br>
-; CHECK-NEXT: [[R:%.*]] = lshr exact i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = lshr exact i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = ashr exact i64 %x, 63<br>
%r = sub i64 0, %t0<br>
@@ -40,8 +40,8 @@ define i64 @t3_exact(i64 %x) {<br>
<br>
define <2 x i64> @t4(<2 x i64> %x) {<br>
; CHECK-LABEL: @t4(<br>
-; CHECK-NEXT: [[R:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 63, i64 63><br>
-; CHECK-NEXT: ret <2 x i64> [[R]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 63, i64 63><br>
+; CHECK-NEXT: ret <2 x i64> [[T0_NEG]]<br>
;<br>
%t0 = lshr <2 x i64> %x, <i64 63, i64 63><br>
%r = sub <2 x i64> zeroinitializer, %t0<br>
@@ -64,10 +64,10 @@ declare void @use32(i64)<br>
<br>
define i64 @t6(i64 %x) {<br>
; CHECK-LABEL: @t6(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X]], 63<br>
; CHECK-NEXT: call void @use64(i64 [[T0]])<br>
-; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
call void @use64(i64 %t0)<br>
@@ -77,10 +77,10 @@ define i64 @t6(i64 %x) {<br>
<br>
define i64 @n7(i64 %x) {<br>
; CHECK-LABEL: @n7(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X]], 63<br>
; CHECK-NEXT: call void @use32(i64 [[T0]])<br>
-; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
call void @use32(i64 %t0)<br>
@@ -90,11 +90,11 @@ define i64 @n7(i64 %x) {<br>
<br>
define i64 @n8(i64 %x) {<br>
; CHECK-LABEL: @n8(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X]], 63<br>
; CHECK-NEXT: call void @use64(i64 [[T0]])<br>
; CHECK-NEXT: call void @use32(i64 [[T0]])<br>
-; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X]], 63<br>
-; CHECK-NEXT: ret i64 [[R]]<br>
+; CHECK-NEXT: ret i64 [[T0_NEG]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
call void @use64(i64 %t0)<br>
@@ -116,8 +116,8 @@ define i64 @n9(i64 %x) {<br>
<br>
define i64 @n10(i64 %x) {<br>
; CHECK-LABEL: @n10(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63<br>
-; CHECK-NEXT: [[R:%.*]] = xor i64 [[T0]], 1<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63<br>
+; CHECK-NEXT: [[R:%.*]] = add nsw i64 [[T0_NEG]], 1<br>
; CHECK-NEXT: ret i64 [[R]]<br>
;<br>
%t0 = lshr i64 %x, 63<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll<br>
index c256bd1ed4dc..40cb4aa29446 100644<br>
--- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll<br>
+++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll<br>
@@ -31,8 +31,8 @@ define i8 @t1(i8 %x, i8 %y) {<br>
; Shift-left can be negated if all uses can be updated<br>
define i8 @t2(i8 %x, i8 %y) {<br>
; CHECK-LABEL: @t2(<br>
-; CHECK-NEXT: [[T0:%.*]] = shl i8 -42, [[Y:%.*]]<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i8 [[X:%.*]], [[T0]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = shl i8 42, [[Y:%.*]]<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = shl i8 -42, %y<br>
@@ -55,8 +55,8 @@ define i8 @t3(i8 %x, i8 %y, i8 %z) {<br>
; CHECK-LABEL: @t3(<br>
; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[Z:%.*]]<br>
; CHECK-NEXT: call void @use8(i8 [[T0]])<br>
-; CHECK-NEXT: [[T1:%.*]] = shl i8 [[T0]], [[Y:%.*]]<br>
-; CHECK-NEXT: [[T2:%.*]] = sub i8 [[X:%.*]], [[T1]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = shl i8 [[Z]], [[Y:%.*]]<br>
+; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T2]]<br>
;<br>
%t0 = sub i8 0, %z<br>
@@ -85,8 +85,8 @@ define i8 @n3(i8 %x, i8 %y, i8 %z) {<br>
; Select can be negated if all it's operands can be negated and all the users of select can be updated<br>
define i8 @t4(i8 %x, i1 %y) {<br>
; CHECK-LABEL: @t4(<br>
-; CHECK-NEXT: [[T0:%.*]] = select i1 [[Y:%.*]], i8 -42, i8 44<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i8 [[X:%.*]], [[T0]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = select i1 [[Y:%.*]], i8 42, i8 -44<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = select i1 %y, i8 -42, i8 44<br>
@@ -119,8 +119,8 @@ define i8 @t6(i8 %x, i1 %y, i8 %z) {<br>
; CHECK-LABEL: @t6(<br>
; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[Z:%.*]]<br>
; CHECK-NEXT: call void @use8(i8 [[T0]])<br>
-; CHECK-NEXT: [[T1:%.*]] = select i1 [[Y:%.*]], i8 -42, i8 [[T0]]<br>
-; CHECK-NEXT: [[T2:%.*]] = sub i8 [[X:%.*]], [[T1]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = select i1 [[Y:%.*]], i8 42, i8 [[Z]]<br>
+; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T2]]<br>
;<br>
%t0 = sub i8 0, %z<br>
@@ -131,9 +131,9 @@ define i8 @t6(i8 %x, i1 %y, i8 %z) {<br>
}<br>
define i8 @t7(i8 %x, i1 %y, i8 %z) {<br>
; CHECK-LABEL: @t7(<br>
-; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Z:%.*]]<br>
-; CHECK-NEXT: [[T1:%.*]] = select i1 [[Y:%.*]], i8 0, i8 [[T0]]<br>
-; CHECK-NEXT: [[T2:%.*]] = sub i8 [[X:%.*]], [[T1]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = shl i8 -1, [[Z:%.*]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = select i1 [[Y:%.*]], i8 0, i8 [[T0_NEG]]<br>
+; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T2]]<br>
;<br>
%t0 = shl i8 1, %z<br>
@@ -169,10 +169,10 @@ define i8 @t9(i8 %x, i8 %y) {<br>
}<br>
define i8 @n10(i8 %x, i8 %y, i8 %z) {<br>
; CHECK-LABEL: @n10(<br>
-; CHECK-NEXT: [[T0:%.*]] = sub i8 [[Y:%.*]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]<br>
+; CHECK-NEXT: [[T0:%.*]] = sub i8 [[Y]], [[X]]<br>
; CHECK-NEXT: call void @use8(i8 [[T0]])<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i8 0, [[T0]]<br>
-; CHECK-NEXT: ret i8 [[T1]]<br>
+; CHECK-NEXT: ret i8 [[T0_NEG]]<br>
;<br>
%t0 = sub i8 %y, %x<br>
call void @use8(i8 %t0)<br>
@@ -204,8 +204,8 @@ define i8 @n13(i8 %x, i8 %y, i8 %z) {<br>
; CHECK-LABEL: @n13(<br>
; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[Y:%.*]]<br>
; CHECK-NEXT: call void @use8(i8 [[T0]])<br>
-; CHECK-NEXT: [[T11:%.*]] = sub i8 [[Y]], [[Z:%.*]]<br>
-; CHECK-NEXT: [[T2:%.*]] = add i8 [[T11]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = sub i8 [[Y]], [[Z:%.*]]<br>
+; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T2]]<br>
;<br>
%t0 = sub i8 0, %y<br>
@@ -242,8 +242,8 @@ define i8 @t15(i8 %x, i8 %y, i8 %z) {<br>
; CHECK-LABEL: @t15(<br>
; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[Y:%.*]]<br>
; CHECK-NEXT: call void @use8(i8 [[T0]])<br>
-; CHECK-NEXT: [[TMP1:%.*]] = mul i8 [[Z:%.*]], [[Y]]<br>
-; CHECK-NEXT: [[T2:%.*]] = add i8 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = mul i8 [[Y]], [[Z:%.*]]<br>
+; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T2]]<br>
;<br>
%t0 = sub i8 0, %y<br>
@@ -279,8 +279,8 @@ define i8 @t16(i1 %c, i8 %x) {<br>
; CHECK: else:<br>
; CHECK-NEXT: br label [[END]]<br>
; CHECK: end:<br>
-; CHECK-NEXT: [[Z:%.*]] = phi i8 [ [[X:%.*]], [[THEN]] ], [ 42, [[ELSE]] ]<br>
-; CHECK-NEXT: ret i8 [[Z]]<br>
+; CHECK-NEXT: [[Z_NEG:%.*]] = phi i8 [ [[X:%.*]], [[THEN]] ], [ 42, [[ELSE]] ]<br>
+; CHECK-NEXT: ret i8 [[Z_NEG]]<br>
;<br>
begin:<br>
br i1 %c, label %then, label %else<br>
@@ -352,9 +352,9 @@ end:<br>
; truncation can be negated if it's operand can be negated<br>
define i8 @t20(i8 %x, i16 %y) {<br>
; CHECK-LABEL: @t20(<br>
-; CHECK-NEXT: [[T0:%.*]] = shl i16 -42, [[Y:%.*]]<br>
-; CHECK-NEXT: [[T1:%.*]] = trunc i16 [[T0]] to i8<br>
-; CHECK-NEXT: [[T2:%.*]] = sub i8 [[X:%.*]], [[T1]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = shl i16 42, [[Y:%.*]]<br>
+; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i16 [[T0_NEG]] to i8<br>
+; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T2]]<br>
;<br>
%t0 = shl i16 -42, %y<br>
@@ -427,9 +427,9 @@ define i4 @negate_shl_xor(i4 %x, i4 %y) {<br>
<br>
define i8 @negate_shl_not_uses(i8 %x, i8 %y) {<br>
; CHECK-LABEL: @negate_shl_not_uses(<br>
-; CHECK-NEXT: [[O:%.*]] = xor i8 [[X:%.*]], -1<br>
+; CHECK-NEXT: [[O_NEG:%.*]] = add i8 [[X:%.*]], 1<br>
+; CHECK-NEXT: [[O:%.*]] = xor i8 [[X]], -1<br>
; CHECK-NEXT: call void @use8(i8 [[O]])<br>
-; CHECK-NEXT: [[O_NEG:%.*]] = add i8 [[X]], 1<br>
; CHECK-NEXT: [[S_NEG:%.*]] = shl i8 [[O_NEG]], [[Y:%.*]]<br>
; CHECK-NEXT: ret i8 [[S_NEG]]<br>
;<br>
@@ -442,9 +442,9 @@ define i8 @negate_shl_not_uses(i8 %x, i8 %y) {<br>
<br>
define <2 x i4> @negate_mul_not_uses_vec(<2 x i4> %x, <2 x i4> %y) {<br>
; CHECK-LABEL: @negate_mul_not_uses_vec(<br>
-; CHECK-NEXT: [[O:%.*]] = xor <2 x i4> [[X:%.*]], <i4 -1, i4 -1><br>
+; CHECK-NEXT: [[O_NEG:%.*]] = add <2 x i4> [[X:%.*]], <i4 1, i4 1><br>
+; CHECK-NEXT: [[O:%.*]] = xor <2 x i4> [[X]], <i4 -1, i4 -1><br>
; CHECK-NEXT: call void @use_v2i4(<2 x i4> [[O]])<br>
-; CHECK-NEXT: [[O_NEG:%.*]] = add <2 x i4> [[X]], <i4 1, i4 1><br>
; CHECK-NEXT: [[S_NEG:%.*]] = mul <2 x i4> [[O_NEG]], [[Y:%.*]]<br>
; CHECK-NEXT: ret <2 x i4> [[S_NEG]]<br>
;<br>
@@ -458,8 +458,8 @@ define <2 x i4> @negate_mul_not_uses_vec(<2 x i4> %x, <2 x i4> %y) {<br>
; signed division can be negated if divisor can be negated and is not 1/-1<br>
define i8 @negate_sdiv(i8 %x, i8 %y) {<br>
; CHECK-LABEL: @negate_sdiv(<br>
-; CHECK-NEXT: [[T0:%.*]] = sdiv i8 [[Y:%.*]], 42<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i8 [[X:%.*]], [[T0]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = sdiv i8 [[Y:%.*]], -42<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = sdiv i8 %y, 42<br>
@@ -478,12 +478,24 @@ define i8 @negate_sdiv_extrause(i8 %x, i8 %y) {<br>
%t1 = sub i8 %x, %t0<br>
ret i8 %t1<br>
}<br>
+define i8 @negate_sdiv_extrause2(i8 %x, i8 %y) {<br>
+; CHECK-LABEL: @negate_sdiv_extrause2(<br>
+; CHECK-NEXT: [[T0:%.*]] = sdiv i8 [[Y:%.*]], 42<br>
+; CHECK-NEXT: call void @use8(i8 [[T0]])<br>
+; CHECK-NEXT: [[T1:%.*]] = sub nsw i8 0, [[T0]]<br>
+; CHECK-NEXT: ret i8 [[T1]]<br>
+;<br>
+ %t0 = sdiv i8 %y, 42<br>
+ call void @use8(i8 %t0)<br>
+ %t1 = sub i8 0, %t0<br>
+ ret i8 %t1<br>
+}<br>
<br>
; Right-shift sign bit smear is negatible.<br>
define i8 @negate_ashr(i8 %x, i8 %y) {<br>
; CHECK-LABEL: @negate_ashr(<br>
-; CHECK-NEXT: [[T0:%.*]] = ashr i8 [[Y:%.*]], 7<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i8 [[X:%.*]], [[T0]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = lshr i8 [[Y:%.*]], 7<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = ashr i8 %y, 7<br>
@@ -492,8 +504,8 @@ define i8 @negate_ashr(i8 %x, i8 %y) {<br>
}<br>
define i8 @negate_lshr(i8 %x, i8 %y) {<br>
; CHECK-LABEL: @negate_lshr(<br>
-; CHECK-NEXT: [[T0:%.*]] = lshr i8 [[Y:%.*]], 7<br>
-; CHECK-NEXT: [[T1:%.*]] = sub i8 [[X:%.*]], [[T0]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i8 [[Y:%.*]], 7<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = lshr i8 %y, 7<br>
@@ -548,8 +560,8 @@ define i8 @negate_lshr_wrongshift(i8 %x, i8 %y) {<br>
; *ext of i1 is always negatible<br>
define i8 @negate_sext(i8 %x, i1 %y) {<br>
; CHECK-LABEL: @negate_sext(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[Y:%.*]] to i8<br>
-; CHECK-NEXT: [[T1:%.*]] = add i8 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = zext i1 [[Y:%.*]] to i8<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = sext i1 %y to i8<br>
@@ -558,8 +570,8 @@ define i8 @negate_sext(i8 %x, i1 %y) {<br>
}<br>
define i8 @negate_zext(i8 %x, i1 %y) {<br>
; CHECK-LABEL: @negate_zext(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = sext i1 [[Y:%.*]] to i8<br>
-; CHECK-NEXT: [[T1:%.*]] = add i8 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[T0_NEG:%.*]] = sext i1 [[Y:%.*]] to i8<br>
+; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[T1]]<br>
;<br>
%t0 = zext i1 %y to i8<br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/sub.ll b/llvm/test/Transforms/InstCombine/sub.ll<br>
index 6bda5b0a3019..1b4149291951 100644<br>
--- a/llvm/test/Transforms/InstCombine/sub.ll<br>
+++ b/llvm/test/Transforms/InstCombine/sub.ll<br>
@@ -218,8 +218,8 @@ define <2 x i8> @notnotsub_vec_undef_elts(<2 x i8> %x, <2 x i8> %y) {<br>
<br>
define i32 @test5(i32 %A, i32 %B, i32 %C) {<br>
; CHECK-LABEL: @test5(<br>
-; CHECK-NEXT: [[D1:%.*]] = sub i32 [[C:%.*]], [[B:%.*]]<br>
-; CHECK-NEXT: [[E:%.*]] = add i32 [[D1]], [[A:%.*]]<br>
+; CHECK-NEXT: [[D_NEG:%.*]] = sub i32 [[C:%.*]], [[B:%.*]]<br>
+; CHECK-NEXT: [[E:%.*]] = add i32 [[D_NEG]], [[A:%.*]]<br>
; CHECK-NEXT: ret i32 [[E]]<br>
;<br>
%D = sub i32 %B, %C<br>
@@ -555,11 +555,11 @@ define i64 @test_neg_shl_sub(i64 %a, i64 %b) {<br>
<br>
define i64 @test_neg_shl_sub_extra_use1(i64 %a, i64 %b, i64* %p) {<br>
; CHECK-LABEL: @test_neg_shl_sub_extra_use1(<br>
-; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A:%.*]], [[B:%.*]]<br>
+; CHECK-NEXT: [[SUB_NEG:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]<br>
+; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A]], [[B]]<br>
; CHECK-NEXT: store i64 [[SUB]], i64* [[P:%.*]], align 8<br>
-; CHECK-NEXT: [[MUL:%.*]] = shl i64 [[SUB]], 2<br>
-; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]<br>
-; CHECK-NEXT: ret i64 [[NEG]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = shl i64 [[SUB_NEG]], 2<br>
+; CHECK-NEXT: ret i64 [[MUL_NEG]]<br>
;<br>
%sub = sub i64 %a, %b<br>
store i64 %sub, i64* %p<br>
@@ -621,8 +621,8 @@ define i64 @test_neg_shl_sext_i1(i1 %a, i64 %b) {<br>
<br>
define i64 @test_neg_zext_i1_extra_use(i1 %a, i64 %b, i64* %p) {<br>
; CHECK-LABEL: @test_neg_zext_i1_extra_use(<br>
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[A:%.*]] to i64<br>
-; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[A]] to i64<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[A:%.*]] to i64<br>
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[A]] to i64<br>
; CHECK-NEXT: store i64 [[EXT]], i64* [[P:%.*]], align 8<br>
; CHECK-NEXT: ret i64 [[EXT_NEG]]<br>
;<br>
@@ -634,8 +634,8 @@ define i64 @test_neg_zext_i1_extra_use(i1 %a, i64 %b, i64* %p) {<br>
<br>
define i64 @test_neg_sext_i1_extra_use(i1 %a, i64 %b, i64* %p) {<br>
; CHECK-LABEL: @test_neg_sext_i1_extra_use(<br>
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[A:%.*]] to i64<br>
-; CHECK-NEXT: [[EXT_NEG:%.*]] = zext i1 [[A]] to i64<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = zext i1 [[A:%.*]] to i64<br>
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[A]] to i64<br>
; CHECK-NEXT: store i64 [[EXT]], i64* [[P:%.*]], align 8<br>
; CHECK-NEXT: ret i64 [[EXT_NEG]]<br>
;<br>
@@ -703,7 +703,7 @@ define i64 @test_neg_mul_sub_commuted(i64 %a, i64 %b, i64 %c) {<br>
; CHECK-LABEL: @test_neg_mul_sub_commuted(<br>
; CHECK-NEXT: [[COMPLEX:%.*]] = mul i64 [[C:%.*]], [[C]]<br>
; CHECK-NEXT: [[SUB_NEG:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]<br>
-; CHECK-NEXT: [[MUL_NEG:%.*]] = mul i64 [[COMPLEX]], [[SUB_NEG]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = mul i64 [[SUB_NEG]], [[COMPLEX]]<br>
; CHECK-NEXT: ret i64 [[MUL_NEG]]<br>
;<br>
%complex = mul i64 %c, %c<br>
@@ -715,8 +715,8 @@ define i64 @test_neg_mul_sub_commuted(i64 %a, i64 %b, i64 %c) {<br>
<br>
define i32 @test27(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @test27(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[Y:%.*]], 3<br>
-; CHECK-NEXT: [[SUB:%.*]] = add i32 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = shl i32 [[Y:%.*]], 3<br>
+; CHECK-NEXT: [[SUB:%.*]] = add i32 [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i32 [[SUB]]<br>
;<br>
%mul = mul i32 %y, -8<br>
@@ -726,8 +726,8 @@ define i32 @test27(i32 %x, i32 %y) {<br>
<br>
define <2 x i32> @test27vec(<2 x i32> %x, <2 x i32> %y) {<br>
; CHECK-LABEL: @test27vec(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 6><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 6><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i32> [[SUB]]<br>
;<br>
%mul = mul <2 x i32> %y, <i32 -8, i32 -6><br>
@@ -737,8 +737,8 @@ define <2 x i32> @test27vec(<2 x i32> %x, <2 x i32> %y) {<br>
<br>
define <2 x i32> @test27vecsplat(<2 x i32> %x, <2 x i32> %y) {<br>
; CHECK-LABEL: @test27vecsplat(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 3, i32 3><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 3, i32 3><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i32> [[SUB]]<br>
;<br>
%mul = mul <2 x i32> %y, <i32 -8, i32 -8><br>
@@ -748,8 +748,8 @@ define <2 x i32> @test27vecsplat(<2 x i32> %x, <2 x i32> %y) {<br>
<br>
define <2 x i32> @test27vecmixed(<2 x i32> %x, <2 x i32> %y) {<br>
; CHECK-LABEL: @test27vecmixed(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 -8><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 -8><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i32> [[SUB]]<br>
;<br>
%mul = mul <2 x i32> %y, <i32 -8, i32 8><br>
@@ -759,8 +759,8 @@ define <2 x i32> @test27vecmixed(<2 x i32> %x, <2 x i32> %y) {<br>
<br>
define i32 @test27commuted(i32 %x, i32 %y) {<br>
; CHECK-LABEL: @test27commuted(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[Y:%.*]], 3<br>
-; CHECK-NEXT: [[SUB:%.*]] = add i32 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = shl i32 [[Y:%.*]], 3<br>
+; CHECK-NEXT: [[SUB:%.*]] = add i32 [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i32 [[SUB]]<br>
;<br>
%mul = mul i32 -8, %y<br>
@@ -770,8 +770,8 @@ define i32 @test27commuted(i32 %x, i32 %y) {<br>
<br>
define <2 x i32> @test27commutedvec(<2 x i32> %x, <2 x i32> %y) {<br>
; CHECK-LABEL: @test27commutedvec(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 6><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 6><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i32> [[SUB]]<br>
;<br>
%mul = mul <2 x i32> <i32 -8, i32 -6>, %y<br>
@@ -781,8 +781,8 @@ define <2 x i32> @test27commutedvec(<2 x i32> %x, <2 x i32> %y) {<br>
<br>
define <2 x i32> @test27commutedvecsplat(<2 x i32> %x, <2 x i32> %y) {<br>
; CHECK-LABEL: @test27commutedvecsplat(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 3, i32 3><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 3, i32 3><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i32> [[SUB]]<br>
;<br>
%mul = mul <2 x i32> <i32 -8, i32 -8>, %y<br>
@@ -792,8 +792,8 @@ define <2 x i32> @test27commutedvecsplat(<2 x i32> %x, <2 x i32> %y) {<br>
<br>
define <2 x i32> @test27commutedvecmixed(<2 x i32> %x, <2 x i32> %y) {<br>
; CHECK-LABEL: @test27commutedvecmixed(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 -8><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[MUL_NEG:%.*]] = mul <2 x i32> [[Y:%.*]], <i32 8, i32 -8><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i32> [[SUB]]<br>
;<br>
%mul = mul <2 x i32> <i32 -8, i32 8>, %y<br>
@@ -1105,7 +1105,7 @@ define i32 @test52(i32 %X) {<br>
<br>
define <2 x i1> @test53(<2 x i1> %A, <2 x i1> %B) {<br>
; CHECK-LABEL: @test53(<br>
-; CHECK-NEXT: [[SUB:%.*]] = xor <2 x i1> [[A:%.*]], [[B:%.*]]<br>
+; CHECK-NEXT: [[SUB:%.*]] = xor <2 x i1> [[B:%.*]], [[A:%.*]]<br>
; CHECK-NEXT: ret <2 x i1> [[SUB]]<br>
;<br>
%sub = sub <2 x i1> %A, %B<br>
@@ -1149,8 +1149,8 @@ define i32 @test55(i1 %which) {<br>
; CHECK: delay:<br>
; CHECK-NEXT: br label [[FINAL]]<br>
; CHECK: final:<br>
-; CHECK-NEXT: [[A:%.*]] = phi i32 [ -877, [[ENTRY:%.*]] ], [ 113, [[DELAY]] ]<br>
-; CHECK-NEXT: ret i32 [[A]]<br>
+; CHECK-NEXT: [[A_NEG:%.*]] = phi i32 [ -877, [[ENTRY:%.*]] ], [ 113, [[DELAY]] ]<br>
+; CHECK-NEXT: ret i32 [[A_NEG]]<br>
;<br>
entry:<br>
br i1 %which, label %final, label %delay<br>
@@ -1171,8 +1171,8 @@ define <2 x i32> @test55vec(i1 %which) {<br>
; CHECK: delay:<br>
; CHECK-NEXT: br label [[FINAL]]<br>
; CHECK: final:<br>
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 -877, i32 -877>, [[ENTRY:%.*]] ], [ <i32 113, i32 113>, [[DELAY]] ]<br>
-; CHECK-NEXT: ret <2 x i32> [[A]]<br>
+; CHECK-NEXT: [[A_NEG:%.*]] = phi <2 x i32> [ <i32 -877, i32 -877>, [[ENTRY:%.*]] ], [ <i32 113, i32 113>, [[DELAY]] ]<br>
+; CHECK-NEXT: ret <2 x i32> [[A_NEG]]<br>
;<br>
entry:<br>
br i1 %which, label %final, label %delay<br>
@@ -1193,8 +1193,8 @@ define <2 x i32> @test55vec2(i1 %which) {<br>
; CHECK: delay:<br>
; CHECK-NEXT: br label [[FINAL]]<br>
; CHECK: final:<br>
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 -877, i32 -2167>, [[ENTRY:%.*]] ], [ <i32 113, i32 303>, [[DELAY]] ]<br>
-; CHECK-NEXT: ret <2 x i32> [[A]]<br>
+; CHECK-NEXT: [[A_NEG:%.*]] = phi <2 x i32> [ <i32 -877, i32 -2167>, [[ENTRY:%.*]] ], [ <i32 113, i32 303>, [[DELAY]] ]<br>
+; CHECK-NEXT: ret <2 x i32> [[A_NEG]]<br>
;<br>
entry:<br>
br i1 %which, label %final, label %delay<br>
@@ -1356,8 +1356,8 @@ define i32 @test64(i32 %x) {<br>
; CHECK-LABEL: @test64(<br>
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 255<br>
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 255<br>
-; CHECK-NEXT: [[RES:%.*]] = add nsw i32 [[TMP2]], 1<br>
-; CHECK-NEXT: ret i32 [[RES]]<br>
+; CHECK-NEXT: [[DOTNEG:%.*]] = add nsw i32 [[TMP2]], 1<br>
+; CHECK-NEXT: ret i32 [[DOTNEG]]<br>
;<br>
%1 = xor i32 %x, -1<br>
%2 = icmp sgt i32 %1, -256<br>
@@ -1370,8 +1370,8 @@ define i32 @test65(i32 %x) {<br>
; CHECK-LABEL: @test65(<br>
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -256<br>
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -256<br>
-; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP2]], 1<br>
-; CHECK-NEXT: ret i32 [[RES]]<br>
+; CHECK-NEXT: [[DOTNEG:%.*]] = add i32 [[TMP2]], 1<br>
+; CHECK-NEXT: ret i32 [[DOTNEG]]<br>
;<br>
%1 = xor i32 %x, -1<br>
%2 = icmp slt i32 %1, 255<br>
@@ -1384,8 +1384,8 @@ define i32 @test66(i32 %x) {<br>
; CHECK-LABEL: @test66(<br>
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -101<br>
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -101<br>
-; CHECK-NEXT: [[RES:%.*]] = add nuw i32 [[TMP2]], 1<br>
-; CHECK-NEXT: ret i32 [[RES]]<br>
+; CHECK-NEXT: [[DOTNEG:%.*]] = add nuw i32 [[TMP2]], 1<br>
+; CHECK-NEXT: ret i32 [[DOTNEG]]<br>
;<br>
%1 = xor i32 %x, -1<br>
%2 = icmp ugt i32 %1, 100<br>
@@ -1398,8 +1398,8 @@ define i32 @test67(i32 %x) {<br>
; CHECK-LABEL: @test67(<br>
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], 100<br>
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 100<br>
-; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP2]], 1<br>
-; CHECK-NEXT: ret i32 [[RES]]<br>
+; CHECK-NEXT: [[DOTNEG:%.*]] = add i32 [[TMP2]], 1<br>
+; CHECK-NEXT: ret i32 [[DOTNEG]]<br>
;<br>
%1 = xor i32 %x, -1<br>
%2 = icmp ult i32 %1, -101<br>
@@ -1413,8 +1413,8 @@ define <2 x i32> @test68(<2 x i32> %x) {<br>
; CHECK-LABEL: @test68(<br>
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 255, i32 255><br>
; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[X]], <2 x i32> <i32 255, i32 255><br>
-; CHECK-NEXT: [[RES:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 1, i32 1><br>
-; CHECK-NEXT: ret <2 x i32> [[RES]]<br>
+; CHECK-NEXT: [[DOTNEG:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 1, i32 1><br>
+; CHECK-NEXT: ret <2 x i32> [[DOTNEG]]<br>
;<br>
%1 = xor <2 x i32> %x, <i32 -1, i32 -1><br>
%2 = icmp sgt <2 x i32> %1, <i32 -256, i32 -256><br>
@@ -1428,8 +1428,8 @@ define <2 x i32> @test69(<2 x i32> %x) {<br>
; CHECK-LABEL: @test69(<br>
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 255, i32 127><br>
; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[X]], <2 x i32> <i32 255, i32 127><br>
-; CHECK-NEXT: [[RES:%.*]] = add <2 x i32> [[TMP2]], <i32 1, i32 1><br>
-; CHECK-NEXT: ret <2 x i32> [[RES]]<br>
+; CHECK-NEXT: [[DOTNEG:%.*]] = add <2 x i32> [[TMP2]], <i32 1, i32 1><br>
+; CHECK-NEXT: ret <2 x i32> [[DOTNEG]]<br>
;<br>
%1 = xor <2 x i32> %x, <i32 -1, i32 -1><br>
%2 = icmp sgt <2 x i32> %1, <i32 -256, i32 -128><br>
<br>
diff --git a/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll b/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll<br>
index 71fa9a795735..7ad0655dcbe8 100644<br>
--- a/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll<br>
+++ b/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll<br>
@@ -5,9 +5,9 @@<br>
<br>
define i32 @a(i1 zeroext %x, i1 zeroext %y) {<br>
; CHECK-LABEL: @a(<br>
-; CHECK-NEXT: [[CONV3_NEG:%.*]] = sext i1 [[Y:%.*]] to i32<br>
+; CHECK-NEXT: [[CONV3_NEG1:%.*]] = sext i1 [[Y:%.*]] to i32<br>
; CHECK-NEXT: [[SUB:%.*]] = select i1 [[X:%.*]], i32 2, i32 1<br>
-; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG]]<br>
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG1]]<br>
; CHECK-NEXT: ret i32 [[ADD]]<br>
;<br>
%conv = zext i1 %x to i32<br>
@@ -95,8 +95,8 @@ declare void @use(i64)<br>
<br>
define i64 @zext_negate(i1 %A) {<br>
; CHECK-LABEL: @zext_negate(<br>
-; CHECK-NEXT: [[SUB:%.*]] = sext i1 [[A:%.*]] to i64<br>
-; CHECK-NEXT: ret i64 [[SUB]]<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[A:%.*]] to i64<br>
+; CHECK-NEXT: ret i64 [[EXT_NEG]]<br>
;<br>
%ext = zext i1 %A to i64<br>
%sub = sub i64 0, %ext<br>
@@ -105,10 +105,10 @@ define i64 @zext_negate(i1 %A) {<br>
<br>
define i64 @zext_negate_extra_use(i1 %A) {<br>
; CHECK-LABEL: @zext_negate_extra_use(<br>
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[A:%.*]] to i64<br>
-; CHECK-NEXT: [[SUB:%.*]] = sext i1 [[A]] to i64<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[A:%.*]] to i64<br>
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[A]] to i64<br>
; CHECK-NEXT: call void @use(i64 [[EXT]])<br>
-; CHECK-NEXT: ret i64 [[SUB]]<br>
+; CHECK-NEXT: ret i64 [[EXT_NEG]]<br>
;<br>
%ext = zext i1 %A to i64<br>
%sub = sub i64 0, %ext<br>
@@ -118,8 +118,8 @@ define i64 @zext_negate_extra_use(i1 %A) {<br>
<br>
define <2 x i64> @zext_negate_vec(<2 x i1> %A) {<br>
; CHECK-LABEL: @zext_negate_vec(<br>
-; CHECK-NEXT: [[SUB:%.*]] = sext <2 x i1> [[A:%.*]] to <2 x i64><br>
-; CHECK-NEXT: ret <2 x i64> [[SUB]]<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = sext <2 x i1> [[A:%.*]] to <2 x i64><br>
+; CHECK-NEXT: ret <2 x i64> [[EXT_NEG]]<br>
;<br>
%ext = zext <2 x i1> %A to <2 x i64><br>
%sub = sub <2 x i64> zeroinitializer, %ext<br>
@@ -128,8 +128,8 @@ define <2 x i64> @zext_negate_vec(<2 x i1> %A) {<br>
<br>
define <2 x i64> @zext_negate_vec_undef_elt(<2 x i1> %A) {<br>
; CHECK-LABEL: @zext_negate_vec_undef_elt(<br>
-; CHECK-NEXT: [[SUB:%.*]] = sext <2 x i1> [[A:%.*]] to <2 x i64><br>
-; CHECK-NEXT: ret <2 x i64> [[SUB]]<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = sext <2 x i1> [[A:%.*]] to <2 x i64><br>
+; CHECK-NEXT: ret <2 x i64> [[EXT_NEG]]<br>
;<br>
%ext = zext <2 x i1> %A to <2 x i64><br>
%sub = sub <2 x i64> <i64 0, i64 undef>, %ext<br>
@@ -181,8 +181,8 @@ define <2 x i64> @zext_sub_const_vec_undef_elt(<2 x i1> %A) {<br>
<br>
define i64 @sext_negate(i1 %A) {<br>
; CHECK-LABEL: @sext_negate(<br>
-; CHECK-NEXT: [[SUB:%.*]] = zext i1 [[A:%.*]] to i64<br>
-; CHECK-NEXT: ret i64 [[SUB]]<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = zext i1 [[A:%.*]] to i64<br>
+; CHECK-NEXT: ret i64 [[EXT_NEG]]<br>
;<br>
%ext = sext i1 %A to i64<br>
%sub = sub i64 0, %ext<br>
@@ -191,10 +191,10 @@ define i64 @sext_negate(i1 %A) {<br>
<br>
define i64 @sext_negate_extra_use(i1 %A) {<br>
; CHECK-LABEL: @sext_negate_extra_use(<br>
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[A:%.*]] to i64<br>
-; CHECK-NEXT: [[SUB:%.*]] = zext i1 [[A]] to i64<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = zext i1 [[A:%.*]] to i64<br>
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[A]] to i64<br>
; CHECK-NEXT: call void @use(i64 [[EXT]])<br>
-; CHECK-NEXT: ret i64 [[SUB]]<br>
+; CHECK-NEXT: ret i64 [[EXT_NEG]]<br>
;<br>
%ext = sext i1 %A to i64<br>
%sub = sub i64 0, %ext<br>
@@ -204,8 +204,8 @@ define i64 @sext_negate_extra_use(i1 %A) {<br>
<br>
define <2 x i64> @sext_negate_vec(<2 x i1> %A) {<br>
; CHECK-LABEL: @sext_negate_vec(<br>
-; CHECK-NEXT: [[SUB:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i64><br>
-; CHECK-NEXT: ret <2 x i64> [[SUB]]<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i64><br>
+; CHECK-NEXT: ret <2 x i64> [[EXT_NEG]]<br>
;<br>
%ext = sext <2 x i1> %A to <2 x i64><br>
%sub = sub <2 x i64> zeroinitializer, %ext<br>
@@ -214,8 +214,8 @@ define <2 x i64> @sext_negate_vec(<2 x i1> %A) {<br>
<br>
define <2 x i64> @sext_negate_vec_undef_elt(<2 x i1> %A) {<br>
; CHECK-LABEL: @sext_negate_vec_undef_elt(<br>
-; CHECK-NEXT: [[SUB:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i64><br>
-; CHECK-NEXT: ret <2 x i64> [[SUB]]<br>
+; CHECK-NEXT: [[EXT_NEG:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i64><br>
+; CHECK-NEXT: ret <2 x i64> [[EXT_NEG]]<br>
;<br>
%ext = sext <2 x i1> %A to <2 x i64><br>
%sub = sub <2 x i64> <i64 0, i64 undef>, %ext<br>
@@ -267,8 +267,8 @@ define <2 x i64> @sext_sub_const_vec_undef_elt(<2 x i1> %A) {<br>
<br>
define i8 @sext_sub(i8 %x, i1 %y) {<br>
; CHECK-LABEL: @sext_sub(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[Y:%.*]] to i8<br>
-; CHECK-NEXT: [[SUB:%.*]] = add i8 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[SEXT_NEG:%.*]] = zext i1 [[Y:%.*]] to i8<br>
+; CHECK-NEXT: [[SUB:%.*]] = add i8 [[SEXT_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[SUB]]<br>
;<br>
%sext = sext i1 %y to i8<br>
@@ -280,8 +280,8 @@ define i8 @sext_sub(i8 %x, i1 %y) {<br>
<br>
define <2 x i8> @sext_sub_vec(<2 x i8> %x, <2 x i1> %y) {<br>
; CHECK-LABEL: @sext_sub_vec(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[Y:%.*]] to <2 x i8><br>
-; CHECK-NEXT: [[SUB:%.*]] = add <2 x i8> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[SEXT_NEG:%.*]] = zext <2 x i1> [[Y:%.*]] to <2 x i8><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i8> [[SEXT_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i8> [[SUB]]<br>
;<br>
%sext = sext <2 x i1> %y to <2 x i8><br>
@@ -293,8 +293,8 @@ define <2 x i8> @sext_sub_vec(<2 x i8> %x, <2 x i1> %y) {<br>
<br>
define <2 x i8> @sext_sub_vec_nsw(<2 x i8> %x, <2 x i1> %y) {<br>
; CHECK-LABEL: @sext_sub_vec_nsw(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[Y:%.*]] to <2 x i8><br>
-; CHECK-NEXT: [[SUB:%.*]] = add nsw <2 x i8> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[SEXT_NEG:%.*]] = zext <2 x i1> [[Y:%.*]] to <2 x i8><br>
+; CHECK-NEXT: [[SUB:%.*]] = add <2 x i8> [[SEXT_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <2 x i8> [[SUB]]<br>
;<br>
%sext = sext <2 x i1> %y to <2 x i8><br>
@@ -306,8 +306,8 @@ define <2 x i8> @sext_sub_vec_nsw(<2 x i8> %x, <2 x i1> %y) {<br>
<br>
define i8 @sext_sub_nuw(i8 %x, i1 %y) {<br>
; CHECK-LABEL: @sext_sub_nuw(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[Y:%.*]] to i8<br>
-; CHECK-NEXT: [[SUB:%.*]] = add i8 [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[SEXT_NEG:%.*]] = zext i1 [[Y:%.*]] to i8<br>
+; CHECK-NEXT: [[SUB:%.*]] = add i8 [[SEXT_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret i8 [[SUB]]<br>
;<br>
%sext = sext i1 %y to i8<br>
@@ -393,8 +393,8 @@ define i32 @zextbool_sub_uses(i1 %c, i32 %x) {<br>
<br>
define <4 x i32> @zextbool_sub_vector(<4 x i1> %c, <4 x i32> %x) {<br>
; CHECK-LABEL: @zextbool_sub_vector(<br>
-; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i1> [[C:%.*]] to <4 x i32><br>
-; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[TMP1]], [[X:%.*]]<br>
+; CHECK-NEXT: [[B_NEG:%.*]] = sext <4 x i1> [[C:%.*]] to <4 x i32><br>
+; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[B_NEG]], [[X:%.*]]<br>
; CHECK-NEXT: ret <4 x i32> [[S]]<br>
;<br>
%b = zext <4 x i1> %c to <4 x i32><br>
<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>
</blockquote></div>