<div dir="ltr">I'm compiling all targets (even experimental ones) and most projects from llvm-project.<div>When I'm adding the LLVM_ATTRIBUTE_DEPRECATED I make sure llvm-project does not have any remaining calls to the deprecated method, only to the new one.</div><div><br></div><div>The attribute helps for out of tree users though.</div><div><br></div><div>Did I break you? Or build bots?</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Mar 18, 2020 at 2:54 PM Roman Lebedev <<a href="mailto:lebedev.ri@gmail.com">lebedev.ri@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Just wondering, how does deprecation help?<br>
Since bots use -Werror, if there's uses of the deprecated methods within LLVM,<br>
this will break the build, and if there aren't any uses, then it's dead code<br>
that can be freely dropped under guarantee of the lack of C++<br>
interface stability..<br>
<br>
Roman<br>
<br>
On Wed, Mar 18, 2020 at 4:49 PM Guillaume Chatelet via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
><br>
><br>
> Author: Guillaume Chatelet<br>
> Date: 2020-03-18T14:48:45+01:00<br>
> New Revision: d000655a8cd58c8449a86a1761038c8c1dd78d87<br>
><br>
> URL: <a href="https://github.com/llvm/llvm-project/commit/d000655a8cd58c8449a86a1761038c8c1dd78d87" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/d000655a8cd58c8449a86a1761038c8c1dd78d87</a><br>
> DIFF: <a href="https://github.com/llvm/llvm-project/commit/d000655a8cd58c8449a86a1761038c8c1dd78d87.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/d000655a8cd58c8449a86a1761038c8c1dd78d87.diff</a><br>
><br>
> LOG: [Alignment][NFC] Deprecate getMaxAlignment<br>
><br>
> Summary:<br>
> This is patch is part of a series to introduce an Alignment type.<br>
> See this thread for context: <a href="http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html" rel="noreferrer" target="_blank">http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html</a><br>
> See this patch for the introduction of the type: <a href="https://reviews.llvm.org/D64790" rel="noreferrer" target="_blank">https://reviews.llvm.org/D64790</a><br>
><br>
> Reviewers: courbet<br>
><br>
> Subscribers: jholewinski, arsenm, dschuff, jyknight, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits<br>
><br>
> Tags: #llvm<br>
><br>
> Differential Revision: <a href="https://reviews.llvm.org/D76348" rel="noreferrer" target="_blank">https://reviews.llvm.org/D76348</a><br>
><br>
> Added:<br>
><br>
><br>
> Modified:<br>
> llvm/include/llvm/CodeGen/MachineFrameInfo.h<br>
> llvm/lib/CodeGen/MIRPrinter.cpp<br>
> llvm/lib/CodeGen/TargetRegisterInfo.cpp<br>
> llvm/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
> llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp<br>
> llvm/lib/Target/AMDGPU/SIFrameLowering.cpp<br>
> llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp<br>
> llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
> llvm/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
> llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
> llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
> llvm/lib/Target/Lanai/LanaiFrameLowering.cpp<br>
> llvm/lib/Target/Mips/MipsSEFrameLowering.cpp<br>
> llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
> llvm/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
> llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp<br>
> llvm/lib/Target/RISCV/RISCVFrameLowering.cpp<br>
> llvm/lib/Target/Sparc/SparcFrameLowering.cpp<br>
> llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp<br>
> llvm/lib/Target/X86/X86FrameLowering.cpp<br>
><br>
> Removed:<br>
><br>
><br>
><br>
> ################################################################################<br>
> diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h<br>
> index 681a27b0ad29..384b206fc220 100644<br>
> --- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h<br>
> +++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h<br>
> @@ -583,7 +583,10 @@ class MachineFrameInfo {<br>
><br>
> /// Return the alignment in bytes that this function must be aligned to,<br>
> /// which is greater than the default stack alignment provided by the target.<br>
> - unsigned getMaxAlignment() const { return MaxAlignment.value(); }<br>
> + LLVM_ATTRIBUTE_DEPRECATED(unsigned getMaxAlignment() const,<br>
> + "Use getMaxAlign instead") {<br>
> + return MaxAlignment.value();<br>
> + }<br>
> /// Return the alignment in bytes that this function must be aligned to,<br>
> /// which is greater than the default stack alignment provided by the target.<br>
> Align getMaxAlign() const { return MaxAlignment; }<br>
><br>
> diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp<br>
> index 1fb557e4dfcd..2a150b1368df 100644<br>
> --- a/llvm/lib/CodeGen/MIRPrinter.cpp<br>
> +++ b/llvm/lib/CodeGen/MIRPrinter.cpp<br>
> @@ -334,7 +334,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,<br>
> YamlMFI.HasPatchPoint = MFI.hasPatchPoint();<br>
> YamlMFI.StackSize = MFI.getStackSize();<br>
> YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();<br>
> - YamlMFI.MaxAlignment = MFI.getMaxAlignment();<br>
> + YamlMFI.MaxAlignment = MFI.getMaxAlign().value();<br>
> YamlMFI.AdjustsStack = MFI.adjustsStack();<br>
> YamlMFI.HasCalls = MFI.hasCalls();<br>
> YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()<br>
><br>
> diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp<br>
> index 1c582ff06560..34d1f7e611ab 100644<br>
> --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp<br>
> +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp<br>
> @@ -468,8 +468,8 @@ bool TargetRegisterInfo::needsStackRealignment(<br>
> const MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();<br>
> const Function &F = MF.getFunction();<br>
> - unsigned StackAlign = TFI->getStackAlignment();<br>
> - bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||<br>
> + Align StackAlign = TFI->getStackAlign();<br>
> + bool requiresRealignment = ((MFI.getMaxAlign() > StackAlign) ||<br>
> F.hasFnAttribute(Attribute::StackAlignment));<br>
> if (F.hasFnAttribute("stackrealign") || requiresRealignment) {<br>
> if (canRealignStack(MF))<br>
><br>
> diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
> index 91a8bca99397..9f17d7d0762b 100644<br>
> --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
> +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
> @@ -1217,8 +1217,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,<br>
> false, NeedsWinCFI, &HasWinCFI);<br>
><br>
> if (NeedsRealignment) {<br>
> - const unsigned Alignment = MFI.getMaxAlignment();<br>
> - const unsigned NrBitsToZero = countTrailingZeros(Alignment);<br>
> + const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());<br>
> assert(NrBitsToZero > 1);<br>
> assert(scratchSPReg != AArch64::SP);<br>
><br>
><br>
> diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp<br>
> index 1a56f382ca80..733db1eae80d 100644<br>
> --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp<br>
> +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp<br>
> @@ -631,8 +631,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(<br>
> Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();<br>
> Info.PrivateSegmentSize = FrameInfo.getStackSize();<br>
> if (MFI->isStackRealigned())<br>
> - Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();<br>
> -<br>
> + Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();<br>
><br>
> Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||<br>
> MRI.isPhysRegUsed(AMDGPU::VCC_HI);<br>
><br>
> diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp<br>
> index d0c713d07d87..60b35981de9c 100644<br>
> --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp<br>
> @@ -768,7 +768,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,<br>
><br>
> if (TRI.needsStackRealignment(MF)) {<br>
> HasFP = true;<br>
> - const unsigned Alignment = MFI.getMaxAlignment();<br>
> + const unsigned Alignment = MFI.getMaxAlign().value();<br>
><br>
> RoundedSize += Alignment;<br>
> if (LiveRegs.empty()) {<br>
> @@ -834,8 +834,9 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,<br>
><br>
> const MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> uint32_t NumBytes = MFI.getStackSize();<br>
> - uint32_t RoundedSize = FuncInfo->isStackRealigned() ?<br>
> - NumBytes + MFI.getMaxAlignment() : NumBytes;<br>
> + uint32_t RoundedSize = FuncInfo->isStackRealigned()<br>
> + ? NumBytes + MFI.getMaxAlign().value()<br>
> + : NumBytes;<br>
><br>
> if (RoundedSize != 0 && hasFP(MF)) {<br>
> const unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();<br>
><br>
> diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp<br>
> index 4dcb1f62577a..9fc566761c5c 100644<br>
> --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp<br>
> +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp<br>
> @@ -1360,17 +1360,18 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,<br>
> // If there's dynamic realignment, adjust for it.<br>
> if (RI.needsStackRealignment(MF)) {<br>
> MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> - unsigned MaxAlign = MFI.getMaxAlignment();<br>
> + Align MaxAlign = MFI.getMaxAlign();<br>
> assert (!AFI->isThumb1OnlyFunction());<br>
> // Emit bic r6, r6, MaxAlign<br>
> - assert(MaxAlign <= 256 && "The BIC instruction cannot encode "<br>
> - "immediates larger than 256 with all lower "<br>
> - "bits set.");<br>
> + assert(MaxAlign <= Align(256) &&<br>
> + "The BIC instruction cannot encode "<br>
> + "immediates larger than 256 with all lower "<br>
> + "bits set.");<br>
> unsigned bicOpc = AFI->isThumbFunction() ?<br>
> ARM::t2BICri : ARM::BICri;<br>
> BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)<br>
> .addReg(ARM::R6, RegState::Kill)<br>
> - .addImm(MaxAlign - 1)<br>
> + .addImm(MaxAlign.value() - 1)<br>
> .add(predOps(ARMCC::AL))<br>
> .add(condCodeOp());<br>
> }<br>
><br>
> diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
> index 9807971b558b..8910b66c235e 100644<br>
> --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
> @@ -260,13 +260,13 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,<br>
> MachineBasicBlock &MBB,<br>
> MachineBasicBlock::iterator MBBI,<br>
> const DebugLoc &DL, const unsigned Reg,<br>
> - const unsigned Alignment,<br>
> + const Align Alignment,<br>
> const bool MustBeSingleInstruction) {<br>
> const ARMSubtarget &AST =<br>
> static_cast<const ARMSubtarget &>(MF.getSubtarget());<br>
> const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();<br>
> - const unsigned AlignMask = Alignment - 1;<br>
> - const unsigned NrBitsToZero = countTrailingZeros(Alignment);<br>
> + const unsigned AlignMask = Alignment.value() - 1U;<br>
> + const unsigned NrBitsToZero = Log2(Alignment);<br>
> assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");<br>
> if (!AFI->isThumbFunction()) {<br>
> // if the BFC instruction is available, use that to zero the lower<br>
> @@ -346,7 +346,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,<br>
> assert(!AFI->isThumb1OnlyFunction() &&<br>
> "This emitPrologue does not support Thumb1!");<br>
> bool isARM = !AFI->isThumbFunction();<br>
> - unsigned Align = STI.getFrameLowering()->getStackAlignment();<br>
> + Align Alignment = STI.getFrameLowering()->getStackAlign();<br>
> unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();<br>
> unsigned NumBytes = MFI.getStackSize();<br>
> const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();<br>
> @@ -437,8 +437,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,<br>
> // Determine starting offsets of spill areas.<br>
> unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;<br>
> unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;<br>
> - unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;<br>
> - unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;<br>
> + Align DPRAlign = DPRCSSize ? std::min(Align(8), Alignment) : Align(4);<br>
> + unsigned DPRGapSize =<br>
> + (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign.value();<br>
> unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;<br>
> int FramePtrOffsetInPush = 0;<br>
> if (HasFP) {<br>
> @@ -696,7 +697,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,<br>
> // If aligned NEON registers were spilled, the stack has already been<br>
> // realigned.<br>
> if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {<br>
> - unsigned MaxAlign = MFI.getMaxAlignment();<br>
> + Align MaxAlign = MFI.getMaxAlign();<br>
> assert(!AFI->isThumb1OnlyFunction());<br>
> if (!AFI->isThumbFunction()) {<br>
> emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,<br>
> @@ -1168,7 +1169,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,<br>
> int FI = CSI[i].getFrameIdx();<br>
> // The even-numbered registers will be 16-byte aligned, the odd-numbered<br>
> // registers will be 8-byte aligned.<br>
> - MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);<br>
> + MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16));<br>
><br>
> // The stack slot for D8 needs to be maximally aligned because this is<br>
> // actually the point where we align the stack pointer. MachineFrameInfo<br>
> @@ -1177,7 +1178,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,<br>
> // over-alignment is not realized because the code inserted below adjusts<br>
> // the stack pointer by numregs * 8 before aligning the stack pointer.<br>
> if (DNum == 0)<br>
> - MFI.setObjectAlignment(FI, MFI.getMaxAlignment());<br>
> + MFI.setObjectAlignment(FI, MFI.getMaxAlign());<br>
> }<br>
><br>
> // Move the stack pointer to the d8 spill slot, and align it at the same<br>
> @@ -1200,7 +1201,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,<br>
> .add(predOps(ARMCC::AL))<br>
> .add(condCodeOp());<br>
><br>
> - unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();<br>
> + Align MaxAlign = MF.getFrameInfo().getMaxAlign();<br>
> // We must set parameter MustBeSingleInstruction to true, since<br>
> // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform<br>
> // stack alignment. Luckily, this can always be done since all ARM<br>
><br>
> diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
> index c0632016ccf0..c017ebb885da 100644<br>
> --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
> +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
> @@ -402,7 +402,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,<br>
> AFI->setDPRCalleeSavedAreaSize(DPRCSSize);<br>
><br>
> if (RegInfo->needsStackRealignment(MF)) {<br>
> - const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());<br>
> + const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());<br>
> // Emit the following sequence, using R4 as a temporary, since we cannot use<br>
> // SP as a source or destination register for the shifts:<br>
> // mov r4, sp<br>
><br>
> diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
> index 1a2d92719c5e..1601d5600cc2 100644<br>
> --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp<br>
> @@ -591,7 +591,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,<br>
> auto &HII = *HST.getInstrInfo();<br>
> auto &HRI = *HST.getRegisterInfo();<br>
><br>
> - unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());<br>
> + Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());<br>
><br>
> // Calculate the total stack frame size.<br>
> // Get the number of bytes to allocate from the FrameInfo.<br>
> @@ -603,7 +603,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,<br>
> FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);<br>
> MFI.setStackSize(FrameSize);<br>
><br>
> - bool AlignStack = (MaxAlign > getStackAlignment());<br>
> + bool AlignStack = (MaxAlign > getStackAlign());<br>
><br>
> // Get the number of bytes to allocate from the FrameInfo.<br>
> unsigned NumBytes = MFI.getStackSize();<br>
> @@ -742,7 +742,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,<br>
> if (AlignStack) {<br>
> BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)<br>
> .addReg(SP)<br>
> - .addImm(-int64_t(MaxAlign));<br>
> + .addImm(-int64_t(MaxAlign.value()));<br>
> }<br>
> // If the stack-checking is enabled, and we spilled the callee-saved<br>
> // registers inline (i.e. did not use a spill function), then call<br>
> @@ -1507,7 +1507,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized(<br>
> // via AP, which may not be available at the particular place in the program.<br>
> MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> bool HasAlloca = MFI.hasVarSizedObjects();<br>
> - bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());<br>
> + bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());<br>
><br>
> if (!HasAlloca || !NeedsAlign)<br>
> return;<br>
><br>
> diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
> index e220a0765e2d..388c5feb0e11 100644<br>
> --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
> +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
> @@ -734,8 +734,8 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {<br>
> MachineFrameInfo &MFI = MF->getFrameInfo();<br>
> const HexagonFrameLowering *HFI = HST->getFrameLowering();<br>
> int FX = cast<FrameIndexSDNode>(N)->getIndex();<br>
> - unsigned StkA = HFI->getStackAlignment();<br>
> - unsigned MaxA = MFI.getMaxAlignment();<br>
> + Align StkA = HFI->getStackAlign();<br>
> + Align MaxA = MFI.getMaxAlign();<br>
> SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);<br>
> SDLoc DL(N);<br>
> SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);<br>
> @@ -1284,9 +1284,9 @@ void HexagonDAGToDAGISel::emitFunctionEntryCode() {<br>
> MachineFrameInfo &MFI = MF->getFrameInfo();<br>
> MachineBasicBlock *EntryBB = &MF->front();<br>
> unsigned AR = FuncInfo->CreateReg(MVT::i32);<br>
> - unsigned EntryMaxA = MFI.getMaxAlignment();<br>
> + Align EntryMaxA = MFI.getMaxAlign();<br>
> BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)<br>
> - .addImm(EntryMaxA);<br>
> + .addImm(EntryMaxA.value());<br>
> MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);<br>
> }<br>
><br>
> @@ -1296,7 +1296,7 @@ void HexagonDAGToDAGISel::updateAligna() {<br>
> return;<br>
> auto *AlignaI = const_cast<MachineInstr*>(HFI.getAlignaInstr(*MF));<br>
> assert(AlignaI != nullptr);<br>
> - unsigned MaxA = MF->getFrameInfo().getMaxAlignment();<br>
> + unsigned MaxA = MF->getFrameInfo().getMaxAlign().value();<br>
> if (AlignaI->getOperand(1).getImm() < MaxA)<br>
> AlignaI->getOperand(1).setImm(MaxA);<br>
> }<br>
><br>
> diff --git a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp<br>
> index eddc2b8e61f7..3c84ed057fd1 100644<br>
> --- a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp<br>
> @@ -32,8 +32,8 @@ void LanaiFrameLowering::determineFrameLayout(MachineFunction &MF) const {<br>
> unsigned FrameSize = MFI.getStackSize();<br>
><br>
> // Get the alignment.<br>
> - unsigned StackAlign = LRI->needsStackRealignment(MF) ? MFI.getMaxAlignment()<br>
> - : getStackAlignment();<br>
> + Align StackAlign =<br>
> + LRI->needsStackRealignment(MF) ? MFI.getMaxAlign() : getStackAlign();<br>
><br>
> // Get the maximum call frame size of all the calls.<br>
> unsigned MaxCallFrameSize = MFI.getMaxCallFrameSize();<br>
><br>
> diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp<br>
> index d5a44801dcf2..e0f4f9eab9da 100644<br>
> --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp<br>
> @@ -539,11 +539,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,<br>
> // addiu $Reg, $zero, -MaxAlignment<br>
> // andi $sp, $sp, $Reg<br>
> Register VR = MF.getRegInfo().createVirtualRegister(RC);<br>
> - assert(isInt<16>(MFI.getMaxAlignment()) &&<br>
> + assert((Log2(MFI.getMaxAlign()) < 16) &&<br>
> "Function's alignment size requirement is not supported.");<br>
> - int MaxAlign = -(int)MFI.getMaxAlignment();<br>
> + int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value();<br>
><br>
> - BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);<br>
> + BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign);<br>
> BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);<br>
><br>
> if (hasBP(MF)) {<br>
><br>
> diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
> index 76fe78ee0bfb..6fcadfb5a160 100644<br>
> --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
> +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
> @@ -1634,8 +1634,8 @@ void NVPTXAsmPrinter::setAndEmitFunctionVirtualRegisters(<br>
> const MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> int NumBytes = (int) MFI.getStackSize();<br>
> if (NumBytes) {<br>
> - O << "\t.local .align " << MFI.getMaxAlignment() << " .b8 \t" << DEPOTNAME<br>
> - << getFunctionNumber() << "[" << NumBytes << "];\n";<br>
> + O << "\t.local .align " << MFI.getMaxAlign().value() << " .b8 \t"<br>
> + << DEPOTNAME << getFunctionNumber() << "[" << NumBytes << "];\n";<br>
> if (static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit()) {<br>
> O << "\t.reg .b64 \t%SP;\n";<br>
> O << "\t.reg .b64 \t%SPL;\n";<br>
><br>
> diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
> index 4b91ca8368db..93695a854c24 100644<br>
> --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp<br>
> @@ -437,9 +437,9 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,<br>
> UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();<br>
><br>
> // Get stack alignments. The frame must be aligned to the greatest of these:<br>
> - unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI<br>
> - unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame<br>
> - unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;<br>
> + Align TargetAlign = getStackAlign(); // alignment required per the ABI<br>
> + Align MaxAlign = MFI.getMaxAlign(); // algmt required by data in frame<br>
> + Align Alignment = std::max(TargetAlign, MaxAlign);<br>
><br>
> const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();<br>
><br>
> @@ -471,7 +471,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,<br>
> // If we have dynamic alloca then maxCallFrameSize needs to be aligned so<br>
> // that allocations will be aligned.<br>
> if (MFI.hasVarSizedObjects())<br>
> - maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;<br>
> + maxCallFrameSize = alignTo(maxCallFrameSize, Alignment);<br>
><br>
> // Update the new max call frame size if the caller passes in a valid pointer.<br>
> if (NewMaxCallFrameSize)<br>
> @@ -481,7 +481,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,<br>
> FrameSize += maxCallFrameSize;<br>
><br>
> // Make sure the frame is aligned.<br>
> - FrameSize = (FrameSize + AlignMask) & ~AlignMask;<br>
> + FrameSize = alignTo(FrameSize, Alignment);<br>
><br>
> return FrameSize;<br>
> }<br>
> @@ -667,7 +667,7 @@ PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {<br>
> int NegFrameSize = -FrameSize;<br>
> bool IsLargeFrame = !isInt<16>(NegFrameSize);<br>
> MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> - unsigned MaxAlign = MFI.getMaxAlignment();<br>
> + Align MaxAlign = MFI.getMaxAlign();<br>
> bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();<br>
><br>
> return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;<br>
> @@ -867,10 +867,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,<br>
> }<br>
><br>
> // Get stack alignments.<br>
> - unsigned MaxAlign = MFI.getMaxAlignment();<br>
> + Align MaxAlign = MFI.getMaxAlign();<br>
> if (HasBP && MaxAlign > 1)<br>
> - assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&<br>
> - "Invalid alignment!");<br>
> + assert(Log2(MaxAlign) < 16 && "Invalid alignment!");<br>
><br>
> // Frames of 32KB & larger require special handling because they cannot be<br>
> // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.<br>
> @@ -1007,15 +1006,15 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,<br>
> if (HasBP && MaxAlign > 1) {<br>
> if (isPPC64)<br>
> BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)<br>
> - .addReg(SPReg)<br>
> - .addImm(0)<br>
> - .addImm(64 - Log2_32(MaxAlign));<br>
> + .addReg(SPReg)<br>
> + .addImm(0)<br>
> + .addImm(64 - Log2(MaxAlign));<br>
> else // PPC32...<br>
> BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)<br>
> - .addReg(SPReg)<br>
> - .addImm(0)<br>
> - .addImm(32 - Log2_32(MaxAlign))<br>
> - .addImm(31);<br>
> + .addReg(SPReg)<br>
> + .addImm(0)<br>
> + .addImm(32 - Log2(MaxAlign))<br>
> + .addImm(31);<br>
> if (!isLargeFrame) {<br>
> BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)<br>
> .addReg(ScratchReg, RegState::Kill)<br>
> @@ -2058,8 +2057,8 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,<br>
> RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));<br>
><br>
> // Might we have over-aligned allocas?<br>
> - bool HasAlVars = MFI.hasVarSizedObjects() &&<br>
> - MFI.getMaxAlignment() > getStackAlignment();<br>
> + bool HasAlVars =<br>
> + MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign();<br>
><br>
> // These kinds of spills might need two registers.<br>
> if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)<br>
><br>
> diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp<br>
> index caa9d7b6b869..35d3c420c3c3 100644<br>
> --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp<br>
> +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp<br>
> @@ -499,7 +499,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {<br>
> // Get stack alignments.<br>
> const PPCFrameLowering *TFI = getFrameLowering(MF);<br>
> unsigned TargetAlign = TFI->getStackAlignment();<br>
> - unsigned MaxAlign = MFI.getMaxAlignment();<br>
> + unsigned MaxAlign = MFI.getMaxAlign().value();<br>
> assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&<br>
> "Maximum call-frame size not sufficiently aligned");<br>
><br>
><br>
> diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp<br>
> index 072f0d902cc3..927e8534ece8 100644<br>
> --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp<br>
> @@ -142,10 +142,10 @@ void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {<br>
> uint64_t FrameSize = MFI.getStackSize();<br>
><br>
> // Get the alignment.<br>
> - unsigned StackAlign = getStackAlignment();<br>
> + Align StackAlign = getStackAlign();<br>
> if (RI->needsStackRealignment(MF)) {<br>
> - unsigned MaxStackAlign = std::max(StackAlign, MFI.getMaxAlignment());<br>
> - FrameSize += (MaxStackAlign - StackAlign);<br>
> + Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());<br>
> + FrameSize += (MaxStackAlign.value() - StackAlign.value());<br>
> StackAlign = MaxStackAlign;<br>
> }<br>
><br>
> @@ -359,15 +359,15 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,<br>
> // Realign Stack<br>
> const RISCVRegisterInfo *RI = STI.getRegisterInfo();<br>
> if (RI->needsStackRealignment(MF)) {<br>
> - unsigned MaxAlignment = MFI.getMaxAlignment();<br>
> + Align MaxAlignment = MFI.getMaxAlign();<br>
><br>
> const RISCVInstrInfo *TII = STI.getInstrInfo();<br>
> - if (isInt<12>(-(int)MaxAlignment)) {<br>
> + if (isInt<12>(-(int)MaxAlignment.value())) {<br>
> BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)<br>
> .addReg(SPReg)<br>
> - .addImm(-(int)MaxAlignment);<br>
> + .addImm(-(int)MaxAlignment.value());<br>
> } else {<br>
> - unsigned ShiftAmount = countTrailingZeros(MaxAlignment);<br>
> + unsigned ShiftAmount = Log2(MaxAlignment);<br>
> Register VR =<br>
> MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);<br>
> BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)<br>
><br>
> diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp<br>
> index 0f74f2bb344c..6bb3a51df0c3 100644<br>
> --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp<br>
> @@ -104,7 +104,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,<br>
> // rather than reporting an error, as would be sensible. This is<br>
> // poor, but fixing that bogosity is going to be a large project.<br>
> // For now, just see if it's lied, and report an error here.<br>
> - if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())<br>
> + if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign())<br>
> report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "<br>
> "stack re-alignment, but LLVM couldn't handle it "<br>
> "(probably because it has a dynamic alloca).");<br>
> @@ -146,9 +146,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,<br>
><br>
> // Finally, ensure that the size is sufficiently aligned for the<br>
> // data on the stack.<br>
> - if (MFI.getMaxAlignment() > 0) {<br>
> - NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());<br>
> - }<br>
> + NumBytes = alignTo(NumBytes, MFI.getMaxAlign());<br>
><br>
> // Update stack size with corrected value.<br>
> MFI.setStackSize(NumBytes);<br>
> @@ -189,9 +187,10 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,<br>
> regUnbiased = SP::O6;<br>
><br>
> // andn %regUnbiased, MaxAlign-1, %regUnbiased<br>
> - int MaxAlign = MFI.getMaxAlignment();<br>
> + Align MaxAlign = MFI.getMaxAlign();<br>
> BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)<br>
> - .addReg(regUnbiased).addImm(MaxAlign - 1);<br>
> + .addReg(regUnbiased)<br>
> + .addImm(MaxAlign.value() - 1U);<br>
><br>
> if (Bias) {<br>
> // add %g1, -BIAS, %o6<br>
><br>
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp<br>
> index 21b81d8cd0ed..036c2aee0050 100644<br>
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp<br>
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp<br>
> @@ -201,11 +201,9 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF,<br>
> }<br>
> if (HasBP) {<br>
> Register BitmaskReg = MRI.createVirtualRegister(PtrRC);<br>
> - unsigned Alignment = MFI.getMaxAlignment();<br>
> - assert((1u << countTrailingZeros(Alignment)) == Alignment &&<br>
> - "Alignment must be a power of 2");<br>
> + Align Alignment = MFI.getMaxAlign();<br>
> BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), BitmaskReg)<br>
> - .addImm((int)~(Alignment - 1));<br>
> + .addImm((int)~(Alignment.value() - 1));<br>
> BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::AND_I32),<br>
> WebAssembly::SP32)<br>
> .addReg(WebAssembly::SP32)<br>
><br>
> diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp<br>
> index 9d7d5b7a6f18..1661497849d1 100644<br>
> --- a/llvm/lib/Target/X86/X86FrameLowering.cpp<br>
> +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp<br>
> @@ -1042,15 +1042,15 @@ static unsigned calculateSetFPREG(uint64_t SPAdjust) {<br>
> // go with the minimum SlotSize.<br>
> uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {<br>
> const MachineFrameInfo &MFI = MF.getFrameInfo();<br>
> - uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.<br>
> - unsigned StackAlign = getStackAlignment();<br>
> + Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.<br>
> + Align StackAlign = getStackAlign();<br>
> if (MF.getFunction().hasFnAttribute("stackrealign")) {<br>
> if (MFI.hasCalls())<br>
> MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;<br>
> else if (MaxAlign < SlotSize)<br>
> - MaxAlign = SlotSize;<br>
> + MaxAlign = Align(SlotSize);<br>
> }<br>
> - return MaxAlign;<br>
> + return MaxAlign.value();<br>
> }<br>
><br>
> void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,<br>
><br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
> <a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>