<div dir="ltr">Hello Matt,<br><br>Your commit broke the test to couple of our builders:<br><br><a href="http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/15535">http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/15535</a><br><a href="http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu">http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu</a><br><br>. . .<br>Failing Tests (1):<br> LLVM :: CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir<br> <br>Please have a look ASAP?<br> <br>Thanks<br> <br>Galina</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Jan 27, 2020 at 7:14 AM Matt Arsenault via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Matt Arsenault<br>
Date: 2020-01-27T07:13:56-08:00<br>
New Revision: fdaad485e620de39ea578e02535c6e75e44581ff<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/fdaad485e620de39ea578e02535c6e75e44581ff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/fdaad485e620de39ea578e02535c6e75e44581ff</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/fdaad485e620de39ea578e02535c6e75e44581ff.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/fdaad485e620de39ea578e02535c6e75e44581ff.diff</a><br>
<br>
LOG: AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store<br>
<br>
Fixes the main reason for compile failures on SI, but doesn't really<br>
try to use the addressing modes yet.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/Target/AMDGPU/AMDGPUGISel.td<br>
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp<br>
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.append.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.consume.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td<br>
index 44b27dde14cc..5cbbc283821f 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td<br>
@@ -84,6 +84,10 @@ def gi_ds_1addr_1offset :<br>
GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">,<br>
GIComplexPatternEquiv<DS1Addr1Offset>;<br>
<br>
+def gi_mubuf_addr64 :<br>
+ GIComplexOperandMatcher<s64, "selectMUBUFAddr64">,<br>
+ GIComplexPatternEquiv<MUBUFAddr64>;<br>
+<br>
<br>
// Separate load nodes are defined to glue m0 initialization in<br>
// SelectionDAG. The GISel selector can just insert m0 initialization<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp<br>
index 2b6308dc1549..eb4c4e0eba01 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp<br>
@@ -1343,6 +1343,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,<br>
SDValue &TFE, SDValue &DLC,<br>
SDValue &SWZ) const {<br>
// Subtarget prefers to use flat instruction<br>
+ // FIXME: This should be a pattern predicate and not reach here<br>
if (Subtarget->useFlatForGlobal())<br>
return false;<br>
<br>
@@ -1438,6 +1439,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,<br>
SDValue Ptr, Offen, Idxen, Addr64;<br>
<br>
// addr64 bit was removed for volcanic islands.<br>
+ // FIXME: This should be a pattern predicate and not reach here<br>
if (!Subtarget->hasAddr64())<br>
return false;<br>
<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
index ce47e56da02a..c580e72aefbb 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
@@ -2552,6 +2552,84 @@ AMDGPUInstructionSelector::selectDS1Addr1Offset(MachineOperand &Root) const {<br>
}};<br>
}<br>
<br>
+static void addZeroImm(MachineInstrBuilder &MIB) {<br>
+ MIB.addImm(0);<br>
+}<br>
+<br>
+/// Return a resource descriptor for use with an arbitrary 64-bit pointer. If \p<br>
+/// BasePtr is not valid, a null base pointer will be ussed.<br>
+static Register buildRSrc(MachineInstr *MI, MachineRegisterInfo &MRI,<br>
+ const SIInstrInfo &TII, Register BasePtr) {<br>
+ Register RSrc2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);<br>
+ Register RSrc3 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);<br>
+ Register RSrcHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);<br>
+ Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);<br>
+<br>
+ const DebugLoc &DL = MI->getDebugLoc();<br>
+ MachineBasicBlock *BB = MI->getParent();<br>
+<br>
+ // TODO: Try to use a real pointer if available.<br>
+ BuildMI(*BB, MI, DL, TII.get(AMDGPU::S_MOV_B32), RSrc2)<br>
+ .addImm(0);<br>
+ BuildMI(*BB, MI, DL, TII.get(AMDGPU::S_MOV_B32), RSrc3)<br>
+ .addImm(TII.getDefaultRsrcDataFormat() >> 32);<br>
+<br>
+ // Build the half of the subregister with the constants before building the<br>
+ // full 128-bit register. If we are building multiple resource descriptors,<br>
+ // this will allow CSEing of the 2-component register.<br>
+ BuildMI(*BB, MI, DL, TII.get(AMDGPU::REG_SEQUENCE), RSrcHi)<br>
+ .addReg(RSrc2)<br>
+ .addImm(AMDGPU::sub0)<br>
+ .addReg(RSrc3)<br>
+ .addImm(AMDGPU::sub1);<br>
+<br>
+ Register RSrcLo = BasePtr;<br>
+ if (!BasePtr) {<br>
+ RSrcLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);<br>
+ BuildMI(*BB, MI, DL, TII.get(AMDGPU::S_MOV_B64), RSrcLo)<br>
+ .addImm(0);<br>
+ }<br>
+<br>
+ BuildMI(*BB, MI, DL, TII.get(AMDGPU::REG_SEQUENCE), RSrc)<br>
+ .addReg(RSrcLo)<br>
+ .addImm(AMDGPU::sub0_sub1)<br>
+ .addReg(RSrcHi)<br>
+ .addImm(AMDGPU::sub2_sub3);<br>
+<br>
+ return RSrc;<br>
+}<br>
+<br>
+InstructionSelector::ComplexRendererFns<br>
+AMDGPUInstructionSelector::selectMUBUFAddr64(MachineOperand &Root) const {<br>
+ // FIXME: Predicates should stop this from reaching here.<br>
+ // addr64 bit was removed for volcanic islands.<br>
+ if (!STI.hasAddr64() || STI.useFlatForGlobal())<br>
+ return {};<br>
+<br>
+ MachineInstr *MI = MRI->getVRegDef(Root.getReg());<br>
+ Register VAddr = Root.getReg();<br>
+ int64_t Offset = 0;<br>
+<br>
+ // TODO: Attempt to use addressing modes. We need to look back through regbank<br>
+ // copies to find a 64-bit SGPR base and VGPR offset.<br>
+<br>
+ // FIXME: Use defaulted operands for trailing 0s and remove from the complex<br>
+ // pattern.<br>
+ return {{<br>
+ [=](MachineInstrBuilder &MIB) { // rsrc<br>
+ MIB.addReg(buildRSrc(MI, *MRI, TII, Register()));<br>
+ },<br>
+ [=](MachineInstrBuilder &MIB) { MIB.addReg(VAddr); }, // vaddr<br>
+ [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // soffset<br>
+ addZeroImm, // offset<br>
+ addZeroImm, // glc<br>
+ addZeroImm, // slc<br>
+ addZeroImm, // tfe<br>
+ addZeroImm, // dlc<br>
+ addZeroImm // swz<br>
+ }};<br>
+}<br>
+<br>
void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB,<br>
const MachineInstr &MI,<br>
int OpIdx) const {<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h<br>
index d7dc8de3677d..94019ddf8ff5 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h<br>
@@ -180,6 +180,9 @@ class AMDGPUInstructionSelector : public InstructionSelector {<br>
InstructionSelector::ComplexRendererFns<br>
selectDS1Addr1Offset(MachineOperand &Root) const;<br>
<br>
+ InstructionSelector::ComplexRendererFns<br>
+ selectMUBUFAddr64(MachineOperand &Root) const;<br>
+<br>
void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,<br>
int OpIdx = -1) const;<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll<br>
index bf4a3a254c12..eebfbee8a12e 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll<br>
@@ -1,5 +1,5 @@<br>
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s<br>
+; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s<br>
<br>
; End to end tests for scalar vs. vector boolean legalization strategies.<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir<br>
index 1afa71ec4a30..e600aa0e1805 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir<br>
@@ -1,6 +1,6 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s<br>
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s<br>
<br>
---<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir<br>
index b69776bb7b39..636b1d2dda69 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
<br>
---<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir<br>
index 0b82dd159d97..020e171d3fd5 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
<br>
# FIXME: Ideally this would fail to select with ieee mode enabled.<br>
---<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir<br>
index b5d9c8851bff..d6ac32e41543 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
<br>
---<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir<br>
index 2f7319c57ac4..1f4decb7826a 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s<br>
<br>
# FIXME: Ideally this would fail to select with ieee mode enabled.<br>
---<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir<br>
index eb4a5484d1ad..e6736f2d7147 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN<br>
<br>
---<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir<br>
index 17da10515a36..b4ac02a72f61 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s<br>
# XUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s<br>
<br>
---<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir<br>
index 1920b6b9f3bb..6321080d6bec 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir<br>
@@ -1,4 +1,4 @@<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN<br>
<br>
---<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir<br>
index 2e1a2ea089eb..ed7007fe5818 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir<br>
@@ -1,6 +1,7 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s<br>
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7-FLAT %s<br>
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s<br>
<br>
---<br>
@@ -16,14 +17,29 @@ body: |<br>
<br>
; GFX6-LABEL: name: load_atomic_global_s32_seq_cst<br>
; GFX6: liveins: $vgpr0_vgpr1<br>
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
- ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(s32) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)<br>
- ; GFX6: $vgpr0 = COPY [[LOAD]](s32)<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
; GFX7-LABEL: name: load_atomic_global_s32_seq_cst<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
+ ; GFX7: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_s32_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
; GFX9-LABEL: name: load_atomic_global_s32_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -56,6 +72,11 @@ body: |<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)<br>
; GFX7: $vgpr0 = COPY [[LOAD]](<2 x s16>)<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_v2s16_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[LOAD]](<2 x s16>)<br>
; GFX9-LABEL: name: load_atomic_global_v2s16_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -88,6 +109,11 @@ body: |<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)<br>
; GFX7: $vgpr0 = COPY [[LOAD]](p3)<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_p3_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[LOAD]](p3)<br>
; GFX9-LABEL: name: load_atomic_global_p3_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -112,14 +138,29 @@ body: |<br>
<br>
; GFX6-LABEL: name: load_atomic_global_s64_seq_cst<br>
; GFX6: liveins: $vgpr0_vgpr1<br>
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
- ; GFX6: [[LOAD:%[0-9]+]]:vreg_64(s64) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
- ; GFX6: $vgpr0_vgpr1 = COPY [[LOAD]](s64)<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORDX2_ADDR64_:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[BUFFER_LOAD_DWORDX2_ADDR64_]]<br>
; GFX7-LABEL: name: load_atomic_global_s64_seq_cst<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 8, addrspace 1)<br>
- ; GFX7: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
+ ; GFX7: [[BUFFER_LOAD_DWORDX2_ADDR64_:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX7: $vgpr0_vgpr1 = COPY [[BUFFER_LOAD_DWORDX2_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_s64_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
; GFX9-LABEL: name: load_atomic_global_s64_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -152,6 +193,11 @@ body: |<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_64(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_v2s32_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_64(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)<br>
; GFX9-LABEL: name: load_atomic_global_v2s32_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -184,6 +230,11 @@ body: |<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_v4s16_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)<br>
; GFX9-LABEL: name: load_atomic_global_v4s16_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -216,6 +267,11 @@ body: |<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_64(p1) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](p1)<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_p1_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_64(p1) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)<br>
; GFX9-LABEL: name: load_atomic_global_p1_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -248,6 +304,11 @@ body: |<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_64(p0) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](p0)<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_p0_seq_cst<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_64(p0) = G_LOAD [[COPY]](p1) :: (load seq_cst 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[LOAD]](p0)<br>
; GFX9-LABEL: name: load_atomic_global_p0_seq_cst<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -272,26 +333,59 @@ body: |<br>
<br>
; GFX6-LABEL: name: load_atomic_global_s32_seq_cst_gep_m2048<br>
; GFX6: liveins: $vgpr0_vgpr1<br>
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
- ; GFX6: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 -2048<br>
- ; GFX6: [[GEP:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64)<br>
- ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(s32) = G_LOAD [[GEP]](p1) :: (load seq_cst 4, addrspace 1)<br>
- ; GFX6: $vgpr0 = COPY [[LOAD]](s32)<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
; GFX7-LABEL: name: load_atomic_global_s32_seq_cst_gep_m2048<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_s32_seq_cst_gep_m2048<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
; GFX9-LABEL: name: load_atomic_global_s32_seq_cst_gep_m2048<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -328,26 +422,59 @@ body: |<br>
<br>
; GFX6-LABEL: name: load_atomic_global_s32_seq_cst_gep_4095<br>
; GFX6: liveins: $vgpr0_vgpr1<br>
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
- ; GFX6: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 4095<br>
- ; GFX6: [[GEP:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64)<br>
- ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(s32) = G_LOAD [[GEP]](p1) :: (load seq_cst 4, addrspace 1)<br>
- ; GFX6: $vgpr0 = COPY [[LOAD]](s32)<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
; GFX7-LABEL: name: load_atomic_global_s32_seq_cst_gep_4095<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_atomic_global_s32_seq_cst_gep_4095<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
; GFX9-LABEL: name: load_atomic_global_s32_seq_cst_gep_4095<br>
; GFX9: liveins: $vgpr0_vgpr1<br>
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir<br>
index 2c070d65565d..3bbc8f0e016d 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir<br>
@@ -1,5 +1,7 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s<br>
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7-FLAT %s<br>
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s<br>
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s<br>
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX10 %s<br>
@@ -18,11 +20,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_4<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_4<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
+ ; GFX7: [[BUFFER_LOAD_DWORD_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_4<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
; GFX8-LABEL: name: load_global_s32_from_4<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -56,11 +78,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_2<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_USHORT_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 2, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_2<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_USHORT:%[0-9]+]]:vgpr_32 = FLAT_LOAD_USHORT [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 2, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_USHORT]]<br>
+ ; GFX7: [[BUFFER_LOAD_USHORT_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 2, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_2<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_USHORT:%[0-9]+]]:vgpr_32 = FLAT_LOAD_USHORT [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 2, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_USHORT]]<br>
; GFX8-LABEL: name: load_global_s32_from_2<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -94,11 +136,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -132,11 +194,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v2s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORDX2_ADDR64_:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[BUFFER_LOAD_DWORDX2_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_v2s32<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
- ; GFX7: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
+ ; GFX7: [[BUFFER_LOAD_DWORDX2_ADDR64_:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 8, addrspace 1)<br>
+ ; GFX7: $vgpr0_vgpr1 = COPY [[BUFFER_LOAD_DWORDX2_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v2s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
; GFX8-LABEL: name: load_global_v2s32<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -170,11 +252,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v3s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORDX3_ADDR64_:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[BUFFER_LOAD_DWORDX3_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_v3s32<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = FLAT_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 12, align 4, addrspace 1)<br>
- ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[FLAT_LOAD_DWORDX3_]]<br>
+ ; GFX7: [[BUFFER_LOAD_DWORDX3_ADDR64_:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)<br>
+ ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[BUFFER_LOAD_DWORDX3_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v3s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = FLAT_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 12, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[FLAT_LOAD_DWORDX3_]]<br>
; GFX8-LABEL: name: load_global_v3s32<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -208,11 +310,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v4s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[BUFFER_LOAD_DWORDX4_ADDR64_:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 16, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUFFER_LOAD_DWORDX4_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_v4s32<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
- ; GFX7: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = FLAT_LOAD_DWORDX4 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16, align 4, addrspace 1)<br>
- ; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[FLAT_LOAD_DWORDX4_]]<br>
+ ; GFX7: [[BUFFER_LOAD_DWORDX4_ADDR64_:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 16, align 4, addrspace 1)<br>
+ ; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUFFER_LOAD_DWORDX4_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v4s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = FLAT_LOAD_DWORDX4 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[FLAT_LOAD_DWORDX4_]]<br>
; GFX8-LABEL: name: load_global_v4s32<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -246,11 +368,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s64<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_64(s64) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[LOAD]](s64)<br>
; GFX7-LABEL: name: load_global_s64<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s64<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
; GFX8-LABEL: name: load_global_s64<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -284,11 +416,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v2s64<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_128(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)<br>
; GFX7-LABEL: name: load_global_v2s64<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = FLAT_LOAD_DWORDX4 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16, align 4, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[FLAT_LOAD_DWORDX4_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v2s64<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = FLAT_LOAD_DWORDX4 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[FLAT_LOAD_DWORDX4_]]<br>
; GFX8-LABEL: name: load_global_v2s64<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -322,11 +464,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v2p1<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_128(<2 x p1>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x p1>)<br>
; GFX7-LABEL: name: load_global_v2p1<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_128(<2 x p1>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x p1>)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v2p1<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_128(<2 x p1>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x p1>)<br>
; GFX8-LABEL: name: load_global_v2p1<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -359,11 +511,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s96<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)<br>
; GFX7-LABEL: name: load_global_s96<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s96<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)<br>
; GFX8-LABEL: name: load_global_s96<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -396,11 +558,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s128<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_128(s128) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](s128)<br>
; GFX7-LABEL: name: load_global_s128<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_128(s128) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](s128)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s128<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_128(s128) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](s128)<br>
; GFX8-LABEL: name: load_global_s128<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -433,11 +605,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_p3_from_4<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[LOAD]](p3)<br>
; GFX7-LABEL: name: load_global_p3_from_4<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)<br>
; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_p3_from_4<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
; GFX8-LABEL: name: load_global_p3_from_4<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -471,11 +653,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_p1_from_8<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_64(p1) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[LOAD]](p1)<br>
; GFX7-LABEL: name: load_global_p1_from_8<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_p1_from_8<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
; GFX8-LABEL: name: load_global_p1_from_8<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -509,11 +701,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_p999_from_8<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_64(p999) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[LOAD]](p999)<br>
; GFX7-LABEL: name: load_global_p999_from_8<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_64(p999) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](p999)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_p999_from_8<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_64(p999) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[LOAD]](p999)<br>
; GFX8-LABEL: name: load_global_p999_from_8<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -546,11 +748,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v2p3<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_64(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)<br>
; GFX7-LABEL: name: load_global_v2p3<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_64(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v2p3<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_64(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)<br>
; GFX8-LABEL: name: load_global_v2p3<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -583,11 +795,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v2s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[LOAD]](<2 x s16>)<br>
; GFX7-LABEL: name: load_global_v2s16<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)<br>
; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v2s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]<br>
; GFX8-LABEL: name: load_global_v2s16<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -621,11 +843,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v4s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)<br>
; GFX7-LABEL: name: load_global_v4s16<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v4s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 8, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]<br>
; GFX8-LABEL: name: load_global_v4s16<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -659,11 +891,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v6s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vgpr(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)<br>
; GFX7-LABEL: name: load_global_v6s16<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v6s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)<br>
; GFX8-LABEL: name: load_global_v6s16<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -696,11 +938,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_v8s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[LOAD:%[0-9]+]]:vreg_128(<8 x s16>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<8 x s16>)<br>
; GFX7-LABEL: name: load_global_v8s16<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[LOAD:%[0-9]+]]:vreg_128(<8 x s16>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<8 x s16>)<br>
+ ; GFX7-FLAT-LABEL: name: load_global_v8s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_128(<8 x s16>) = G_LOAD [[COPY]](p1) :: (load 16, align 4, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<8 x s16>)<br>
; GFX8-LABEL: name: load_global_v8s16<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -737,21 +989,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_2047<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_2047<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_2047<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_2047<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -797,21 +1089,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_2048<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2048, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_2048<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2048, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_2048<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2048, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_2048<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -867,21 +1199,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_m2047<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965249, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_m2047<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965249, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_m2047<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965249, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_m2047<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -927,21 +1299,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_m2048<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_m2048<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_m2048<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_m2048<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -987,21 +1399,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_4095<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_4095<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_4095<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_4095<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1057,21 +1509,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_4096<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_4096<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_4096<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_4096<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1137,21 +1629,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_m4095<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963201, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_m4095<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963201, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_m4095<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963201, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_m4095<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1207,21 +1739,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_m4096<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963200, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_m4096<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963200, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_m4096<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963200, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_m4096<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1277,21 +1849,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_8191<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8191, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_8191<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8191, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_8191<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8191, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_8191<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1357,21 +1969,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_8192<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8192, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_8192<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8192, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_8192<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8192, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_8192<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1437,21 +2089,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_m8191<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294959105, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_m8191<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294959105, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_m8191<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294959105, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_m8191<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -1517,21 +2209,61 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1<br>
<br>
+ ; GFX6-LABEL: name: load_global_s32_from_1_gep_m8192<br>
+ ; GFX6: liveins: $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294959104, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
; GFX7-LABEL: name: load_global_s32_from_1_gep_m8192<br>
; GFX7: liveins: $vgpr0_vgpr1<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294959104, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
- ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: [[BUFFER_LOAD_UBYTE_ADDR64_:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 1, addrspace 1)<br>
+ ; GFX7: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_ADDR64_]]<br>
+ ; GFX7-FLAT-LABEL: name: load_global_s32_from_1_gep_m8192<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294959104, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 1, addrspace 1)<br>
+ ; GFX7-FLAT: $vgpr0 = COPY [[FLAT_LOAD_UBYTE]]<br>
; GFX8-LABEL: name: load_global_s32_from_1_gep_m8192<br>
; GFX8: liveins: $vgpr0_vgpr1<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir<br>
index 3e0de2289aaa..e68fda19d493 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir<br>
@@ -1,6 +1,6 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s<br>
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s<br>
<br>
---<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir<br>
index 8486edd6c744..04735c7c5ac9 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir<br>
@@ -1,5 +1,7 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s<br>
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s<br>
+# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7-FLAT %s<br>
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s<br>
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s<br>
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX10 %s<br>
@@ -15,11 +17,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_global_s32_to_4<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX6: BUFFER_STORE_DWORD_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s32_to_4<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
- ; GFX7: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
+ ; GFX7: BUFFER_STORE_DWORD_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s32_to_4<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s32_to_4<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -52,11 +74,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_global_s32_to_2<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX6: BUFFER_STORE_SHORT_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 2, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s32_to_2<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
- ; GFX7: FLAT_STORE_SHORT [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 2, addrspace 1)<br>
+ ; GFX7: BUFFER_STORE_SHORT_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 2, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s32_to_2<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX7-FLAT: FLAT_STORE_SHORT [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 2, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s32_to_2<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -89,11 +131,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_global_s32_to_1<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX6: BUFFER_STORE_BYTE_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s32_to_1<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
- ; GFX7: FLAT_STORE_BYTE [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 1, addrspace 1)<br>
+ ; GFX7: BUFFER_STORE_BYTE_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s32_to_1<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX7-FLAT: FLAT_STORE_BYTE [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 1, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s32_to_1<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -127,11 +189,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
<br>
+ ; GFX6-LABEL: name: store_global_s64<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3<br>
+ ; GFX6: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store 8, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s64<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
; GFX7: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s64<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s64<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -164,11 +236,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
<br>
+ ; GFX6-LABEL: name: store_global_s96<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s96) = COPY $vgpr2_vgpr3_vgpr4<br>
+ ; GFX6: G_STORE [[COPY1]](s96), [[COPY]](p1) :: (store 12, align 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s96<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(s96) = COPY $vgpr2_vgpr3_vgpr4<br>
; GFX7: G_STORE [[COPY1]](s96), [[COPY]](p1) :: (store 12, align 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s96<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(s96) = COPY $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](s96), [[COPY]](p1) :: (store 12, align 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s96<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -200,11 +282,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
<br>
+ ; GFX6-LABEL: name: store_global_s128<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: G_STORE [[COPY1]](s128), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s128<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: G_STORE [[COPY1]](s128), [[COPY]](p1) :: (store 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s128<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](s128), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s128<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -237,11 +329,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
<br>
+ ; GFX6-LABEL: name: store_global_v2s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
+ ; GFX6: BUFFER_STORE_DWORDX2_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v2s32<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
- ; GFX7: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
+ ; GFX7: BUFFER_STORE_DWORDX2_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v2s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v2s32<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -274,11 +386,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
<br>
+ ; GFX6-LABEL: name: store_global_v3s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_96 = COPY $vgpr2_vgpr3_vgpr4<br>
+ ; GFX6: BUFFER_STORE_DWORDX3_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 12, align 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v3s32<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_96 = COPY $vgpr2_vgpr3_vgpr4<br>
- ; GFX7: FLAT_STORE_DWORDX3 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 12, align 16, addrspace 1)<br>
+ ; GFX7: BUFFER_STORE_DWORDX3_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 12, align 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v3s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_96 = COPY $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX3 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 12, align 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v3s32<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -311,11 +443,31 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
<br>
+ ; GFX6-LABEL: name: store_global_v4s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: BUFFER_STORE_DWORDX4_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v4s32<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
- ; GFX7: FLAT_STORE_DWORDX4 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 16, addrspace 1)<br>
+ ; GFX7: BUFFER_STORE_DWORDX4_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v4s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX4 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v4s32<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -349,11 +501,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_global_v2s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr2<br>
+ ; GFX6: G_STORE [[COPY1]](<2 x s16>), [[COPY]](p1) :: (store 4, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v2s16<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
; GFX7: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v2s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v2s16<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -387,11 +549,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
<br>
+ ; GFX6-LABEL: name: store_global_v4s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3<br>
+ ; GFX6: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store 8, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v4s16<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
; GFX7: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v4s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v4s16<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -425,11 +597,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
<br>
+ ; GFX6-LABEL: name: store_global_v6s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<6 x s16>) = COPY $vgpr2_vgpr3_vgpr4<br>
+ ; GFX6: G_STORE [[COPY1]](<6 x s16>), [[COPY]](p1) :: (store 12, align 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v6s16<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(<6 x s16>) = COPY $vgpr2_vgpr3_vgpr4<br>
; GFX7: G_STORE [[COPY1]](<6 x s16>), [[COPY]](p1) :: (store 12, align 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v6s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(<6 x s16>) = COPY $vgpr2_vgpr3_vgpr4<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](<6 x s16>), [[COPY]](p1) :: (store 12, align 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v6s16<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -461,11 +643,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
<br>
+ ; GFX6-LABEL: name: store_global_v8s16<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: G_STORE [[COPY1]](<8 x s16>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v8s16<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: G_STORE [[COPY1]](<8 x s16>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v8s16<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](<8 x s16>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v8s16<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -498,11 +690,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
<br>
+ ; GFX6-LABEL: name: store_global_v2s64<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v2s64<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: FLAT_STORE_DWORDX4 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v2s64<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX4 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v2s64<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -536,11 +738,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
<br>
+ ; GFX6-LABEL: name: store_global_p1<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY $vgpr2_vgpr3<br>
+ ; GFX6: G_STORE [[COPY1]](p1), [[COPY]](p1) :: (store 8, addrspace 1)<br>
; GFX7-LABEL: name: store_global_p1<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
; GFX7: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_p1<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORDX2 [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 8, addrspace 1)<br>
; GFX8-LABEL: name: store_global_p1<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -574,11 +786,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
<br>
+ ; GFX6-LABEL: name: store_global_v2p1<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x p1>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX6: G_STORE [[COPY1]](<2 x p1>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v2p1<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x p1>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX7: G_STORE [[COPY1]](<2 x p1>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v2p1<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(<2 x p1>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](<2 x p1>), [[COPY]](p1) :: (store 16, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v2p1<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -611,11 +833,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_global_p3<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr2<br>
+ ; GFX6: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store 4, addrspace 1)<br>
; GFX7-LABEL: name: store_global_p3<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
; GFX7: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_p3<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
; GFX8-LABEL: name: store_global_p3<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -649,11 +881,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
<br>
+ ; GFX6-LABEL: name: store_global_v2p3<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x p3>) = COPY $vgpr2_vgpr3<br>
+ ; GFX6: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store 8, addrspace 1)<br>
; GFX7-LABEL: name: store_global_v2p3<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x p3>) = COPY $vgpr2_vgpr3<br>
; GFX7: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store 8, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_v2p3<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(<2 x p3>) = COPY $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store 8, addrspace 1)<br>
; GFX8-LABEL: name: store_global_v2p3<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -685,11 +927,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_atomic_global_s32<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2<br>
+ ; GFX6: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store monotonic 4, addrspace 1)<br>
; GFX7-LABEL: name: store_atomic_global_s32<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2<br>
; GFX7: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store monotonic 4, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_atomic_global_s32<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store monotonic 4, addrspace 1)<br>
; GFX8-LABEL: name: store_atomic_global_s32<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -722,11 +974,21 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
<br>
+ ; GFX6-LABEL: name: store_atomic_global_s64<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3<br>
+ ; GFX6: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store monotonic 8, addrspace 1)<br>
; GFX7-LABEL: name: store_atomic_global_s64<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3<br>
; GFX7: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store monotonic 8, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_atomic_global_s64<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3<br>
+ ; GFX7-FLAT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store monotonic 8, addrspace 1)<br>
; GFX8-LABEL: name: store_atomic_global_s64<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3<br>
; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1<br>
@@ -759,6 +1021,26 @@ body: |<br>
bb.0:<br>
liveins: $vgpr0_vgpr1, $vgpr2<br>
<br>
+ ; GFX6-LABEL: name: store_global_s32_gep_2047<br>
+ ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec<br>
+ ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX6: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX6: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec<br>
+ ; GFX6: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX6: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX6: BUFFER_STORE_DWORD_ADDR64 [[COPY1]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)<br>
; GFX7-LABEL: name: store_global_s32_gep_2047<br>
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
@@ -766,14 +1048,34 @@ body: |<br>
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec<br>
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0<br>
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440<br>
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1<br>
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0<br>
+ ; GFX7: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3<br>
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
; GFX7: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
; GFX7: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec<br>
- ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
- ; GFX7: FLAT_STORE_DWORD [[REG_SEQUENCE1]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
+ ; GFX7: %14:vgpr_32, dead %16:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %14, %subreg.sub1<br>
+ ; GFX7: BUFFER_STORE_DWORD_ADDR64 [[COPY1]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)<br>
+ ; GFX7-FLAT-LABEL: name: store_global_s32_gep_2047<br>
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2<br>
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
+ ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec<br>
+ ; GFX7-FLAT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1<br>
+ ; GFX7-FLAT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0<br>
+ ; GFX7-FLAT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0<br>
+ ; GFX7-FLAT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1<br>
+ ; GFX7-FLAT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1<br>
+ ; GFX7-FLAT: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec<br>
+ ; GFX7-FLAT: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec<br>
+ ; GFX7-FLAT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %9, %subreg.sub1<br>
+ ; GFX7-FLAT: FLAT_STORE_DWORD [[REG_SEQUENCE1]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)<br>
; GFX8-LABEL: name: store_global_s32_gep_2047<br>
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2<br>
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll<br>
index b1e389053da2..4945f7a338b6 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll<br>
@@ -1,6 +1,6 @@<br>
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s<br>
<br>
; FIXME: Merge with other test. DS offset folding doesn't work due to<br>
; register bank copies, and no return optimization is missing.<br>
@@ -19,30 +19,30 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1<br>
define amdgpu_kernel void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_dec_ret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v1, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s2<br>
; CI-NEXT: ds_dec_rtn_u32 v2, v1, v0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
+; CI-NEXT: v_mov_b32_e32 v0, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dword v[0:1], v2<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_dec_ret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v1, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s2<br>
; VI-NEXT: ds_dec_rtn_u32 v2, v1, v0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
+; VI-NEXT: v_mov_b32_e32 v0, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dword v[0:1], v2<br>
; VI-NEXT: s_endpgm<br>
@@ -67,32 +67,32 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 ad<br>
define amdgpu_kernel void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_dec_ret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 16<br>
-; CI-NEXT: v_mov_b32_e32 v1, s0<br>
+; CI-NEXT: s_add_u32 s2, s2, 16<br>
+; CI-NEXT: v_mov_b32_e32 v1, s2<br>
; CI-NEXT: ds_dec_rtn_u32 v2, v1, v0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
+; CI-NEXT: v_mov_b32_e32 v0, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dword v[0:1], v2<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_dec_ret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 16<br>
-; VI-NEXT: v_mov_b32_e32 v1, s0<br>
+; VI-NEXT: s_add_u32 s2, s2, 16<br>
+; VI-NEXT: v_mov_b32_e32 v1, s2<br>
; VI-NEXT: ds_dec_rtn_u32 v2, v1, v0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
+; VI-NEXT: v_mov_b32_e32 v0, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dword v[0:1], v2<br>
; VI-NEXT: s_endpgm<br>
@@ -117,9 +117,26 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out,<br>
}<br>
<br>
define amdgpu_kernel void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) nounwind {<br>
+; GCN-LABEL: lds_atomic_dec_noret_i32:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dword s0, s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, 42<br>
+; GCN-NEXT: s_mov_b32 m0, -1<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s0<br>
+; GCN-NEXT: ds_dec_rtn_u32 v0, v1, v0<br>
+; GCN-NEXT: s_endpgm<br>
+; GFX9-LABEL: lds_atomic_dec_noret_i32:<br>
+; GFX9: ; %bb.0:<br>
+; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; GFX9-NEXT: v_mov_b32_e32 v1, 42<br>
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
+; GFX9-NEXT: ds_dec_rtn_u32 v0, v0, v1<br>
+; GFX9-NEXT: s_endpgm<br>
; CI-LABEL: lds_atomic_dec_noret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -129,21 +146,13 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) noun<br>
;<br>
; VI-LABEL: lds_atomic_dec_noret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: v_mov_b32_e32 v1, s0<br>
; VI-NEXT: ds_dec_rtn_u32 v0, v1, v0<br>
; VI-NEXT: s_endpgm<br>
-; GFX9-LABEL: lds_atomic_dec_noret_i32:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: ds_dec_rtn_u32 v0, v0, v1<br>
-; GFX9-NEXT: s_endpgm<br>
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)<br>
ret void<br>
}<br>
@@ -151,7 +160,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) noun<br>
define amdgpu_kernel void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_dec_noret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -162,7 +171,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %pt<br>
;<br>
; VI-LABEL: lds_atomic_dec_noret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -187,7 +196,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %pt<br>
define amdgpu_kernel void @global_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_dec_ret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -201,7 +210,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32<br>
;<br>
; VI-LABEL: global_atomic_dec_ret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -233,7 +242,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32<br>
define amdgpu_kernel void @global_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_dec_ret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: s_add_u32 s2, s2, 16<br>
@@ -249,7 +258,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i32_offset(i32 addrspace(1)* %o<br>
;<br>
; VI-LABEL: global_atomic_dec_ret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: s_add_u32 s2, s2, 16<br>
@@ -286,7 +295,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i32_offset(i32 addrspace(1)* %o<br>
define amdgpu_kernel void @global_atomic_dec_noret_i32(i32 addrspace(1)* %ptr) nounwind {<br>
; CI-LABEL: global_atomic_dec_noret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: v_mov_b32_e32 v0, s0<br>
@@ -296,7 +305,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i32(i32 addrspace(1)* %ptr) n<br>
;<br>
; VI-LABEL: global_atomic_dec_noret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: v_mov_b32_e32 v0, s0<br>
@@ -319,7 +328,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i32(i32 addrspace(1)* %ptr) n<br>
define amdgpu_kernel void @global_atomic_dec_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind {<br>
; CI-LABEL: global_atomic_dec_noret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: s_add_u32 s0, s0, 16<br>
@@ -331,7 +340,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i32_offset(i32 addrspace(1)*<br>
;<br>
; VI-LABEL: global_atomic_dec_noret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: s_add_u32 s0, s0, 16<br>
@@ -362,7 +371,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -387,7 +396,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -445,7 +454,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspa<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -465,7 +474,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspa<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -508,7 +517,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspa<br>
define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32* %out, i32* %ptr) #0 {<br>
; CI-LABEL: flat_atomic_dec_ret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -522,7 +531,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32* %out, i32* %ptr) #0 {<br>
;<br>
; VI-LABEL: flat_atomic_dec_ret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -554,7 +563,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32* %out, i32* %ptr) #0 {<br>
define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32* %out, i32* %ptr) #0 {<br>
; CI-LABEL: flat_atomic_dec_ret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: s_add_u32 s2, s2, 16<br>
@@ -570,7 +579,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32* %out, i32* %ptr)<br>
;<br>
; VI-LABEL: flat_atomic_dec_ret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: s_add_u32 s2, s2, 16<br>
@@ -607,7 +616,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32* %out, i32* %ptr)<br>
define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32* %ptr) nounwind {<br>
; CI-LABEL: flat_atomic_dec_noret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: v_mov_b32_e32 v0, s0<br>
@@ -617,7 +626,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32* %ptr) nounwind {<br>
;<br>
; VI-LABEL: flat_atomic_dec_noret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: v_mov_b32_e32 v0, s0<br>
@@ -640,7 +649,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32* %ptr) nounwind {<br>
define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32* %ptr) nounwind {<br>
; CI-LABEL: flat_atomic_dec_noret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: s_add_u32 s0, s0, 16<br>
@@ -652,7 +661,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32* %ptr) nounwind<br>
;<br>
; VI-LABEL: flat_atomic_dec_noret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: s_add_u32 s0, s0, 16<br>
@@ -683,7 +692,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32*<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -708,7 +717,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32*<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -766,7 +775,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -786,7 +795,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -829,7 +838,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0<br>
define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {<br>
; CI-LABEL: flat_atomic_dec_ret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -844,7 +853,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {<br>
;<br>
; VI-LABEL: flat_atomic_dec_ret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -878,7 +887,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {<br>
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr) #0 {<br>
; CI-LABEL: flat_atomic_dec_ret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -895,7 +904,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr)<br>
;<br>
; VI-LABEL: flat_atomic_dec_ret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -934,7 +943,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr)<br>
define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {<br>
; CI-LABEL: flat_atomic_dec_noret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -945,7 +954,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {<br>
;<br>
; VI-LABEL: flat_atomic_dec_noret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -970,7 +979,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {<br>
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind {<br>
; CI-LABEL: flat_atomic_dec_noret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -983,7 +992,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind<br>
;<br>
; VI-LABEL: flat_atomic_dec_noret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1016,7 +1025,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64*<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1042,7 +1051,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64*<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1102,7 +1111,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1123,7 +1132,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1171,7 +1180,7 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32<br>
; CI-LABEL: atomic_dec_shl_base_lds_0:<br>
; CI: ; %bb.0:<br>
; CI-NEXT: v_mul_lo_u32 v5, 4, v0<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v6, 9<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: v_add_i32_e32 v5, vcc, 0, v5<br>
@@ -1190,7 +1199,7 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32<br>
; VI-LABEL: atomic_dec_shl_base_lds_0:<br>
; VI: ; %bb.0:<br>
; VI-NEXT: v_mul_lo_u32 v5, 4, v0<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v6, 9<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: v_add_u32_e32 v5, vcc, 0, v5<br>
@@ -1234,32 +1243,32 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32<br>
define amdgpu_kernel void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_dec_ret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v2, s0<br>
-; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
; CI-NEXT: v_mov_b32_e32 v2, s2<br>
-; CI-NEXT: v_mov_b32_e32 v3, s3<br>
+; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
+; CI-NEXT: v_mov_b32_e32 v3, s1<br>
+; CI-NEXT: v_mov_b32_e32 v2, s0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_dec_ret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v2, s0<br>
-; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
; VI-NEXT: v_mov_b32_e32 v2, s2<br>
-; VI-NEXT: v_mov_b32_e32 v3, s3<br>
+; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
+; VI-NEXT: v_mov_b32_e32 v3, s1<br>
+; VI-NEXT: v_mov_b32_e32 v2, s0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; VI-NEXT: s_endpgm<br>
@@ -1285,34 +1294,34 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 ad<br>
define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_dec_ret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 32<br>
-; CI-NEXT: v_mov_b32_e32 v2, s0<br>
-; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
+; CI-NEXT: s_add_u32 s2, s2, 32<br>
; CI-NEXT: v_mov_b32_e32 v2, s2<br>
-; CI-NEXT: v_mov_b32_e32 v3, s3<br>
+; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
+; CI-NEXT: v_mov_b32_e32 v3, s1<br>
+; CI-NEXT: v_mov_b32_e32 v2, s0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_dec_ret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 32<br>
-; VI-NEXT: v_mov_b32_e32 v2, s0<br>
-; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
+; VI-NEXT: s_add_u32 s2, s2, 32<br>
; VI-NEXT: v_mov_b32_e32 v2, s2<br>
-; VI-NEXT: v_mov_b32_e32 v3, s3<br>
+; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]<br>
+; VI-NEXT: v_mov_b32_e32 v3, s1<br>
+; VI-NEXT: v_mov_b32_e32 v2, s0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; VI-NEXT: s_endpgm<br>
@@ -1340,7 +1349,7 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out,<br>
define amdgpu_kernel void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_dec_noret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
@@ -1351,7 +1360,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) noun<br>
;<br>
; VI-LABEL: lds_atomic_dec_noret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
@@ -1375,7 +1384,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) noun<br>
define amdgpu_kernel void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_dec_noret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
@@ -1387,7 +1396,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %pt<br>
;<br>
; VI-LABEL: lds_atomic_dec_noret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
@@ -1414,7 +1423,7 @@ define amdgpu_kernel void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %pt<br>
define amdgpu_kernel void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_dec_ret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1429,7 +1438,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64<br>
;<br>
; VI-LABEL: global_atomic_dec_ret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1463,7 +1472,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64<br>
define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_dec_ret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1480,7 +1489,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %o<br>
;<br>
; VI-LABEL: global_atomic_dec_ret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1519,7 +1528,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %o<br>
define amdgpu_kernel void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) nounwind {<br>
; CI-LABEL: global_atomic_dec_noret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1530,7 +1539,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) n<br>
;<br>
; VI-LABEL: global_atomic_dec_noret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1555,7 +1564,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) n<br>
define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {<br>
; CI-LABEL: global_atomic_dec_noret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1568,7 +1577,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(i64 addrspace(1)*<br>
;<br>
; VI-LABEL: global_atomic_dec_noret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -1601,7 +1610,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1627,7 +1636,7 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1687,7 +1696,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspa<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1708,7 +1717,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspa<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1756,7 +1765,7 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out,<br>
; CI-LABEL: atomic_dec_shl_base_lds_0_i64:<br>
; CI: ; %bb.0:<br>
; CI-NEXT: v_mul_lo_u32 v7, 8, v0<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_add_i32_e32 v6, vcc, 2, v0<br>
; CI-NEXT: v_mov_b32_e32 v0, 9<br>
; CI-NEXT: v_add_i32_e32 v7, vcc, 0, v7<br>
@@ -1776,7 +1785,7 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out,<br>
; VI-LABEL: atomic_dec_shl_base_lds_0_i64:<br>
; VI: ; %bb.0:<br>
; VI-NEXT: v_mul_lo_u32 v7, 8, v0<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0<br>
; VI-NEXT: v_mov_b32_e32 v0, 9<br>
; VI-NEXT: v_add_u32_e32 v7, vcc, 0, v7<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll<br>
index 454034b0a428..07f45eaf2b8a 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll<br>
@@ -1,7 +1,7 @@<br>
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s<br>
<br>
; FIXME: Merge with other test. DS offset folding doesn't work due to<br>
; register bank copies, and no return optimization is missing.<br>
@@ -20,44 +20,44 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1<br>
define amdgpu_kernel void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_inc_ret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v1, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s2<br>
; CI-NEXT: ds_inc_rtn_u32 v2, v1, v0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
+; CI-NEXT: v_mov_b32_e32 v0, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dword v[0:1], v2<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_inc_ret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v1, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s2<br>
; VI-NEXT: ds_inc_rtn_u32 v2, v1, v0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
+; VI-NEXT: v_mov_b32_e32 v0, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dword v[0:1], v2<br>
; VI-NEXT: s_endpgm<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_ret_i32:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: ds_inc_rtn_u32 v2, v0, v1<br>
; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s3<br>
+; GFX9-NEXT: ds_inc_rtn_u32 v2, v0, v1<br>
+; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
+; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: global_store_dword v[0:1], v2, off<br>
; GFX9-NEXT: s_endpgm<br>
@@ -71,47 +71,47 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 ad<br>
define amdgpu_kernel void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_inc_ret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 16<br>
-; CI-NEXT: v_mov_b32_e32 v1, s0<br>
+; CI-NEXT: s_add_u32 s2, s2, 16<br>
+; CI-NEXT: v_mov_b32_e32 v1, s2<br>
; CI-NEXT: ds_inc_rtn_u32 v2, v1, v0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
+; CI-NEXT: v_mov_b32_e32 v0, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dword v[0:1], v2<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_inc_ret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 16<br>
-; VI-NEXT: v_mov_b32_e32 v1, s0<br>
+; VI-NEXT: s_add_u32 s2, s2, 16<br>
+; VI-NEXT: v_mov_b32_e32 v1, s2<br>
; VI-NEXT: ds_inc_rtn_u32 v2, v1, v0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
+; VI-NEXT: v_mov_b32_e32 v0, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dword v[0:1], v2<br>
; VI-NEXT: s_endpgm<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_ret_i32_offset:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s0, s0, 16<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: ds_inc_rtn_u32 v2, v0, v1<br>
+; GFX9-NEXT: s_add_u32 s2, s2, 16<br>
; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s3<br>
+; GFX9-NEXT: ds_inc_rtn_u32 v2, v0, v1<br>
+; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
+; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: global_store_dword v[0:1], v2, off<br>
; GFX9-NEXT: s_endpgm<br>
@@ -124,7 +124,7 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out,<br>
define amdgpu_kernel void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_inc_noret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -134,7 +134,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) noun<br>
;<br>
; VI-LABEL: lds_atomic_inc_noret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -144,7 +144,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) noun<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_noret_i32:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
@@ -157,7 +157,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) noun<br>
define amdgpu_kernel void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_inc_noret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -168,7 +168,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %pt<br>
;<br>
; VI-LABEL: lds_atomic_inc_noret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -179,7 +179,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %pt<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_noret_i32_offset:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: s_add_u32 s0, s0, 16<br>
@@ -194,7 +194,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %pt<br>
define amdgpu_kernel void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_inc_ret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -208,7 +208,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32<br>
;<br>
; VI-LABEL: global_atomic_inc_ret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -222,7 +222,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32<br>
;<br>
; GFX9-LABEL: global_atomic_inc_ret_i32:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
@@ -241,7 +241,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32<br>
define amdgpu_kernel void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_inc_ret_i32_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: s_add_u32 s2, s2, 16<br>
@@ -257,7 +257,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %o<br>
;<br>
; VI-LABEL: global_atomic_inc_ret_i32_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: s_add_u32 s2, s2, 16<br>
@@ -273,7 +273,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %o<br>
;<br>
; GFX9-LABEL: global_atomic_inc_ret_i32_offset:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: s_add_u32 s2, s2, 16<br>
@@ -293,75 +293,31 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %o<br>
}<br>
<br>
define amdgpu_kernel void @global_atomic_inc_noret_i32(i32 addrspace(1)* %ptr) nounwind {<br>
-; CI-LABEL: global_atomic_inc_noret_i32:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: global_atomic_inc_noret_i32:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: global_atomic_inc_noret_i32:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: global_atomic_inc_noret_i32:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
+; GCN-NEXT: s_endpgm<br>
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42, i32 0, i32 0, i1 false)<br>
ret void<br>
}<br>
<br>
define amdgpu_kernel void @global_atomic_inc_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind {<br>
-; CI-LABEL: global_atomic_inc_noret_i32_offset:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 16<br>
-; CI-NEXT: s_addc_u32 s1, s1, 0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: global_atomic_inc_noret_i32_offset:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 16<br>
-; VI-NEXT: s_addc_u32 s1, s1, 0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: global_atomic_inc_noret_i32_offset:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s0, s0, 16<br>
-; GFX9-NEXT: s_addc_u32 s1, s1, 0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: global_atomic_inc_noret_i32_offset:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: s_add_u32 s0, s0, 16<br>
+; GCN-NEXT: s_addc_u32 s1, s1, 0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
+; GCN-NEXT: s_endpgm<br>
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4<br>
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)<br>
ret void<br>
@@ -373,7 +329,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -398,7 +354,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -421,7 +377,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace<br>
; GFX9-LABEL: global_atomic_inc_ret_i32_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1<br>
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0<br>
@@ -456,7 +412,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspa<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -476,7 +432,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspa<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -494,7 +450,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspa<br>
; GFX9-LABEL: global_atomic_inc_noret_i32_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1<br>
@@ -522,7 +478,7 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out,<br>
; CI-LABEL: atomic_inc_shl_base_lds_0_i32:<br>
; CI: ; %bb.0:<br>
; CI-NEXT: v_mul_lo_u32 v5, 4, v0<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v6, 9<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: v_add_i32_e32 v5, vcc, 0, v5<br>
@@ -541,7 +497,7 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out,<br>
; VI-LABEL: atomic_inc_shl_base_lds_0_i32:<br>
; VI: ; %bb.0:<br>
; VI-NEXT: v_mul_lo_u32 v5, 4, v0<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v6, 9<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: v_add_u32_e32 v5, vcc, 0, v5<br>
@@ -560,7 +516,7 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out,<br>
; GFX9-LABEL: atomic_inc_shl_base_lds_0_i32:<br>
; GFX9: ; %bb.0:<br>
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v0<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_add_u32_e32 v3, 2, v0<br>
; GFX9-NEXT: v_mov_b32_e32 v2, 9<br>
; GFX9-NEXT: v_add_u32_e32 v0, 0, v1<br>
@@ -586,47 +542,47 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out,<br>
define amdgpu_kernel void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_inc_ret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v2, s0<br>
-; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
; CI-NEXT: v_mov_b32_e32 v2, s2<br>
-; CI-NEXT: v_mov_b32_e32 v3, s3<br>
+; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; CI-NEXT: v_mov_b32_e32 v3, s1<br>
+; CI-NEXT: v_mov_b32_e32 v2, s0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_inc_ret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v2, s0<br>
-; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
; VI-NEXT: v_mov_b32_e32 v2, s2<br>
-; VI-NEXT: v_mov_b32_e32 v3, s3<br>
+; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; VI-NEXT: v_mov_b32_e32 v3, s1<br>
+; VI-NEXT: v_mov_b32_e32 v2, s0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; VI-NEXT: s_endpgm<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_ret_i64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; GFX9-NEXT: v_mov_b32_e32 v0, 42<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, s0<br>
-; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
; GFX9-NEXT: v_mov_b32_e32 v2, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, s3<br>
+; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; GFX9-NEXT: v_mov_b32_e32 v3, s1<br>
+; GFX9-NEXT: v_mov_b32_e32 v2, s0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off<br>
; GFX9-NEXT: s_endpgm<br>
@@ -638,50 +594,50 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 ad<br>
define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: lds_atomic_inc_ret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xb<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s2, s[4:5], 0x2<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 32<br>
-; CI-NEXT: v_mov_b32_e32 v2, s0<br>
-; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; CI-NEXT: s_add_u32 s2, s2, 32<br>
; CI-NEXT: v_mov_b32_e32 v2, s2<br>
-; CI-NEXT: v_mov_b32_e32 v3, s3<br>
+; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; CI-NEXT: v_mov_b32_e32 v3, s1<br>
+; CI-NEXT: v_mov_b32_e32 v2, s0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; CI-NEXT: s_endpgm<br>
;<br>
; VI-LABEL: lds_atomic_inc_ret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 32<br>
-; VI-NEXT: v_mov_b32_e32 v2, s0<br>
-; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; VI-NEXT: s_add_u32 s2, s2, 32<br>
; VI-NEXT: v_mov_b32_e32 v2, s2<br>
-; VI-NEXT: v_mov_b32_e32 v3, s3<br>
+; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; VI-NEXT: v_mov_b32_e32 v3, s1<br>
+; VI-NEXT: v_mov_b32_e32 v2, s0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
; VI-NEXT: s_endpgm<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_ret_i64_offset:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8<br>
; GFX9-NEXT: v_mov_b32_e32 v0, 42<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s0, s0, 32<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, s0<br>
-; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; GFX9-NEXT: s_add_u32 s2, s2, 32<br>
; GFX9-NEXT: v_mov_b32_e32 v2, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, s3<br>
+; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]<br>
+; GFX9-NEXT: v_mov_b32_e32 v3, s1<br>
+; GFX9-NEXT: v_mov_b32_e32 v2, s0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off<br>
; GFX9-NEXT: s_endpgm<br>
@@ -694,7 +650,7 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out,<br>
define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_inc_noret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
@@ -705,7 +661,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) noun<br>
;<br>
; VI-LABEL: lds_atomic_inc_noret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
@@ -716,7 +672,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) noun<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_noret_i64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v0, 42<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -730,7 +686,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) noun<br>
define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {<br>
; CI-LABEL: lds_atomic_inc_noret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0x9<br>
+; CI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v0, 42<br>
; CI-NEXT: v_mov_b32_e32 v1, 0<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
@@ -742,7 +698,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %pt<br>
;<br>
; VI-LABEL: lds_atomic_inc_noret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; VI-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v0, 42<br>
; VI-NEXT: v_mov_b32_e32 v1, 0<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
@@ -754,7 +710,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %pt<br>
;<br>
; GFX9-LABEL: lds_atomic_inc_noret_i64_offset:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v0, 42<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -770,7 +726,7 @@ define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %pt<br>
define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_inc_ret_i64:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -785,7 +741,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64<br>
;<br>
; VI-LABEL: global_atomic_inc_ret_i64:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -800,7 +756,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64<br>
;<br>
; GFX9-LABEL: global_atomic_inc_ret_i64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -820,7 +776,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64<br>
define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {<br>
; CI-LABEL: global_atomic_inc_ret_i64_offset:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: v_mov_b32_e32 v3, 0<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -837,7 +793,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %o<br>
;<br>
; VI-LABEL: global_atomic_inc_ret_i64_offset:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: v_mov_b32_e32 v3, 0<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -854,7 +810,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %o<br>
;<br>
; GFX9-LABEL: global_atomic_inc_ret_i64_offset:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
@@ -875,81 +831,33 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %o<br>
}<br>
<br>
define amdgpu_kernel void @global_atomic_inc_noret_i64(i64 addrspace(1)* %ptr) nounwind {<br>
-; CI-LABEL: global_atomic_inc_noret_i64:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: v_mov_b32_e32 v3, 0<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: global_atomic_inc_noret_i64:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: v_mov_b32_e32 v3, 0<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: global_atomic_inc_noret_i64:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: global_atomic_inc_noret_i64:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: v_mov_b32_e32 v3, 0<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
+; GCN-NEXT: s_endpgm<br>
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)<br>
ret void<br>
}<br>
<br>
define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {<br>
-; CI-LABEL: global_atomic_inc_noret_i64_offset:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: v_mov_b32_e32 v3, 0<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 32<br>
-; CI-NEXT: s_addc_u32 s1, s1, 0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: global_atomic_inc_noret_i64_offset:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: v_mov_b32_e32 v3, 0<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 32<br>
-; VI-NEXT: s_addc_u32 s1, s1, 0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: global_atomic_inc_noret_i64_offset:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s0, s0, 32<br>
-; GFX9-NEXT: s_addc_u32 s1, s1, 0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: global_atomic_inc_noret_i64_offset:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: v_mov_b32_e32 v3, 0<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: s_add_u32 s0, s0, 32<br>
+; GCN-NEXT: s_addc_u32 s1, s1, 0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
+; GCN-NEXT: s_endpgm<br>
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4<br>
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)<br>
ret void<br>
@@ -961,7 +869,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -987,7 +895,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1010,7 +918,7 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace<br>
;<br>
; GFX9-LABEL: global_atomic_inc_ret_i64_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1<br>
@@ -1047,7 +955,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspa<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1068,7 +976,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspa<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1086,7 +994,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspa<br>
;<br>
; GFX9-LABEL: global_atomic_inc_noret_i64_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1<br>
@@ -1111,100 +1019,40 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspa<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32* %out, i32* %ptr) #0 {<br>
-; CI-LABEL: flat_atomic_inc_ret_i32:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
-; CI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; CI-NEXT: flat_store_dword v[0:1], v2<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_ret_i32:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
-; VI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; VI-NEXT: flat_store_dword v[0:1], v2<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_ret_i32:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s3<br>
-; GFX9-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; GFX9-NEXT: flat_store_dword v[0:1], v2<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_ret_i32:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s2<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s3<br>
+; GCN-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
+; GCN-NEXT: flat_store_dword v[0:1], v2<br>
+; GCN-NEXT: s_endpgm<br>
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)<br>
store i32 %result, i32* %out<br>
ret void<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32* %out, i32* %ptr) #0 {<br>
-; CI-LABEL: flat_atomic_inc_ret_i32_offset:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s2, s2, 16<br>
-; CI-NEXT: s_addc_u32 s3, s3, 0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
-; CI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; CI-NEXT: flat_store_dword v[0:1], v2<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_ret_i32_offset:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s2, s2, 16<br>
-; VI-NEXT: s_addc_u32 s3, s3, 0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
-; VI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; VI-NEXT: flat_store_dword v[0:1], v2<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_ret_i32_offset:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s2, s2, 16<br>
-; GFX9-NEXT: s_addc_u32 s3, s3, 0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s3<br>
-; GFX9-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; GFX9-NEXT: flat_store_dword v[0:1], v2<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_ret_i32_offset:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: s_add_u32 s2, s2, 16<br>
+; GCN-NEXT: s_addc_u32 s3, s3, 0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s2<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s3<br>
+; GCN-NEXT: flat_atomic_inc v2, v[0:1], v2 glc<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
+; GCN-NEXT: flat_store_dword v[0:1], v2<br>
+; GCN-NEXT: s_endpgm<br>
%gep = getelementptr i32, i32* %ptr, i32 4<br>
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)<br>
store i32 %result, i32* %out<br>
@@ -1212,75 +1060,31 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32* %out, i32* %ptr)<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32* %ptr) nounwind {<br>
-; CI-LABEL: flat_atomic_inc_noret_i32:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_noret_i32:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_noret_i32:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_noret_i32:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
+; GCN-NEXT: s_endpgm<br>
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)<br>
ret void<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32* %ptr) nounwind {<br>
-; CI-LABEL: flat_atomic_inc_noret_i32_offset:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 16<br>
-; CI-NEXT: s_addc_u32 s1, s1, 0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_noret_i32_offset:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 16<br>
-; VI-NEXT: s_addc_u32 s1, s1, 0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_noret_i32_offset:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s0, s0, 16<br>
-; GFX9-NEXT: s_addc_u32 s1, s1, 0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_noret_i32_offset:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: s_add_u32 s0, s0, 16<br>
+; GCN-NEXT: s_addc_u32 s1, s1, 0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc v0, v[0:1], v2 glc<br>
+; GCN-NEXT: s_endpgm<br>
%gep = getelementptr i32, i32* %ptr, i32 4<br>
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)<br>
ret void<br>
@@ -1292,7 +1096,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32*<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1317,7 +1121,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32*<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1340,7 +1144,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32*<br>
; GFX9-LABEL: flat_atomic_inc_ret_i32_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1<br>
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0<br>
@@ -1375,7 +1179,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1395,7 +1199,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 4, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 4, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1413,7 +1217,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0<br>
; GFX9-LABEL: flat_atomic_inc_noret_i32_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1<br>
@@ -1441,7 +1245,7 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out,<br>
; CI-LABEL: atomic_inc_shl_base_lds_0_i64:<br>
; CI: ; %bb.0:<br>
; CI-NEXT: v_mul_lo_u32 v7, 8, v0<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_add_i32_e32 v6, vcc, 2, v0<br>
; CI-NEXT: v_mov_b32_e32 v0, 9<br>
; CI-NEXT: v_add_i32_e32 v7, vcc, 0, v7<br>
@@ -1461,7 +1265,7 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out,<br>
; VI-LABEL: atomic_inc_shl_base_lds_0_i64:<br>
; VI: ; %bb.0:<br>
; VI-NEXT: v_mul_lo_u32 v7, 8, v0<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0<br>
; VI-NEXT: v_mov_b32_e32 v0, 9<br>
; VI-NEXT: v_add_u32_e32 v7, vcc, 0, v7<br>
@@ -1481,7 +1285,7 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out,<br>
; GFX9-LABEL: atomic_inc_shl_base_lds_0_i64:<br>
; GFX9: ; %bb.0:<br>
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v0<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_mov_b32_e32 v1, 9<br>
; GFX9-NEXT: v_add_u32_e32 v4, 2, v0<br>
; GFX9-NEXT: v_add_u32_e32 v0, 0, v3<br>
@@ -1506,106 +1310,42 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out,<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 {<br>
-; CI-LABEL: flat_atomic_inc_ret_i64:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: v_mov_b32_e32 v3, 0<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
-; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; CI-NEXT: v_mov_b32_e32 v3, s1<br>
-; CI-NEXT: v_mov_b32_e32 v2, s0<br>
-; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_ret_i64:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: v_mov_b32_e32 v3, 0<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
-; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; VI-NEXT: v_mov_b32_e32 v3, s1<br>
-; VI-NEXT: v_mov_b32_e32 v2, s0<br>
-; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_ret_i64:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s3<br>
-; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, s1<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, s0<br>
-; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_ret_i64:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: v_mov_b32_e32 v3, 0<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s2<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s3<br>
+; GCN-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
+; GCN-NEXT: v_mov_b32_e32 v3, s1<br>
+; GCN-NEXT: v_mov_b32_e32 v2, s0<br>
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
+; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
+; GCN-NEXT: s_endpgm<br>
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)<br>
store i64 %result, i64* %out<br>
ret void<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 {<br>
-; CI-LABEL: flat_atomic_inc_ret_i64_offset:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: v_mov_b32_e32 v3, 0<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s2, s2, 32<br>
-; CI-NEXT: s_addc_u32 s3, s3, 0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s2<br>
-; CI-NEXT: v_mov_b32_e32 v1, s3<br>
-; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; CI-NEXT: v_mov_b32_e32 v3, s1<br>
-; CI-NEXT: v_mov_b32_e32 v2, s0<br>
-; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_ret_i64_offset:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: v_mov_b32_e32 v3, 0<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s2, s2, 32<br>
-; VI-NEXT: s_addc_u32 s3, s3, 0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s2<br>
-; VI-NEXT: v_mov_b32_e32 v1, s3<br>
-; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; VI-NEXT: v_mov_b32_e32 v3, s1<br>
-; VI-NEXT: v_mov_b32_e32 v2, s0<br>
-; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_ret_i64_offset:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s2, s2, 32<br>
-; GFX9-NEXT: s_addc_u32 s3, s3, 0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s2<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s3<br>
-; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, s1<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, s0<br>
-; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_ret_i64_offset:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: v_mov_b32_e32 v3, 0<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: s_add_u32 s2, s2, 32<br>
+; GCN-NEXT: s_addc_u32 s3, s3, 0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s2<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s3<br>
+; GCN-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
+; GCN-NEXT: v_mov_b32_e32 v3, s1<br>
+; GCN-NEXT: v_mov_b32_e32 v2, s0<br>
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
+; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]<br>
+; GCN-NEXT: s_endpgm<br>
%gep = getelementptr i64, i64* %ptr, i32 4<br>
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)<br>
store i64 %result, i64* %out<br>
@@ -1613,81 +1353,33 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr)<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind {<br>
-; CI-LABEL: flat_atomic_inc_noret_i64:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: v_mov_b32_e32 v3, 0<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_noret_i64:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: v_mov_b32_e32 v3, 0<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_noret_i64:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_noret_i64:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: v_mov_b32_e32 v3, 0<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
+; GCN-NEXT: s_endpgm<br>
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)<br>
ret void<br>
}<br>
<br>
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind {<br>
-; CI-LABEL: flat_atomic_inc_noret_i64_offset:<br>
-; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
-; CI-NEXT: v_mov_b32_e32 v2, 42<br>
-; CI-NEXT: v_mov_b32_e32 v3, 0<br>
-; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: s_add_u32 s0, s0, 32<br>
-; CI-NEXT: s_addc_u32 s1, s1, 0<br>
-; CI-NEXT: v_mov_b32_e32 v0, s0<br>
-; CI-NEXT: v_mov_b32_e32 v1, s1<br>
-; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; CI-NEXT: s_endpgm<br>
-;<br>
-; VI-LABEL: flat_atomic_inc_noret_i64_offset:<br>
-; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; VI-NEXT: v_mov_b32_e32 v2, 42<br>
-; VI-NEXT: v_mov_b32_e32 v3, 0<br>
-; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: s_add_u32 s0, s0, 32<br>
-; VI-NEXT: s_addc_u32 s1, s1, 0<br>
-; VI-NEXT: v_mov_b32_e32 v0, s0<br>
-; VI-NEXT: v_mov_b32_e32 v1, s1<br>
-; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; VI-NEXT: s_endpgm<br>
-;<br>
-; GFX9-LABEL: flat_atomic_inc_noret_i64_offset:<br>
-; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, 42<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, 0<br>
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: s_add_u32 s0, s0, 32<br>
-; GFX9-NEXT: s_addc_u32 s1, s1, 0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
-; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
-; GFX9-NEXT: s_endpgm<br>
+; GCN-LABEL: flat_atomic_inc_noret_i64_offset:<br>
+; GCN: ; %bb.0:<br>
+; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
+; GCN-NEXT: v_mov_b32_e32 v2, 42<br>
+; GCN-NEXT: v_mov_b32_e32 v3, 0<br>
+; GCN-NEXT: s_waitcnt lgkmcnt(0)<br>
+; GCN-NEXT: s_add_u32 s0, s0, 32<br>
+; GCN-NEXT: s_addc_u32 s1, s1, 0<br>
+; GCN-NEXT: v_mov_b32_e32 v0, s0<br>
+; GCN-NEXT: v_mov_b32_e32 v1, s1<br>
+; GCN-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc<br>
+; GCN-NEXT: s_endpgm<br>
%gep = getelementptr i64, i64* %ptr, i32 4<br>
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)<br>
ret void<br>
@@ -1699,7 +1391,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64*<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1725,7 +1417,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64*<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v4, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1748,7 +1440,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64*<br>
;<br>
; GFX9-LABEL: flat_atomic_inc_ret_i64_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1<br>
@@ -1785,7 +1477,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0<br>
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; CI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; CI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9<br>
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; CI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; CI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1<br>
@@ -1806,7 +1498,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0<br>
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; VI-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; VI-NEXT: v_mul_lo_u32 v1, 8, v1<br>
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; VI-NEXT: v_mul_hi_u32 v3, 8, v0<br>
; VI-NEXT: v_mul_lo_u32 v0, 8, v0<br>
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1<br>
@@ -1824,7 +1516,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0<br>
;<br>
; GFX9-LABEL: flat_atomic_inc_noret_i64_offset_addr64:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24<br>
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0<br>
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0<br>
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1<br>
@@ -1851,18 +1543,18 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0<br>
define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 {<br>
; CI-LABEL: nocse_lds_atomic_inc_ret_i32:<br>
; CI: ; %bb.0:<br>
-; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9<br>
-; CI-NEXT: s_load_dword s0, s[0:1], 0xd<br>
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; CI-NEXT: s_load_dword s4, s[4:5], 0x4<br>
; CI-NEXT: v_mov_b32_e32 v2, 42<br>
; CI-NEXT: s_mov_b32 m0, -1<br>
; CI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; CI-NEXT: v_mov_b32_e32 v0, s6<br>
-; CI-NEXT: v_mov_b32_e32 v3, s0<br>
+; CI-NEXT: v_mov_b32_e32 v0, s2<br>
+; CI-NEXT: v_mov_b32_e32 v3, s4<br>
; CI-NEXT: ds_inc_rtn_u32 v4, v3, v2<br>
; CI-NEXT: ds_inc_rtn_u32 v5, v3, v2<br>
-; CI-NEXT: v_mov_b32_e32 v2, s4<br>
-; CI-NEXT: v_mov_b32_e32 v3, s5<br>
-; CI-NEXT: v_mov_b32_e32 v1, s7<br>
+; CI-NEXT: v_mov_b32_e32 v3, s1<br>
+; CI-NEXT: v_mov_b32_e32 v2, s0<br>
+; CI-NEXT: v_mov_b32_e32 v1, s3<br>
; CI-NEXT: s_waitcnt lgkmcnt(1)<br>
; CI-NEXT: flat_store_dword v[2:3], v4<br>
; CI-NEXT: s_waitcnt lgkmcnt(1)<br>
@@ -1871,18 +1563,18 @@ define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0,<br>
;<br>
; VI-LABEL: nocse_lds_atomic_inc_ret_i32:<br>
; VI: ; %bb.0:<br>
-; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24<br>
-; VI-NEXT: s_load_dword s0, s[0:1], 0x34<br>
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; VI-NEXT: s_load_dword s4, s[4:5], 0x10<br>
; VI-NEXT: v_mov_b32_e32 v2, 42<br>
; VI-NEXT: s_mov_b32 m0, -1<br>
; VI-NEXT: s_waitcnt lgkmcnt(0)<br>
-; VI-NEXT: v_mov_b32_e32 v0, s6<br>
-; VI-NEXT: v_mov_b32_e32 v3, s0<br>
+; VI-NEXT: v_mov_b32_e32 v0, s2<br>
+; VI-NEXT: v_mov_b32_e32 v3, s4<br>
; VI-NEXT: ds_inc_rtn_u32 v4, v3, v2<br>
; VI-NEXT: ds_inc_rtn_u32 v5, v3, v2<br>
-; VI-NEXT: v_mov_b32_e32 v2, s4<br>
-; VI-NEXT: v_mov_b32_e32 v3, s5<br>
-; VI-NEXT: v_mov_b32_e32 v1, s7<br>
+; VI-NEXT: v_mov_b32_e32 v3, s1<br>
+; VI-NEXT: v_mov_b32_e32 v2, s0<br>
+; VI-NEXT: v_mov_b32_e32 v1, s3<br>
; VI-NEXT: s_waitcnt lgkmcnt(1)<br>
; VI-NEXT: flat_store_dword v[2:3], v4<br>
; VI-NEXT: s_waitcnt lgkmcnt(1)<br>
@@ -1891,17 +1583,17 @@ define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0,<br>
;<br>
; GFX9-LABEL: nocse_lds_atomic_inc_ret_i32:<br>
; GFX9: ; %bb.0:<br>
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24<br>
-; GFX9-NEXT: s_load_dword s0, s[0:1], 0x34<br>
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0<br>
+; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10<br>
; GFX9-NEXT: v_mov_b32_e32 v0, 42<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
-; GFX9-NEXT: v_mov_b32_e32 v2, s6<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s0<br>
+; GFX9-NEXT: v_mov_b32_e32 v2, s2<br>
+; GFX9-NEXT: v_mov_b32_e32 v1, s4<br>
; GFX9-NEXT: ds_inc_rtn_u32 v4, v1, v0<br>
; GFX9-NEXT: ds_inc_rtn_u32 v5, v1, v0<br>
-; GFX9-NEXT: v_mov_b32_e32 v0, s4<br>
-; GFX9-NEXT: v_mov_b32_e32 v1, s5<br>
-; GFX9-NEXT: v_mov_b32_e32 v3, s7<br>
+; GFX9-NEXT: v_mov_b32_e32 v0, s0<br>
+; GFX9-NEXT: v_mov_b32_e32 v1, s1<br>
+; GFX9-NEXT: v_mov_b32_e32 v3, s3<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(1)<br>
; GFX9-NEXT: global_store_dword v[0:1], v4, off<br>
; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.append.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.append.ll<br>
index 8287a60a069f..1b09c6251912 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.append.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.append.ll<br>
@@ -1,4 +1,4 @@<br>
; XUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,SI,NOTGFX9,CIPLUS-GISEL,GCN-GISEL %S/../llvm.amdgcn.ds.append.ll<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9,CIPLUS-GISEL,GCN-GISEL %S/../llvm.amdgcn.ds.append.ll<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9,CIPLUS-GISEL,GCN-GISEL %S/../llvm.amdgcn.ds.append.ll<br>
+; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -mattr=+flat-for-global -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9,CIPLUS-GISEL,GCN-GISEL %S/../llvm.amdgcn.ds.append.ll<br>
+; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9,CIPLUS-GISEL,GCN-GISEL %S/../llvm.amdgcn.ds.append.ll<br>
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,GFX9,CIPLUS-GISEL,GCN-GISEL %S/../llvm.amdgcn.ds.append.ll<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.consume.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.consume.ll<br>
index c755c37cad46..7aea170ed1ef 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.consume.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.consume.ll<br>
@@ -1,4 +1,4 @@<br>
; XUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,SI,NOTGFX9 %S/../llvm.amdgcn.ds.append.ll<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %S/../llvm.amdgcn.ds.append.ll<br>
-; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %S/../llvm.amdgcn.ds.append.ll<br>
+; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -mattr=+flat-for-global -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %S/../llvm.amdgcn.ds.append.ll<br>
+; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9 %S/../llvm.amdgcn.ds.append.ll<br>
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %S/../llvm.amdgcn.ds.append.ll | FileCheck -check-prefixes=GCN,CIPLUS,GFX9 %S/../llvm.amdgcn.ds.append.ll<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll<br>
index 55929202b1c2..f4ede38b26aa 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll<br>
@@ -1,6 +1,6 @@<br>
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s<br>
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s<br>
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-unknown -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-unknown -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s<br>
<br>
; ALL-LABEL: {{^}}test:<br>
; CO-V2: enable_sgpr_kernarg_segment_ptr = 1<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll<br>
index 946a138bee4f..aed978899565 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll<br>
@@ -1,9 +1,9 @@<br>
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s<br>
-; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s<br>
-; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s<br>
-; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s<br>
-; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s<br>
-; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global,-code-object-v3 -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s<br>
+; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s<br>
<br>
declare i32 @llvm.amdgcn.workitem.id.x() #0<br>
declare i32 @llvm.amdgcn.workitem.id.y() #0<br>
<br>
<br>
<br>
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</blockquote></div>