<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Did you perhaps forget to mark the new .dep file as textual in the module map?<div class=""><br class=""></div><div class="">-- adrian<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Jan 16, 2020, at 12:46 PM, Adrian Prantl <<a href="mailto:aprantl@apple.com" class="">aprantl@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html; charset=us-ascii" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class="">It looks like this may have broken the -DLLVM_ENABLE_MODULE=1 build:</div><div class=""><br class=""></div><a href="http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/5920/" class="">http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/5920/</a><div class=""><br class=""></div><div class=""><a href="http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/5920/consoleFull#1526032908a1ca8a51-895e-46c6-af87-ce24fa4cd561" class="">http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/5920/consoleFull#1526032908a1ca8a51-895e-46c6-af87-ce24fa4cd561</a></div><div class=""><br class=""></div><div class=""><span style="caret-color: rgb(51, 51, 51); color: rgb(51, 51, 51); font-family: monospace; font-size: 14px; white-space: pre-wrap;" class="">/Users/buildslave/jenkins/workspace/lldb-cmake/host-compiler/bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Itools/clang/lib/Lex -I/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Lex -I/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include -Itools/clang/include -I/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.14.sdk/usr/include/libxml2 -Iinclude -I/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/llvm/include -Wdocumentation -fPIC -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -fmodules -fmodules-cache-path=/Users/buildslave/jenkins/workspace/lldb-cmake/lldb-build/module.cache -fcxx-modules -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fdiagnostics-color -fno-common -Woverloaded-virtual -Wno-nested-anon-types -O3 -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.14.sdk -UNDEBUG -fno-exceptions -fno-rtti -std=c++14 -MD -MT tools/clang/lib/Lex/CMakeFiles/obj.clangLex.dir/HeaderMap.cpp.o -MF tools/clang/lib/Lex/CMakeFiles/obj.clangLex.dir/HeaderMap.cpp.o.d -o tools/clang/lib/Lex/CMakeFiles/obj.clangLex.dir/HeaderMap.cpp.o -c /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Lex/HeaderMap.cpp
While building module 'Clang_Lex' imported from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Lex/HeaderMap.cpp:13:
While building module 'Clang_Basic' imported from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Lex/Token.h:16:
In file included from <module-includes>:68:
In file included from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/TargetBuiltins.h:157:
</span><a id="-148564995649ba4694-19c4-4d7e-bec5-911270d8a58c" style="box-sizing: border-box; word-wrap: break-word; caret-color: rgb(51, 51, 51); color: rgb(51, 51, 51); font-family: monospace; font-size: 14px; white-space: pre-wrap; display: block; position: relative; top: -2em; visibility: hidden;" class=""></a><span title="Compile Error" style="box-sizing: border-box; font-family: monospace; font-size: 14px; white-space: pre-wrap; color: white; background-color: red;" class="">/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/BuiltinsHexagon.def:115:1: error: expected identifier
</span><span style="caret-color: rgb(51, 51, 51); color: rgb(51, 51, 51); font-family: monospace; font-size: 14px; white-space: pre-wrap;" class="">#include "clang/Basic/BuiltinsHexagonDep.def"
^
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/BuiltinsHexagon.def:115:1: error: expected '}'
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/TargetBuiltins.h:154:10: note: to match this '{'
enum {
^
While building module 'Clang_Lex' imported from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Lex/HeaderMap.cpp:13:
While building module 'Clang_Basic' imported from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Lex/Token.h:16:
In file included from <module-includes>:68:
In file included from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/TargetBuiltins.h:157:
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/BuiltinsHexagon.def:113:89: error: expected ';' after enum
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65")
^
;
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/BuiltinsHexagon.def:115:1: fatal error: import of module 'Clang_Basic.BuiltinsHexagonDep' appears within namespace 'clang::Hexagon'
#include "clang/Basic/BuiltinsHexagonDep.def"
^
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Basic/TargetBuiltins.h:153:3: note: namespace 'clang::Hexagon' begins here
namespace Hexagon {
^
While building module 'Clang_Lex' imported from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Lex/HeaderMap.cpp:13:
In file included from <module-includes>:1:
In file included from /Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Lex/MacroInfo.h:17:
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/include/clang/Lex/Token.h:16:10: fatal error: could not build module 'Clang_Basic'
#include "clang/Basic/SourceLocation.h"
~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Lex/HeaderMap.cpp:13:10: fatal error: could not build module 'Clang_Lex'
#include "clang/Lex/HeaderMap.h"
~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
6 errors generated.</span><br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Jan 16, 2020, at 11:12 AM, Krzysztof Parzyszek via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class=""><br class="">Author: Krzysztof Parzyszek<br class="">Date: 2020-01-16T13:11:18-06:00<br class="">New Revision: 5f65065437cdbb680a6552d12d43090dc8d632b9<br class=""><br class="">URL: <a href="https://github.com/llvm/llvm-project/commit/5f65065437cdbb680a6552d12d43090dc8d632b9" class="">https://github.com/llvm/llvm-project/commit/5f65065437cdbb680a6552d12d43090dc8d632b9</a><br class="">DIFF: <a href="https://github.com/llvm/llvm-project/commit/5f65065437cdbb680a6552d12d43090dc8d632b9.diff" class="">https://github.com/llvm/llvm-project/commit/5f65065437cdbb680a6552d12d43090dc8d632b9.diff</a><br class=""><br class="">LOG: [Hexagon] Update autogeneated intrinsic information in LLVM<br class=""><br class="">Added: <br class=""> llvm/include/llvm/IR/IntrinsicsHexagonDep.td<br class=""><br class="">Modified: <br class=""> llvm/include/llvm/IR/IntrinsicsHexagon.td<br class=""> llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td<br class=""><br class="">Removed: <br class=""><br class=""><br class=""><br class="">################################################################################<br class="">diff --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td<br class="">index 2abc1dc07ebd..f82cac156eca 100644<br class="">--- a/llvm/include/llvm/IR/IntrinsicsHexagon.td<br class="">+++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td<br class="">@@ -122,24 +122,8 @@ Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;<br class=""> def int_hexagon_circ_stb :<br class=""> Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;<br class=""><br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1)<br class="">-//<br class=""> def int_hexagon_prefetch :<br class=""> Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;<br class="">-def int_hexagon_Y2_dccleana :<br class="">-Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>;<br class="">-def int_hexagon_Y2_dccleaninva :<br class="">-Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>;<br class="">-def int_hexagon_Y2_dcinva :<br class="">-Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>;<br class="">-def int_hexagon_Y2_dczeroa :<br class="">-Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty],<br class="">- [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>;<br class="">-def int_hexagon_Y4_l2fetch :<br class="">-Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>;<br class="">-def int_hexagon_Y5_l2fetch :<br class="">-Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>;<br class=""><br class=""> def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;<br class=""> def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;<br class="">@@ -221,6 +205,55 @@ def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;<br class=""> def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;<br class=""> def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;<br class=""><br class="">+// tag : V6_vrmpybub_rtt<br class="">+class Hexagon_v32i32_v16i32i64_rtt_Intrinsic<string GCCIntSuffix><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],<br class="">+ [IntrNoMem]>;<br class="">+<br class="">+// tag : V6_vrmpybub_rtt_128B<br class="">+class Hexagon_v64i32_v32i32i64_rtt_Intrinsic<string GCCIntSuffix><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],<br class="">+ [IntrNoMem]>;<br class="">+<br class="">+// tag : V6_vrmpybub_rtt_acc<br class="">+class Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<string GCCIntSuffix><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],<br class="">+ [IntrNoMem]>;<br class="">+<br class="">+// tag : V6_vrmpybub_rtt_acc_128B<br class="">+class Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<string GCCIntSuffix><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],<br class="">+ [IntrNoMem]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpybub_rtt :<br class="">+Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybub_rtt_128B :<br class="">+Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybub_rtt_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybub_rtt_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_rtt :<br class="">+Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_rtt_128B :<br class="">+Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_rtt_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_rtt_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;<br class="">+<br class="">+<br class=""> //<br class=""> // Masked vector stores<br class=""> //<br class="">@@ -241,30 +274,6 @@ class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix><br class=""> [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],<br class=""> [IntrArgMemOnly]>;<br class=""><br class="">-def int_hexagon_V6_vS32b_qpred_ai :<br class="">-Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_nqpred_ai :<br class="">-Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_nt_qpred_ai :<br class="">-Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_nt_nqpred_ai :<br class="">-Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_qpred_ai_128B :<br class="">-Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_nqpred_ai_128B :<br class="">-Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_nt_qpred_ai_128B :<br class="">-Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;<br class="">-<br class="">-def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :<br class="">-Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;<br class="">-<br class=""> def int_hexagon_V6_vmaskedstoreq :<br class=""> Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;<br class=""><br class="">@@ -289,6089 +298,4 @@ Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;<br class=""> def int_hexagon_V6_vmaskedstorentnq_128B :<br class=""> Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;<br class=""><br class="">-class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v16i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v32i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v64i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v16i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v32i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v32i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v64i32_ty],<br class="">- [IntrArgMemOnly]>;<br class="">-<br class="">-def int_hexagon_V6_vgathermw :<br class="">-Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;<br class="">-<br class="">-def int_hexagon_V6_vgathermw_128B :<br class="">-Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgathermh :<br class="">-Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;<br class="">-<br class="">-def int_hexagon_V6_vgathermh_128B :<br class="">-Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgathermhw :<br class="">-Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;<br class="">-<br class="">-def int_hexagon_V6_vgathermhw_128B :<br class="">-Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgathermwq :<br class="">-Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;<br class="">-<br class="">-def int_hexagon_V6_vgathermwq_128B :<br class="">-Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgathermhq :<br class="">-Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;<br class="">-<br class="">-def int_hexagon_V6_vgathermhq_128B :<br class="">-Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgathermhwq :<br class="">-Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;<br class="">-<br class="">-def int_hexagon_V6_vgathermhwq_128B :<br class="">-Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;<br class="">-<br class="">-class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_v512i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v16i32_ty,<br class="">- llvm_v16i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_v1024i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v32i32_ty,<br class="">- llvm_v32i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v32i32_ty,llvm_v16i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_i32_ty,llvm_i32_ty,<br class="">- llvm_v64i32_ty,llvm_v32i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_v512i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v32i32_ty,<br class="">- llvm_v16i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [], [llvm_v1024i1_ty,llvm_i32_ty,<br class="">- llvm_i32_ty,llvm_v64i32_ty,<br class="">- llvm_v32i32_ty],<br class="">- [IntrWriteMem]>;<br class="">-<br class="">-class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermw<br class="">-def int_hexagon_V6_vscattermw :<br class="">-Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermw_128B<br class="">-def int_hexagon_V6_vscattermw_128B :<br class="">-Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermh<br class="">-def int_hexagon_V6_vscattermh :<br class="">-Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermh_128B<br class="">-def int_hexagon_V6_vscattermh_128B :<br class="">-Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermw_add<br class="">-def int_hexagon_V6_vscattermw_add :<br class="">-Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermw_add_128B<br class="">-def int_hexagon_V6_vscattermw_add_128B :<br class="">-Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermh_add<br class="">-def int_hexagon_V6_vscattermh_add :<br class="">-Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)<br class="">-// tag : V6_vscattermh_add_128B<br class="">-def int_hexagon_V6_vscattermh_add_128B :<br class="">-Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)<br class="">-// tag : V6_vscattermwq<br class="">-def int_hexagon_V6_vscattermwq :<br class="">-Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)<br class="">-// tag : V6_vscattermwq_128B<br class="">-def int_hexagon_V6_vscattermwq_128B :<br class="">-Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)<br class="">-// tag : V6_vscattermhq<br class="">-def int_hexagon_V6_vscattermhq :<br class="">-Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)<br class="">-// tag : V6_vscattermhq_128B<br class="">-def int_hexagon_V6_vscattermhq_128B :<br class="">-Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)<br class="">-// tag : V6_vscattermhw<br class="">-def int_hexagon_V6_vscattermhw :<br class="">-Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)<br class="">-// tag : V6_vscattermhw_128B<br class="">-def int_hexagon_V6_vscattermhw_128B :<br class="">-Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)<br class="">-// tag : V6_vscattermhwq<br class="">-def int_hexagon_V6_vscattermhwq :<br class="">-Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)<br class="">-// tag : V6_vscattermhwq_128B<br class="">-def int_hexagon_V6_vscattermhwq_128B :<br class="">-Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)<br class="">-// tag : V6_vscattermhw_add<br class="">-def int_hexagon_V6_vscattermhw_add :<br class="">-Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;<br class="">-<br class="">-//<br class="">-// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)<br class="">-// tag : V6_vscattermhw_add_128B<br class="">-def int_hexagon_V6_vscattermhw_add_128B :<br class="">-Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;<br class="">-<br class="">-// Auto-generated intrinsics<br class="">-<br class="">-// tag : S2_vsatwh<br class="">-class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrmpybusv<br class="">-class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrmpybusv<br class="">-class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vaslw_acc<br class="">-class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vaslw_acc<br class="">-class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vmux<br class="">-class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vmux<br class="">-class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S2_tableidxd_goodsyntax<br class="">-class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">-<br class="">-// tag : V6_vandnqrt_acc<br class="">-class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandnqrt_acc<br class="">-class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrmpybusi<br class="">-class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vrmpybusi<br class="">-class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vsubb_dv<br class="">-class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : M2_mpysu_up<br class="">-class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : M2_mpyud_acc_ll_s0<br class="">-class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : S2_lsr_i_r_nac<br class="">-class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : M2_cmpysc_s0<br class="">-class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_lo<br class="">-class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v32i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_lo<br class="">-class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v64i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : S2_shuffoh<br class="">-class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sfmax<br class="">-class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_float_ty,llvm_float_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : A2_vabswsat<br class="">-class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag :<br class="">-class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_ldnp0<br class="">-class Hexagon_v16i32_i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_ldnp0<br class="">-class Hexagon_v32i32_i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdmpyhb<br class="">-class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdmpyhb<br class="">-class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : A4_vcmphgti<br class="">-class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag :<br class="">-class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S6_rol_i_p_or<br class="">-class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vgtuh_and<br class="">-class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vgtuh_and<br class="">-class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : A2_abssat<br class="">-class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : A2_vcmpwgtu<br class="">-class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vtmpybus_acc<br class="">-class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_conv_df2uw_chop<br class="">-class Hexagon_i32_double_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_double_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_pred_or<br class="">-class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_pred_or<br class="">-class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S2_asr_i_p_rnd_goodsyntax<br class="">-class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : F2_conv_w2df<br class="">-class Hexagon_double_i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_double_ty], [llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vunpackuh<br class="">-class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vunpackuh<br class="">-class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vadduhw_acc<br class="">-class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vadduhw_acc<br class="">-class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : M2_vdmacs_s0<br class="">-class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrmpybub_rtt_acc<br class="">-class Hexagon_v32i32_v32i32v16i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrmpybub_rtt_acc<br class="">-class Hexagon_v64i32_v64i32v32i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_ldu0<br class="">-class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_ldu0<br class="">-class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S4_extract_rp<br class="">-class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdmpyhsuisat<br class="">-class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdmpyhsuisat<br class="">-class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : A2_addsp<br class="">-class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_extractw<br class="">-class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_extractw<br class="">-class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vlutvwhi<br class="">-class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vlutvwhi<br class="">-class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vgtuh<br class="">-class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vgtuh<br class="">-class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sffma_lib<br class="">-class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : F2_conv_ud2df<br class="">-class Hexagon_double_i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_double_ty], [llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S2_vzxthw<br class="">-class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vtmpyhb<br class="">-class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vshufoeh<br class="">-class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vshufoeh<br class="">-class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vlut4<br class="">-class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vlut4<br class="">-class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag :<br class="">-class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_conv_uw2sf<br class="">-class Hexagon_float_i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vswap<br class="">-class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vswap<br class="">-class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandnqrt<br class="">-class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandnqrt<br class="">-class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vmpyub<br class="">-class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : A5_ACS<br class="">-class Hexagon_i64i32_i64i64i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vunpackob<br class="">-class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vunpackob<br class="">-class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vmpyhsat_acc<br class="">-class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vmpyhsat_acc<br class="">-class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vaddcarrysat<br class="">-class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vaddcarrysat<br class="">-class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vlutvvb_oracc<br class="">-class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vlutvvb_oracc<br class="">-class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vrmpybub_rtt<br class="">-class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrmpybub_rtt<br class="">-class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : A4_addp_c<br class="">-class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vrsadubi_acc<br class="">-class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vrsadubi_acc<br class="">-class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : F2_conv_df2sf<br class="">-class Hexagon_float_double_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_double_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandvqv<br class="">-class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandvqv<br class="">-class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : C2_vmux<br class="">-class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sfcmpeq<br class="">-class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_float_ty,llvm_float_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : V6_vmpahhsat<br class="">-class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vmpahhsat<br class="">-class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandvrt<br class="">-class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandvrt<br class="">-class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vsubcarry<br class="">-class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic<br class="">- : Hexagon_NonGCC_Intrinsic<<br class="">- [llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vsubcarry<br class="">-class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B<br class="">- : Hexagon_NonGCC_Intrinsic<<br class="">- [llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sffixupr<br class="">-class Hexagon_float_float_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_float_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : V6_vandvrt_acc<br class="">-class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vandvrt_acc<br class="">-class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_dfsub<br class="">-class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_double_ty], [llvm_double_ty,llvm_double_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : V6_vmpyowh_sacc<br class="">-class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vmpyowh_sacc<br class="">-class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S2_insertp<br class="">-class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : F2_sfinvsqrta<br class="">-class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty,llvm_i32_ty], [llvm_float_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : V6_vtran2x2_map<br class="">-class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vtran2x2_map<br class="">-class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vlutvwh_oracc<br class="">-class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : V6_vlutvwh_oracc<br class="">-class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem], intr_properties)>;<br class="">-<br class="">-// tag : F2_dfcmpge<br class="">-class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_double_ty,llvm_double_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : F2_conv_df2d_chop<br class="">-class Hexagon_i64_double_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_double_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_conv_sf2w<br class="">-class Hexagon_i32_float_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_float_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sfclass<br class="">-class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],<br class="">- [IntrNoMem, Throws, ImmArg<1>]>;<br class="">-<br class="">-// tag : F2_conv_sf2ud_chop<br class="">-class Hexagon_i64_float_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty], [llvm_float_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_pred_scalar2v2<br class="">-class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_pred_scalar2v2<br class="">-class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sfrecipa<br class="">-class Hexagon_floati32_floatfloat_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty,llvm_i32_ty], [llvm_float_ty,llvm_float_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : V6_vprefixqh<br class="">-class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v512i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vprefixqh<br class="">-class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v1024i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdmpyhisat_acc<br class="">-class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdmpyhisat_acc<br class="">-class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_conv_ud2sf<br class="">-class Hexagon_float_i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_conv_sf2df<br class="">-class Hexagon_double_float_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_double_ty], [llvm_float_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : F2_sffma_sc<br class="">-class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],<br class="">- [IntrNoMem, Throws]>;<br class="">-<br class="">-// tag : F2_dfclass<br class="">-class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix,<br class="">- list<IntrinsicProperty> intr_properties = []><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],<br class="">- !listconcat([IntrNoMem, Throws], intr_properties)>;<br class="">-<br class="">-// tag : V6_vd0<br class="">-class Hexagon_v16i32__Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v16i32_ty], [],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vd0<br class="">-class Hexagon_v32i32__Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v32i32_ty], [],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vdd0<br class="">-class Hexagon_v64i32__Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : S2_insert_rp<br class="">-class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_vassignp<br class="">-class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v64i32_ty], [llvm_v64i32_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : A6_vminub_RdP<br class="">-class Hexagon_i64i32_i64i64_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_pred_not<br class="">-class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v512i1_ty], [llvm_v512i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// tag : V6_pred_not<br class="">-class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix><br class="">- : Hexagon_Intrinsic<GCCIntSuffix,<br class="">- [llvm_v1024i1_ty], [llvm_v1024i1_ty],<br class="">- [IntrNoMem]>;<br class="">-<br class="">-// V5 Scalar Instructions.<br class="">-<br class="">-def int_hexagon_S2_asr_r_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">;<br class="">-<br class="">-def int_hexagon_S2_vsatwh :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">;<br class="">-<br class="">-def int_hexagon_S2_tableidxd_goodsyntax :<br class="">-Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;<br class="">-<br class="">-def int_hexagon_M2_mpysu_up :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_ll_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_ll_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_cmpysc_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">;<br class="">-<br class="">-def int_hexagon_M2_cmpysc_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">;<br class="">-<br class="">-def int_hexagon_M4_cmpyi_whc :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_lh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_lh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;<br class="">-<br class="">-def int_hexagon_S2_tableidxb_goodsyntax :<br class="">-Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;<br class="">-<br class="">-def int_hexagon_S2_shuffoh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">;<br class="">-<br class="">-def int_hexagon_F2_sfmax :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">;<br class="">-<br class="">-def int_hexagon_A2_vabswsat :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_combineri :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_hl_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;<br class="">-<br class="">-def int_hexagon_M4_vpmpyh_acc :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;<br class="">-<br class="">-def int_hexagon_M2_vcmpy_s0_sat_i :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;<br class="">-<br class="">-def int_hexagon_A2_notp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">;<br class="">-<br class="">-def int_hexagon_M2_mpy_hl_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_hl_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;<br class="">-<br class="">-def int_hexagon_C4_or_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">;<br class="">-<br class="">-def int_hexagon_M2_vmac2s_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">;<br class="">-<br class="">-def int_hexagon_M2_vmac2s_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">;<br class="">-<br class="">-def int_hexagon_S2_brevp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">;<br class="">-<br class="">-def int_hexagon_M4_pmpyw_acc :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">;<br class="">-<br class="">-def int_hexagon_S2_cl1 :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">;<br class="">-<br class="">-def int_hexagon_C4_cmplte :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">;<br class="">-<br class="">-def int_hexagon_M2_mmpyul_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">;<br class="">-<br class="">-def int_hexagon_A2_vaddws :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;<br class="">-<br class="">-def int_hexagon_A2_maxup :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;<br class="">-<br class="">-def int_hexagon_A4_vcmphgti :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_interleave :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpyi_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;<br class="">-<br class="">-def int_hexagon_A2_abssat :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;<br class="">-<br class="">-def int_hexagon_A2_vcmpwgtu :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;<br class="">-<br class="">-def int_hexagon_C2_cmpgtu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;<br class="">-<br class="">-def int_hexagon_C2_cmpgtp :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;<br class="">-<br class="">-def int_hexagon_A4_cmphgtui :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_C2_cmpgti :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2uw_chop :<br class="">-Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;<br class="">-<br class="">-def int_hexagon_A4_cmpheq :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;<br class="">-<br class="">-def int_hexagon_M2_mpy_lh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_lh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_r_xacc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vrcnegh :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;<br class="">-<br class="">-def int_hexagon_S2_extractup :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [ImmArg<1>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p_rnd_goodsyntax :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S4_ntstbit_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;<br class="">-<br class="">-def int_hexagon_F2_conv_w2sf :<br class="">-Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;<br class="">-<br class="">-def int_hexagon_C2_not :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">;<br class="">-<br class="">-def int_hexagon_C2_tfrpr :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">;<br class="">-<br class="">-def int_hexagon_M2_mpy_ll_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_ll_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;<br class="">-<br class="">-def int_hexagon_A4_cmpbgt :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;<br class="">-<br class="">-def int_hexagon_A4_rcmpneqi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_subacc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;<br class="">-<br class="">-def int_hexagon_A2_orp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_up :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_lh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asr_i_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_cmpbgtu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;<br class="">-<br class="">-def int_hexagon_A4_vcmpbeq_any :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;<br class="">-<br class="">-def int_hexagon_A4_cmpbgti :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyd_lh_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_addsp :<br class="">-Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;<br class="">-<br class="">-def int_hexagon_S4_vxsubaddw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;<br class="">-<br class="">-def int_hexagon_A4_vcmpheqi :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S4_vxsubaddh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;<br class="">-<br class="">-def int_hexagon_M4_pmpyw :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;<br class="">-<br class="">-def int_hexagon_S2_vsathb :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_lh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_lh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;<br class="">-<br class="">-def int_hexagon_A2_pxorf :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">;<br class="">-<br class="">-def int_hexagon_C2_cmpgei :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_vsubub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_vrminuw :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;<br class="">-<br class="">-def int_hexagon_F2_sffma :<br class="">-Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">;<br class="">-<br class="">-def int_hexagon_A2_absp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">;<br class="">-<br class="">-def int_hexagon_C2_all8 :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">;<br class="">-<br class="">-def int_hexagon_A4_vrminuh :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">;<br class="">-<br class="">-def int_hexagon_F2_sffma_lib :<br class="">-Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyoh_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyoh_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;<br class="">-<br class="">-def int_hexagon_C2_bitsset :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;<br class="">-<br class="">-def int_hexagon_M2_mpysip :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpysin :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_boundscheck :<br class="">-Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;<br class="">-<br class="">-def int_hexagon_M5_vrmpybuu :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;<br class="">-<br class="">-def int_hexagon_C4_fastcorner9 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpys_s1rp :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;<br class="">-<br class="">-def int_hexagon_A2_neg :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">;<br class="">-<br class="">-def int_hexagon_A2_subsat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">;<br class="">-<br class="">-def int_hexagon_A2_vnavgh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_hl_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;<br class="">-<br class="">-def int_hexagon_F2_conv_ud2df :<br class="">-Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;<br class="">-<br class="">-def int_hexagon_A2_vnavgw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S4_subi_lsr_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vzxthw :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;<br class="">-<br class="">-def int_hexagon_F2_sfadd :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">;<br class="">-<br class="">-def int_hexagon_A2_sub :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">;<br class="">-<br class="">-def int_hexagon_M2_vmac2su_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">;<br class="">-<br class="">-def int_hexagon_M2_vmac2su_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">;<br class="">-<br class="">-def int_hexagon_M2_dpmpyss_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;<br class="">-<br class="">-def int_hexagon_S2_insert :<br class="">-Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">;<br class="">-<br class="">-def int_hexagon_S2_packhl :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;<br class="">-<br class="">-def int_hexagon_A4_vcmpwgti :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_vavguwr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;<br class="">-<br class="">-def int_hexagon_A2_svsubhs :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;<br class="">-<br class="">-def int_hexagon_A2_addh_l16_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;<br class="">-<br class="">-def int_hexagon_M4_and_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;<br class="">-<br class="">-def int_hexagon_F2_conv_d2df :<br class="">-Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;<br class="">-<br class="">-def int_hexagon_C2_cmpgtui :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_vconj :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">;<br class="">-<br class="">-def int_hexagon_A2_subh_l16_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">;<br class="">-<br class="">-def int_hexagon_S4_vxsubaddhr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">;<br class="">-<br class="">-def int_hexagon_S2_clbp :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">;<br class="">-<br class="">-def int_hexagon_S2_deinterleave :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">;<br class="">-<br class="">-def int_hexagon_C2_any8 :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;<br class="">-<br class="">-def int_hexagon_S2_togglebit_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;<br class="">-<br class="">-def int_hexagon_S2_togglebit_i :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_F2_conv_uw2sf :<br class="">-Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;<br class="">-<br class="">-def int_hexagon_S2_vsathb_nopack :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;<br class="">-<br class="">-def int_hexagon_M2_cmacs_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">;<br class="">-<br class="">-def int_hexagon_M2_cmacs_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_hh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_hh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmacuhs_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmacuhs_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;<br class="">-<br class="">-def int_hexagon_S2_clrbit_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">;<br class="">-<br class="">-def int_hexagon_C4_or_andn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A4_vcmpwgtui :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M4_vrmpyoh_acc_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyoh_acc_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;<br class="">-<br class="">-def int_hexagon_A4_vrmaxh :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">;<br class="">-<br class="">-def int_hexagon_A2_vcmpbeq :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">;<br class="">-<br class="">-def int_hexagon_A2_vcmphgt :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">;<br class="">-<br class="">-def int_hexagon_A2_vnavgwcr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">;<br class="">-<br class="">-def int_hexagon_M2_vrcmacr_s0c :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;<br class="">-<br class="">-def int_hexagon_A2_vavgwcr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_p_xacc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A4_vrmaxw :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;<br class="">-<br class="">-def int_hexagon_A2_vnavghr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;<br class="">-<br class="">-def int_hexagon_M4_cmpyi_wh :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;<br class="">-<br class="">-def int_hexagon_A2_tfrsi :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_svnavgh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_vmac2 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;<br class="">-<br class="">-def int_hexagon_A4_vcmphgtui :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_svavgh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyeh_acc_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyeh_acc_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_combine_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;<br class="">-<br class="">-def int_hexagon_M2_mpy_up :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;<br class="">-<br class="">-def int_hexagon_A2_combine_hh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">;<br class="">-<br class="">-def int_hexagon_A2_negsat :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_hl_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_hl_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;<br class="">-<br class="">-def int_hexagon_A4_bitsplit :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">;<br class="">-<br class="">-def int_hexagon_A2_vabshsat :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">;<br class="">-<br class="">-def int_hexagon_M2_mpyui :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">;<br class="">-<br class="">-def int_hexagon_A2_addh_l16_sat_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;<br class="">-<br class="">-def int_hexagon_M2_mmpyul_rs0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r_rnd_goodsyntax :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;<br class="">-<br class="">-def int_hexagon_C2_cmplt :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;<br class="">-<br class="">-def int_hexagon_M2_cmacr_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;<br class="">-<br class="">-def int_hexagon_M4_or_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;<br class="">-<br class="">-def int_hexagon_M4_mpyrr_addi :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_S4_or_andi :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_hl_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_hl_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;<br class="">-<br class="">-def int_hexagon_M4_mpyrr_addr :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">;<br class="">-<br class="">-def int_hexagon_M2_mmachs_rs0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">;<br class="">-<br class="">-def int_hexagon_M2_mmachs_rs1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpyr_s0c :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_hl_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_ll_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;<br class="">-<br class="">-def int_hexagon_F2_sffixupn :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_lh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_lh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_hh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_hh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;<br class="">-<br class="">-def int_hexagon_A2_vadduhs :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">;<br class="">-<br class="">-def int_hexagon_A2_vsubuhs :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_hh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">;<br class="">-<br class="">-def int_hexagon_A2_xorp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">;<br class="">-<br class="">-def int_hexagon_A4_tfrpcp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrpcp">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_lh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_sat_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_sat_hh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;<br class="">-<br class="">-def int_hexagon_A2_zxtb :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">;<br class="">-<br class="">-def int_hexagon_A2_zxth :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">;<br class="">-<br class="">-def int_hexagon_A2_vnavgwr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">;<br class="">-<br class="">-def int_hexagon_M4_or_xor :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_hh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_hh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;<br class="">-<br class="">-def int_hexagon_M5_vmacbsu :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">;<br class="">-<br class="">-def int_hexagon_M2_dpmpyuu_acc_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_hl_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_hl_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;<br class="">-<br class="">-def int_hexagon_F2_sffms_lib :<br class="">-Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">;<br class="">-<br class="">-def int_hexagon_C4_cmpneqi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M4_and_xor :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;<br class="">-<br class="">-def int_hexagon_A2_sat :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_lh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_lh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;<br class="">-<br class="">-def int_hexagon_A2_addsat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;<br class="">-<br class="">-def int_hexagon_A2_svavghs :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;<br class="">-<br class="">-def int_hexagon_A2_vrsadub_acc :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;<br class="">-<br class="">-def int_hexagon_C2_bitsclri :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_sat_hh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_sat_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;<br class="">-<br class="">-def int_hexagon_M2_mmaculs_rs0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;<br class="">-<br class="">-def int_hexagon_M2_mmaculs_rs1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;<br class="">-<br class="">-def int_hexagon_M2_vradduh :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">;<br class="">-<br class="">-def int_hexagon_A4_addp_c :<br class="">-Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_addp_c">;<br class="">-<br class="">-def int_hexagon_C2_xor :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;<br class="">-<br class="">-def int_hexagon_M2_mmpyh_rs1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;<br class="">-<br class="">-def int_hexagon_M2_mmpyh_rs0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2ud_chop :<br class="">-Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;<br class="">-<br class="">-def int_hexagon_C4_or_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">;<br class="">-<br class="">-def int_hexagon_S4_vxaddsubhr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">;<br class="">-<br class="">-def int_hexagon_S2_vsathub :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2sf :<br class="">-Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">;<br class="">-<br class="">-def int_hexagon_M2_hmmpyh_rs1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;<br class="">-<br class="">-def int_hexagon_M2_hmmpyh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;<br class="">-<br class="">-def int_hexagon_A2_vavgwr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">;<br class="">-<br class="">-def int_hexagon_S2_tableidxh_goodsyntax :<br class="">-Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;<br class="">-<br class="">-def int_hexagon_A2_sxth :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">;<br class="">-<br class="">-def int_hexagon_A2_sxtb :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">;<br class="">-<br class="">-def int_hexagon_C4_or_orn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">;<br class="">-<br class="">-def int_hexagon_M2_vrcmaci_s0c :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;<br class="">-<br class="">-def int_hexagon_A2_sxtw :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">;<br class="">-<br class="">-def int_hexagon_M2_vabs<br class="">diff h :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabs<br class="">diff h">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_lh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_lh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;<br class="">-<br class="">-def int_hexagon_M2_hmmpyl_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;<br class="">-<br class="">-def int_hexagon_S2_cl1p :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">;<br class="">-<br class="">-def int_hexagon_M2_vabs<br class="">diff w :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabs<br class="">diff w">;<br class="">-<br class="">-def int_hexagon_A4_andnp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">;<br class="">-<br class="">-def int_hexagon_C2_vmux :<br class="">-Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;<br class="">-<br class="">-def int_hexagon_S2_parityp :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_ll_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_ll_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;<br class="">-<br class="">-def int_hexagon_F2_sfcmpeq :<br class="">-Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq">;<br class="">-<br class="">-def int_hexagon_A2_vaddb_map :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;<br class="">-<br class="">-def int_hexagon_A2_vcmpheq :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">;<br class="">-<br class="">-def int_hexagon_S2_clbnorm :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">;<br class="">-<br class="">-def int_hexagon_M2_cnacsc_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;<br class="">-<br class="">-def int_hexagon_M2_cnacsc_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;<br class="">-<br class="">-def int_hexagon_S4_subaddi :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_hl_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_hl_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;<br class="">-<br class="">-def int_hexagon_S5_vasrhrnd_goodsyntax :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_tstbit_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;<br class="">-<br class="">-def int_hexagon_S4_vrcrotate :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mmachs_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmachs_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;<br class="">-<br class="">-def int_hexagon_S2_tstbit_i :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_up_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;<br class="">-<br class="">-def int_hexagon_S2_extractu_rp :<br class="">-Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;<br class="">-<br class="">-def int_hexagon_M2_mmpyuh_rs0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_ll_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_ll_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;<br class="">-<br class="">-def int_hexagon_M4_or_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_hh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_hh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_lh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_lh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_ll_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_ll_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;<br class="">-<br class="">-def int_hexagon_F2_conv_w2df :<br class="">-Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;<br class="">-<br class="">-def int_hexagon_A2_subh_l16_sat_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;<br class="">-<br class="">-def int_hexagon_C2_cmpeqi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vcnegh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;<br class="">-<br class="">-def int_hexagon_A4_vcmpweqi :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_vdmpyrs_s0 :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;<br class="">-<br class="">-def int_hexagon_M2_vdmpyrs_s1 :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;<br class="">-<br class="">-def int_hexagon_M4_xor_xacc :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">;<br class="">-<br class="">-def int_hexagon_M2_vdmpys_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">;<br class="">-<br class="">-def int_hexagon_M2_vdmpys_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">;<br class="">-<br class="">-def int_hexagon_A2_vavgubr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_hl_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_hl_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;<br class="">-<br class="">-def int_hexagon_S2_cl0p :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;<br class="">-<br class="">-def int_hexagon_S2_valignib :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_F2_sffixupd :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_hl_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_hl_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_cmacsc_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">;<br class="">-<br class="">-def int_hexagon_M2_cmacsc_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">;<br class="">-<br class="">-def int_hexagon_S2_ct1 :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">;<br class="">-<br class="">-def int_hexagon_S2_ct0 :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">;<br class="">-<br class="">-def int_hexagon_M2_dpmpyuu_nac_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;<br class="">-<br class="">-def int_hexagon_M2_mmpyul_rs1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;<br class="">-<br class="">-def int_hexagon_S4_ntstbit_i :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [ImmArg<1>]> ;<br class="">-<br class="">-def int_hexagon_F2_sffixupr :<br class="">-Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_p_xor :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_hl_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_hl_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;<br class="">-<br class="">-def int_hexagon_A2_vcmphgtu :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;<br class="">-<br class="">-def int_hexagon_C2_andn :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2s_s0pack :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;<br class="">-<br class="">-def int_hexagon_S4_addaddi :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_ll_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_hl_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;<br class="">-<br class="">-def int_hexagon_A4_rcmpeqi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M4_xor_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mmpyuh_rs1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;<br class="">-<br class="">-def int_hexagon_A4_round_ri :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_max :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;<br class="">-<br class="">-def int_hexagon_A4_round_rr :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;<br class="">-<br class="">-def int_hexagon_A4_combineii :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii", [ImmArg<0>, ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_combineir :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_C4_and_orn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;<br class="">-<br class="">-def int_hexagon_M5_vmacbuu :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;<br class="">-<br class="">-def int_hexagon_A4_rcmpeq :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;<br class="">-<br class="">-def int_hexagon_M4_cmpyr_whc :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vzxtbh :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;<br class="">-<br class="">-def int_hexagon_M2_mmacuhs_rs1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_r_sat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;<br class="">-<br class="">-def int_hexagon_A2_combinew :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_ll_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_ll_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_cmpyi_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;<br class="">-<br class="">-def int_hexagon_S4_ori_asl_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_C4_nbitsset :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_hh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_hh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_ll_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_ll_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;<br class="">-<br class="">-def int_hexagon_A2_addh_l16_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;<br class="">-<br class="">-def int_hexagon_A4_modwrapu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">;<br class="">-<br class="">-def int_hexagon_A4_rcmpneq :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_hh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_hh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;<br class="">-<br class="">-def int_hexagon_F2_sfimm_p :<br class="">-Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_F2_sfimm_n :<br class="">-Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_M4_cmpyr_wh :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;<br class="">-<br class="">-def int_hexagon_A2_vavgub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;<br class="">-<br class="">-def int_hexagon_F2_conv_d2sf :<br class="">-Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;<br class="">-<br class="">-def int_hexagon_A2_vavguh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;<br class="">-<br class="">-def int_hexagon_A4_cmpbeqi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_F2_sfcmpuo :<br class="">-Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">;<br class="">-<br class="">-def int_hexagon_A2_vavguw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vsatwh_nopack :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_hh_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_hh_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;<br class="">-<br class="">-def int_hexagon_A2_minu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_lh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;<br class="">-<br class="">-def int_hexagon_M4_or_andn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;<br class="">-<br class="">-def int_hexagon_A2_minp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;<br class="">-<br class="">-def int_hexagon_S4_or_andix :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_lh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_rnd_lh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmpyuh_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mmpyuh_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_lh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;<br class="">-<br class="">-def int_hexagon_F2_sfcmpge :<br class="">-Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge">;<br class="">-<br class="">-def int_hexagon_F2_sfmin :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin">;<br class="">-<br class="">-def int_hexagon_F2_sfcmpgt :<br class="">-Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt">;<br class="">-<br class="">-def int_hexagon_M4_vpmpyh :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">;<br class="">-<br class="">-def int_hexagon_M2_mmacuhs_rs0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_lh_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_lh_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;<br class="">-<br class="">-def int_hexagon_A2_roundsat :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">;<br class="">-<br class="">-def int_hexagon_S2_ct1p :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">;<br class="">-<br class="">-def int_hexagon_S4_extract_rp :<br class="">-Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;<br class="">-<br class="">-def int_hexagon_C4_cmplteui :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S4_addi_lsr_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A4_tfrcpp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_svw_trun :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_cmphgti :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_vrminh :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;<br class="">-<br class="">-def int_hexagon_A4_vrminw :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;<br class="">-<br class="">-def int_hexagon_A4_cmphgtu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;<br class="">-<br class="">-def int_hexagon_S2_insertp_rp :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;<br class="">-<br class="">-def int_hexagon_A2_vnavghcr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;<br class="">-<br class="">-def int_hexagon_S4_subi_asl_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;<br class="">-<br class="">-def int_hexagon_M2_mpy_hh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;<br class="">-<br class="">-def int_hexagon_A2_vsubws :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;<br class="">-<br class="">-def int_hexagon_A2_sath :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_p_xor :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;<br class="">-<br class="">-def int_hexagon_A2_satb :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;<br class="">-<br class="">-def int_hexagon_C2_cmpltu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;<br class="">-<br class="">-def int_hexagon_S2_insertp :<br class="">-Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [ImmArg<2>, ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_ll_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_ll_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_extractup_rp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;<br class="">-<br class="">-def int_hexagon_S4_vxaddsubw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;<br class="">-<br class="">-def int_hexagon_S4_vxaddsubh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">;<br class="">-<br class="">-def int_hexagon_A2_asrh :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">;<br class="">-<br class="">-def int_hexagon_S4_extractp_rp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_ll_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_ll_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;<br class="">-<br class="">-def int_hexagon_C2_or :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">;<br class="">-<br class="">-def int_hexagon_M2_mmpyul_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">;<br class="">-<br class="">-def int_hexagon_M2_vrcmacr_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;<br class="">-<br class="">-def int_hexagon_A2_xor :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">;<br class="">-<br class="">-def int_hexagon_A2_add :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">;<br class="">-<br class="">-def int_hexagon_A2_vsububs :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2s_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2s_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;<br class="">-<br class="">-def int_hexagon_A2_vraddub_acc :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">;<br class="">-<br class="">-def int_hexagon_F2_sfinvsqrta :<br class="">-Hexagon_floati32_float_Intrinsic<"HEXAGON_F2_sfinvsqrta">;<br class="">-<br class="">-def int_hexagon_S2_ct0p :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">;<br class="">-<br class="">-def int_hexagon_A2_svaddh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">;<br class="">-<br class="">-def int_hexagon_S2_vcrotate :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">;<br class="">-<br class="">-def int_hexagon_A2_aslh :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_lh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">;<br class="">-<br class="">-def int_hexagon_M2_hmmpyl_rs1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">;<br class="">-<br class="">-def int_hexagon_S2_vsplatrh :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">;<br class="">-<br class="">-def int_hexagon_S2_vsplatrb :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_hh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">;<br class="">-<br class="">-def int_hexagon_M2_cmpyr_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;<br class="">-<br class="">-def int_hexagon_M2_dpmpyss_rnd_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;<br class="">-<br class="">-def int_hexagon_C2_muxri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_vmac2es_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;<br class="">-<br class="">-def int_hexagon_M2_vmac2es_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;<br class="">-<br class="">-def int_hexagon_C2_pxfer_map :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_lh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_lh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_hl_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_acc_hl_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;<br class="">-<br class="">-def int_hexagon_A2_vaddw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_vaddh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_lh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_lh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;<br class="">-<br class="">-def int_hexagon_C2_cmpeqp :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;<br class="">-<br class="">-def int_hexagon_M4_mpyri_addi :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_not :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;<br class="">-<br class="">-def int_hexagon_S4_andi_lsr_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_macsip :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_tfrcrr :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">;<br class="">-<br class="">-def int_hexagon_M2_macsin :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_C2_orn :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;<br class="">-<br class="">-def int_hexagon_M4_and_andn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;<br class="">-<br class="">-def int_hexagon_F2_sfmpy :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_hh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_hh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">;<br class="">-<br class="">-def int_hexagon_M4_and_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">;<br class="">-<br class="">-def int_hexagon_C2_mask :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_hh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_hh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_up_s1_sat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;<br class="">-<br class="">-def int_hexagon_A4_vcmpbgt :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">;<br class="">-<br class="">-def int_hexagon_M5_vrmacbsu :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">;<br class="">-<br class="">-def int_hexagon_S2_tableidxw_goodsyntax :<br class="">-Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;<br class="">-<br class="">-def int_hexagon_A2_vrsadub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">;<br class="">-<br class="">-def int_hexagon_A2_tfrrcr :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrrcr">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpys_acc_s1 :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;<br class="">-<br class="">-def int_hexagon_F2_dfcmpge :<br class="">-Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">;<br class="">-<br class="">-def int_hexagon_M2_accii :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A5_vaddhubs :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;<br class="">-<br class="">-def int_hexagon_A2_vmaxw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;<br class="">-<br class="">-def int_hexagon_A2_vmaxb :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;<br class="">-<br class="">-def int_hexagon_A2_vmaxh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;<br class="">-<br class="">-def int_hexagon_S2_vsxthw :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;<br class="">-<br class="">-def int_hexagon_S4_andi_asl_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_p_xor :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;<br class="">-<br class="">-def int_hexagon_C2_cmpgt :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2d_chop :<br class="">-Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_hl_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_hl_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2w :<br class="">-Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;<br class="">-<br class="">-def int_hexagon_F2_sfclass :<br class="">-Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_lh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;<br class="">-<br class="">-def int_hexagon_M4_xor_andn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;<br class="">-<br class="">-def int_hexagon_S2_addasl_rrri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M5_vdmpybsu :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_hh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_nac_hh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;<br class="">-<br class="">-def int_hexagon_A2_addi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_addp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2s_s1pack :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;<br class="">-<br class="">-def int_hexagon_S4_clbpnorm :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">;<br class="">-<br class="">-def int_hexagon_A4_round_rr_sat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">;<br class="">-<br class="">-def int_hexagon_M2_nacci :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">;<br class="">-<br class="">-def int_hexagon_S2_shuffeh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_hh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_hh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2uw :<br class="">-Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">;<br class="">-<br class="">-def int_hexagon_A2_vsubh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2ud :<br class="">-Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">;<br class="">-<br class="">-def int_hexagon_A2_vsubw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">;<br class="">-<br class="">-def int_hexagon_A2_vcmpwgt :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">;<br class="">-<br class="">-def int_hexagon_M4_xor_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2uw_chop :<br class="">-Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">;<br class="">-<br class="">-def int_hexagon_S2_vsatwuh_nopack :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">;<br class="">-<br class="">-def int_hexagon_A2_svsubuhs :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">;<br class="">-<br class="">-def int_hexagon_M5_vmpybsu :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">;<br class="">-<br class="">-def int_hexagon_A2_subh_l16_sat_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;<br class="">-<br class="">-def int_hexagon_C4_and_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_hl_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_hl_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">;<br class="">-<br class="">-def int_hexagon_A4_subp_c :<br class="">-Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_subp_c">;<br class="">-<br class="">-def int_hexagon_A2_vsubhs :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">;<br class="">-<br class="">-def int_hexagon_C2_vitpack :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">;<br class="">-<br class="">-def int_hexagon_A2_vavguhr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">;<br class="">-<br class="">-def int_hexagon_S2_vsplicerb :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">;<br class="">-<br class="">-def int_hexagon_C4_nbitsclr :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">;<br class="">-<br class="">-def int_hexagon_A2_vcmpbgtu :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">;<br class="">-<br class="">-def int_hexagon_M2_cmpys_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">;<br class="">-<br class="">-def int_hexagon_M2_cmpys_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">;<br class="">-<br class="">-def int_hexagon_F2_dfcmpuo :<br class="">-Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo">;<br class="">-<br class="">-def int_hexagon_S2_shuffob :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">;<br class="">-<br class="">-def int_hexagon_C2_and :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">;<br class="">-<br class="">-def int_hexagon_S5_popcountp :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">;<br class="">-<br class="">-def int_hexagon_S4_extractp :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [ImmArg<1>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_cl0 :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">;<br class="">-<br class="">-def int_hexagon_A4_vcmpbgti :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mmacls_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmacls_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">;<br class="">-<br class="">-def int_hexagon_C4_cmpneq :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">;<br class="">-<br class="">-def int_hexagon_M2_vmac2es :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">;<br class="">-<br class="">-def int_hexagon_M2_vdmacs_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">;<br class="">-<br class="">-def int_hexagon_M2_vdmacs_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_ll_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_ll_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;<br class="">-<br class="">-def int_hexagon_S2_clb :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_ll_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_ll_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_hl_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_hl_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_maci :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">;<br class="">-<br class="">-def int_hexagon_A2_vmaxuh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">;<br class="">-<br class="">-def int_hexagon_A4_bitspliti :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_vmaxub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_hh_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_hh_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_vrmac_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_lh_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_r_sat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2d :<br class="">-Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;<br class="">-<br class="">-def int_hexagon_F2_dfimm_n :<br class="">-Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_A4_cmphgt :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">;<br class="">-<br class="">-def int_hexagon_F2_dfimm_p :<br class="">-Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyud_acc_lh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_vcmpy_s1_sat_r :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;<br class="">-<br class="">-def int_hexagon_M4_mpyri_addr_u2 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_vcmpy_s1_sat_i :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;<br class="">-<br class="">-def int_hexagon_M5_vrmacbuu :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">;<br class="">-<br class="">-def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_vspliceib :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_dpmpyss_acc_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;<br class="">-<br class="">-def int_hexagon_M2_cnacs_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">;<br class="">-<br class="">-def int_hexagon_M2_cnacs_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">;<br class="">-<br class="">-def int_hexagon_A2_maxu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">;<br class="">-<br class="">-def int_hexagon_A2_maxp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">;<br class="">-<br class="">-def int_hexagon_A2_andir :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_F2_sfrecipa :<br class="">-Hexagon_floati32_floatfloat_Intrinsic<"HEXAGON_F2_sfrecipa">;<br class="">-<br class="">-def int_hexagon_A2_combineii :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [ImmArg<0>, ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_orn :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">;<br class="">-<br class="">-def int_hexagon_A4_cmpbgtui :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;<br class="">-<br class="">-def int_hexagon_A4_vcmpbeqi :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">;<br class="">-<br class="">-def int_hexagon_A2_or :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">;<br class="">-<br class="">-def int_hexagon_F2_dfcmpeq :<br class="">-Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq">;<br class="">-<br class="">-def int_hexagon_C2_cmpeq :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">;<br class="">-<br class="">-def int_hexagon_A2_tfrp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">;<br class="">-<br class="">-def int_hexagon_C4_and_andn :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">;<br class="">-<br class="">-def int_hexagon_S2_vsathub_nopack :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">;<br class="">-<br class="">-def int_hexagon_A2_satuh :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">;<br class="">-<br class="">-def int_hexagon_A2_satub :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpys_s1 :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;<br class="">-<br class="">-def int_hexagon_S4_or_ori :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_C4_fastcorner9_not :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">;<br class="">-<br class="">-def int_hexagon_A2_tfrih :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_tfril :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M4_mpyri_addr :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vtrunehb :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">;<br class="">-<br class="">-def int_hexagon_A2_vabsw :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">;<br class="">-<br class="">-def int_hexagon_A2_vabsh :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">;<br class="">-<br class="">-def int_hexagon_F2_sfsub :<br class="">-Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub">;<br class="">-<br class="">-def int_hexagon_C2_muxii :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [ImmArg<1>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_C2_muxir :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_swiz :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_cmpyrsc_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;<br class="">-<br class="">-def int_hexagon_M2_cmpyrsc_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;<br class="">-<br class="">-def int_hexagon_A2_vraddub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">;<br class="">-<br class="">-def int_hexagon_A4_tlbmatch :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2w_chop :<br class="">-Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;<br class="">-<br class="">-def int_hexagon_A2_and :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_ll_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_ll_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;<br class="">-<br class="">-def int_hexagon_S4_extract :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [ImmArg<1>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_vcmpweq :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">;<br class="">-<br class="">-def int_hexagon_M2_acci :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_F2_conv_ud2sf :<br class="">-Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">;<br class="">-<br class="">-def int_hexagon_A2_tfr :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_subri :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_A4_vrmaxuw :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">;<br class="">-<br class="">-def int_hexagon_M5_vmpybuu :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">;<br class="">-<br class="">-def int_hexagon_A4_vrmaxuh :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_vavgw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">;<br class="">-<br class="">-def int_hexagon_S2_brev :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">;<br class="">-<br class="">-def int_hexagon_A2_vavgh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">;<br class="">-<br class="">-def int_hexagon_S2_clrbit_i :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;<br class="">-<br class="">-def int_hexagon_M2_mmpyl_rs1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_hl_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmpyl_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mmpyl_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">;<br class="">-<br class="">-def int_hexagon_M2_naccii :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S2_vrndpackwhs :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">;<br class="">-<br class="">-def int_hexagon_S2_vtrunewh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">;<br class="">-<br class="">-def int_hexagon_M2_dpmpyss_nac_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_ll_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_ll_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;<br class="">-<br class="">-def int_hexagon_M4_mac_up_s1_sat :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;<br class="">-<br class="">-def int_hexagon_S4_vrcrotate_acc :<br class="">-Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_F2_conv_uw2df :<br class="">-Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">;<br class="">-<br class="">-def int_hexagon_A2_vaddubs :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;<br class="">-<br class="">-def int_hexagon_A2_orir :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_andp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">;<br class="">-<br class="">-def int_hexagon_S2_lfsp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">;<br class="">-<br class="">-def int_hexagon_A2_min :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">;<br class="">-<br class="">-def int_hexagon_M2_mpysmi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_vcmpy_s0_sat_r :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_ll_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyu_acc_ll_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_svw_trun :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;<br class="">-<br class="">-def int_hexagon_M2_mmpyh_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mmpyh_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2df :<br class="">-Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">;<br class="">-<br class="">-def int_hexagon_S2_vtrunohb :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2d_chop :<br class="">-Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_lh_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2w :<br class="">-Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">;<br class="">-<br class="">-def int_hexagon_S5_asrhub_sat :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r_xacc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_F2_conv_df2d :<br class="">-Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">;<br class="">-<br class="">-def int_hexagon_M2_mmaculs_s1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">;<br class="">-<br class="">-def int_hexagon_M2_mmaculs_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">;<br class="">-<br class="">-def int_hexagon_A2_svadduhs :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2w_chop :<br class="">-Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;<br class="">-<br class="">-def int_hexagon_S2_svsathub :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_hl_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_hl_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;<br class="">-<br class="">-def int_hexagon_S2_setbit_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">;<br class="">-<br class="">-def int_hexagon_A2_vavghr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">;<br class="">-<br class="">-def int_hexagon_F2_sffma_sc :<br class="">-Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc">;<br class="">-<br class="">-def int_hexagon_F2_dfclass :<br class="">-Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_F2_conv_df2ud :<br class="">-Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">;<br class="">-<br class="">-def int_hexagon_F2_conv_df2uw :<br class="">-Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">;<br class="">-<br class="">-def int_hexagon_M2_cmpyrs_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;<br class="">-<br class="">-def int_hexagon_M2_cmpyrs_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;<br class="">-<br class="">-def int_hexagon_C4_cmpltei :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_C4_cmplteu :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">;<br class="">-<br class="">-def int_hexagon_A2_vsubb_map :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">;<br class="">-<br class="">-def int_hexagon_A2_subh_l16_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r_rnd :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_vrmpy_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_hh_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_rnd_hh_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;<br class="">-<br class="">-def int_hexagon_A2_minup :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">;<br class="">-<br class="">-def int_hexagon_S2_valignrb :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">;<br class="">-<br class="">-def int_hexagon_S2_asr_r_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;<br class="">-<br class="">-def int_hexagon_M2_mmpyl_rs0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;<br class="">-<br class="">-def int_hexagon_M2_vrcmaci_s0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;<br class="">-<br class="">-def int_hexagon_A2_vaddub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">;<br class="">-<br class="">-def int_hexagon_A2_combine_lh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">;<br class="">-<br class="">-def int_hexagon_M5_vdmacbsu :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">;<br class="">-<br class="">-def int_hexagon_A2_combine_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_hl_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpyi_s0c :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p_rnd :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_addpsat :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">;<br class="">-<br class="">-def int_hexagon_A2_svaddhs :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">;<br class="">-<br class="">-def int_hexagon_S4_ori_lsr_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_ll_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_sat_rnd_ll_s0 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;<br class="">-<br class="">-def int_hexagon_A2_vminw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">;<br class="">-<br class="">-def int_hexagon_A2_vminh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">;<br class="">-<br class="">-def int_hexagon_M2_vrcmpyr_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;<br class="">-<br class="">-def int_hexagon_A2_vminb :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">;<br class="">-<br class="">-def int_hexagon_M2_vcmac_s0_sat_i :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_lh_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_lh_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">;<br class="">-<br class="">-def int_hexagon_S4_lsli :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_S2_lsl_r_vw :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">;<br class="">-<br class="">-def int_hexagon_M2_mpy_hh_s1 :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyeh_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;<br class="">-<br class="">-def int_hexagon_M4_vrmpyeh_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_lh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_lh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_vraddh :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">;<br class="">-<br class="">-def int_hexagon_C2_tfrrp :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_ll_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_ll_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;<br class="">-<br class="">-def int_hexagon_S2_vtrunowh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">;<br class="">-<br class="">-def int_hexagon_A2_abs :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">;<br class="">-<br class="">-def int_hexagon_A4_cmpbeq :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">;<br class="">-<br class="">-def int_hexagon_A2_negp :<br class="">-Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">;<br class="">-<br class="">-def int_hexagon_S2_asl_i_r_sat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A2_addh_l16_sat_hl :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;<br class="">-<br class="">-def int_hexagon_S2_vsatwuh :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">;<br class="">-<br class="">-def int_hexagon_F2_dfcmpgt :<br class="">-Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt">;<br class="">-<br class="">-def int_hexagon_S2_svsathb :<br class="">-Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">;<br class="">-<br class="">-def int_hexagon_C2_cmpgtup :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">;<br class="">-<br class="">-def int_hexagon_A4_cround_ri :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S4_clbpaddi :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_cround_rr :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">;<br class="">-<br class="">-def int_hexagon_C2_mux :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">;<br class="">-<br class="">-def int_hexagon_M2_dpmpyuu_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;<br class="">-<br class="">-def int_hexagon_S2_shuffeb :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">;<br class="">-<br class="">-def int_hexagon_A2_vminuw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">;<br class="">-<br class="">-def int_hexagon_A2_vaddhs :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">;<br class="">-<br class="">-def int_hexagon_S2_insert_rp :<br class="">-Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">;<br class="">-<br class="">-def int_hexagon_A2_vminuh :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">;<br class="">-<br class="">-def int_hexagon_A2_vminub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">;<br class="">-<br class="">-def int_hexagon_S2_extractu :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [ImmArg<1>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A2_svsubh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">;<br class="">-<br class="">-def int_hexagon_S4_clbaddi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_F2_sffms :<br class="">-Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms">;<br class="">-<br class="">-def int_hexagon_S2_vsxtbh :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_ll_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_ll_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;<br class="">-<br class="">-def int_hexagon_A2_subp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2es_s1 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2es_s0 :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;<br class="">-<br class="">-def int_hexagon_S4_parity :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_hh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_hh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;<br class="">-<br class="">-def int_hexagon_S4_addi_asl_ri :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [ImmArg<0>, ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_hh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyd_nac_hh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A4_cmpheqi :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_r_p_xor :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_hl_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_hl_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;<br class="">-<br class="">-def int_hexagon_F2_conv_sf2ud_chop :<br class="">-Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;<br class="">-<br class="">-def int_hexagon_C2_cmpgeui :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_hh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_acc_sat_hh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;<br class="">-<br class="">-def int_hexagon_S2_asl_r_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_sat_lh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;<br class="">-<br class="">-def int_hexagon_A2_addh_h16_sat_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;<br class="">-<br class="">-def int_hexagon_M4_nac_up_s1_sat :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_lh_s1 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpyud_nac_lh_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;<br class="">-<br class="">-def int_hexagon_A4_round_ri_sat :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_hl_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_hl_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;<br class="">-<br class="">-def int_hexagon_A2_vavghcr :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">;<br class="">-<br class="">-def int_hexagon_M2_mmacls_rs0 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">;<br class="">-<br class="">-def int_hexagon_M2_mmacls_rs1 :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">;<br class="">-<br class="">-def int_hexagon_M2_cmaci_s0 :<br class="">-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">;<br class="">-<br class="">-def int_hexagon_S2_setbit_i :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_asl_i_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_A4_andn :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">;<br class="">-<br class="">-def int_hexagon_M5_vrmpybsu :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">;<br class="">-<br class="">-def int_hexagon_S2_vrndpackwh :<br class="">-Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">;<br class="">-<br class="">-def int_hexagon_M2_vcmac_s0_sat_r :<br class="">-Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;<br class="">-<br class="">-def int_hexagon_A2_vmaxuw :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">;<br class="">-<br class="">-def int_hexagon_C2_bitsclr :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">;<br class="">-<br class="">-def int_hexagon_M2_xor_xacc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">;<br class="">-<br class="">-def int_hexagon_A4_vcmpbgtui :<br class="">-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_A4_ornp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">;<br class="">-<br class="">-def int_hexagon_A2_tfrpi :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [ImmArg<0>]>;<br class="">-<br class="">-def int_hexagon_C4_and_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_hh_s1 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;<br class="">-<br class="">-def int_hexagon_M2_mpy_nac_sat_hh_s0 :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_sat_ll :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;<br class="">-<br class="">-def int_hexagon_A2_subh_h16_sat_lh :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2su_s1 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;<br class="">-<br class="">-def int_hexagon_M2_vmpy2su_s0 :<br class="">-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;<br class="">-<br class="">-def int_hexagon_S2_asr_i_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_C4_nbitsclri :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_vh :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S2_lsr_i_p_xacc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [ImmArg<2>]>;<br class="">-<br class="">-// V55 Scalar Instructions.<br class="">-<br class="">-def int_hexagon_A5_ACS :<br class="">-Hexagon_i64i32_i64i64i64_Intrinsic<"HEXAGON_A5_ACS">;<br class="">-<br class="">-// V60 Scalar Instructions.<br class="">-<br class="">-def int_hexagon_S6_rol_i_p_and :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_r_xacc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_r_and :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_r_acc :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_p_xacc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_p :<br class="">-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_p_nac :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_p_acc :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_r_or :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_r :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [ImmArg<1>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_r_nac :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_S6_rol_i_p_or :<br class="">-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [ImmArg<2>]>;<br class="">-<br class="">-// V62 Scalar Instructions.<br class="">-<br class="">-def int_hexagon_S6_vtrunehb_ppp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;<br class="">-<br class="">-def int_hexagon_V6_ldntnt0 :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldntnt0">;<br class="">-<br class="">-def int_hexagon_M6_vabs<br class="">diff ub :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabs<br class="">diff ub">;<br class="">-<br class="">-def int_hexagon_S6_vtrunohb_ppp :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;<br class="">-<br class="">-def int_hexagon_M6_vabs<br class="">diff b :<br class="">-Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabs<br class="">diff b">;<br class="">-<br class="">-def int_hexagon_A6_vminub_RdP :<br class="">-Hexagon_i64i32_i64i64_Intrinsic<"HEXAGON_A6_vminub_RdP">;<br class="">-<br class="">-def int_hexagon_S6_vsplatrbp :<br class="">-Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">;<br class="">-<br class="">-// V65 Scalar Instructions.<br class="">-<br class="">-def int_hexagon_A6_vcmpbeq_notany :<br class="">-Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;<br class="">-<br class="">-// V66 Scalar Instructions.<br class="">-<br class="">-def int_hexagon_F2_dfsub :<br class="">-Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub">;<br class="">-<br class="">-def int_hexagon_F2_dfadd :<br class="">-Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd">;<br class="">-<br class="">-def int_hexagon_M2_mnaci :<br class="">-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">;<br class="">-<br class="">-def int_hexagon_S2_mask :<br class="">-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [ImmArg<0>, ImmArg<1>]>;<br class="">-<br class="">-// V60 HVX Instructions.<br class="">-<br class="">-def int_hexagon_V6_veqb_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">;<br class="">-<br class="">-def int_hexagon_V6_veqb_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vminub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">;<br class="">-<br class="">-def int_hexagon_V6_vminub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaslw_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">;<br class="">-<br class="">-def int_hexagon_V6_vaslw_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhvsrs :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhvsrs_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsathub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">;<br class="">-<br class="">-def int_hexagon_V6_vsathub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddh_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddh_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusi :<br class="">-Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusi_128B :<br class="">-Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vshufoh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">;<br class="">-<br class="">-def int_hexagon_V6_vshufoh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrwv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">;<br class="">-<br class="">-def int_hexagon_V6_vasrwv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsuisat :<br class="">-Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsuisat_128B :<br class="">-Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrsadubi_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vrsadubi_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vnavgw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">;<br class="">-<br class="">-def int_hexagon_V6_vnavgw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vnavgh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">;<br class="">-<br class="">-def int_hexagon_V6_vnavgh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">;<br class="">-<br class="">-def int_hexagon_V6_vavgub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">;<br class="">-<br class="">-def int_hexagon_V6_vsubb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgubrnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">;<br class="">-<br class="">-def int_hexagon_V6_vavgubrnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubbnq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">;<br class="">-<br class="">-def int_hexagon_V6_vsubbnq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vroundhb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">;<br class="">-<br class="">-def int_hexagon_V6_vroundhb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vadduhsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vadduhsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsububsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">;<br class="">-<br class="">-def int_hexagon_V6_vsububsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpabus_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpabus_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmux :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">;<br class="">-<br class="">-def int_hexagon_V6_vmux_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhus :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhus_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackeb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">;<br class="">-<br class="">-def int_hexagon_V6_vpackeb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubhnq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">;<br class="">-<br class="">-def int_hexagon_V6_vsubhnq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavghrnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">;<br class="">-<br class="">-def int_hexagon_V6_vavghrnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtran2x2_map :<br class="">-Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map">;<br class="">-<br class="">-def int_hexagon_V6_vtran2x2_map_128B :<br class="">-Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdelta :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">;<br class="">-<br class="">-def int_hexagon_V6_vdelta_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyhb :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyhb_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackob :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">;<br class="">-<br class="">-def int_hexagon_V6_vpackob_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmaxh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">;<br class="">-<br class="">-def int_hexagon_V6_vmaxh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtmpybus_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;<br class="">-<br class="">-def int_hexagon_V6_vtmpybus_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubuhsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">;<br class="">-<br class="">-def int_hexagon_V6_vsubuhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrw_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">;<br class="">-<br class="">-def int_hexagon_V6_vasrw_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_or :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or">;<br class="">-<br class="">-def int_hexagon_V6_pred_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_lo :<br class="">-Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">;<br class="">-<br class="">-def int_hexagon_V6_lo_128B :<br class="">-Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubb_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubb_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubhsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubhsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwh :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwh_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwb :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwb_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldu0 :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldu0">;<br class="">-<br class="">-def int_hexagon_V6_ldu0_128B :<br class="">-Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldu0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgth_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">;<br class="">-<br class="">-def int_hexagon_V6_vgth_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">;<br class="">-<br class="">-def int_hexagon_V6_vavgh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlalignb :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">;<br class="">-<br class="">-def int_hexagon_V6_vlalignb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsh :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">;<br class="">-<br class="">-def int_hexagon_V6_vsh_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_and_n :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and_n">;<br class="">-<br class="">-def int_hexagon_V6_pred_and_n_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsb :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">;<br class="">-<br class="">-def int_hexagon_V6_vsb_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vroundwuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">;<br class="">-<br class="">-def int_hexagon_V6_vroundwuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrhv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">;<br class="">-<br class="">-def int_hexagon_V6_vasrhv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshuffh :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">;<br class="">-<br class="">-def int_hexagon_V6_vshuffh_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddhsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddhsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vnavgub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">;<br class="">-<br class="">-def int_hexagon_V6_vnavgub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vnormamth :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">;<br class="">-<br class="">-def int_hexagon_V6_vnormamth_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavguh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">;<br class="">-<br class="">-def int_hexagon_V6_vavguh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlsrwv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">;<br class="">-<br class="">-def int_hexagon_V6_vlsrwv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlsrhv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">;<br class="">-<br class="">-def int_hexagon_V6_vlsrhv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhisat :<br class="">-Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhisat_128B :<br class="">-Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhvsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhvsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">;<br class="">-<br class="">-def int_hexagon_V6_vaddw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vzh :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">;<br class="">-<br class="">-def int_hexagon_V6_vzh_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">;<br class="">-<br class="">-def int_hexagon_V6_vaddh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmaxub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">;<br class="">-<br class="">-def int_hexagon_V6_vmaxub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhv_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vadduhsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">;<br class="">-<br class="">-def int_hexagon_V6_vadduhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshufoeh :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">;<br class="">-<br class="">-def int_hexagon_V6_vshufoeh_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhv_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqh :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">;<br class="">-<br class="">-def int_hexagon_V6_veqh_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpabuuv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">;<br class="">-<br class="">-def int_hexagon_V6_vmpabuuv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrwhsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrwhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vminuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">;<br class="">-<br class="">-def int_hexagon_V6_vminuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vror :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">;<br class="">-<br class="">-def int_hexagon_V6_vror_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_rnd_sacc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_rnd_sacc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmaxuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">;<br class="">-<br class="">-def int_hexagon_V6_vmaxuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabsh_sat :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">;<br class="">-<br class="">-def int_hexagon_V6_vabsh_sat_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_or_n :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or_n">;<br class="">-<br class="">-def int_hexagon_V6_pred_or_n_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdealb :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">;<br class="">-<br class="">-def int_hexagon_V6_vdealb_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpybusv :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">;<br class="">-<br class="">-def int_hexagon_V6_vmpybusv_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vzb :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">;<br class="">-<br class="">-def int_hexagon_V6_vzb_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_dv :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_dv_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddbq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">;<br class="">-<br class="">-def int_hexagon_V6_vaddbq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">;<br class="">-<br class="">-def int_hexagon_V6_vaddb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddwq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">;<br class="">-<br class="">-def int_hexagon_V6_vaddwq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrhubrndsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrhubrndsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrhubsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrhubsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshufoeb :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">;<br class="">-<br class="">-def int_hexagon_V6_vshufoeb_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackhub_sat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">;<br class="">-<br class="">-def int_hexagon_V6_vpackhub_sat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwh_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwh_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyb :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyb_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpabusv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">;<br class="">-<br class="">-def int_hexagon_V6_vmpabusv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_and :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and">;<br class="">-<br class="">-def int_hexagon_V6_pred_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubwnq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">;<br class="">-<br class="">-def int_hexagon_V6_vsubwnq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackwuh_sat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;<br class="">-<br class="">-def int_hexagon_V6_vpackwuh_sat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vswap :<br class="">-Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">;<br class="">-<br class="">-def int_hexagon_V6_vswap_128B :<br class="">-Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubv_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubv_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaslw :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">;<br class="">-<br class="">-def int_hexagon_V6_vaslw_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackhb_sat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">;<br class="">-<br class="">-def int_hexagon_V6_vpackhb_sat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyih_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyih_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshuffvdd :<br class="">-Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">;<br class="">-<br class="">-def int_hexagon_V6_vshuffvdd_128B :<br class="">-Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddb_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddb_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vunpackub :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">;<br class="">-<br class="">-def int_hexagon_V6_vunpackub_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh :<br class="">-Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_128B :<br class="">-Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtub :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyieoh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyieoh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;<br class="">-<br class="">-def int_hexagon_V6_extractw :<br class="">-Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">;<br class="">-<br class="">-def int_hexagon_V6_extractw_128B :<br class="">-Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgwrnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">;<br class="">-<br class="">-def int_hexagon_V6_vavgwrnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsat_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsat_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyub :<br class="">-Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">;<br class="">-<br class="">-def int_hexagon_V6_vmpyub_128B :<br class="">-Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuh :<br class="">-Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuh_128B :<br class="">-Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vunpackob :<br class="">-Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">;<br class="">-<br class="">-def int_hexagon_V6_vunpackob_128B :<br class="">-Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpahb :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">;<br class="">-<br class="">-def int_hexagon_V6_vmpahb_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqw_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">;<br class="">-<br class="">-def int_hexagon_V6_veqw_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandqrt :<br class="">-Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt">;<br class="">-<br class="">-def int_hexagon_V6_vandqrt_128B :<br class="">-Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">;<br class="">-<br class="">-def int_hexagon_V6_vxor :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">;<br class="">-<br class="">-def int_hexagon_V6_vxor_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrwhrndsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrwhrndsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhsat_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhsat_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybus_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybus_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubhw :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">;<br class="">-<br class="">-def int_hexagon_V6_vsubhw_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdealb4w :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">;<br class="">-<br class="">-def int_hexagon_V6_vdealb4w_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_sacc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_sacc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpybv :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">;<br class="">-<br class="">-def int_hexagon_V6_vmpybv_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff h :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff h">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff h_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff h_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshuffob :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">;<br class="">-<br class="">-def int_hexagon_V6_vshuffob_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyub_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyub_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vnormamtw :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">;<br class="">-<br class="">-def int_hexagon_V6_vnormamtw_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vunpackuh :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">;<br class="">-<br class="">-def int_hexagon_V6_vunpackuh_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiewuh_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiewuh_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vunpackoh :<br class="">-Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">;<br class="">-<br class="">-def int_hexagon_V6_vunpackoh_128B :<br class="">-Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsat :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsat_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyubv :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">;<br class="">-<br class="">-def int_hexagon_V6_vmpyubv_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhss :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhss_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;<br class="">-<br class="">-def int_hexagon_V6_hi :<br class="">-Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">;<br class="">-<br class="">-def int_hexagon_V6_hi_128B :<br class="">-Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrwuhsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrwuhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqw :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">;<br class="">-<br class="">-def int_hexagon_V6_veqw_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdsaduh :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">;<br class="">-<br class="">-def int_hexagon_V6_vdsaduh_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">;<br class="">-<br class="">-def int_hexagon_V6_vsubw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubw_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubw_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqb_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">;<br class="">-<br class="">-def int_hexagon_V6_veqb_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyih :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">;<br class="">-<br class="">-def int_hexagon_V6_vmpyih_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyb_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyb_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybus :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybus_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpybus_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpybus_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgth_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">;<br class="">-<br class="">-def int_hexagon_V6_vgth_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubhsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">;<br class="">-<br class="">-def int_hexagon_V6_vsubhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubi_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubi_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vabsw :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">;<br class="">-<br class="">-def int_hexagon_V6_vabsw_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddwsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddwsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlsrw :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">;<br class="">-<br class="">-def int_hexagon_V6_vlsrw_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabsh :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">;<br class="">-<br class="">-def int_hexagon_V6_vabsh_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlsrh :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">;<br class="">-<br class="">-def int_hexagon_V6_vlsrh_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">;<br class="">-<br class="">-def int_hexagon_V6_valignb :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">;<br class="">-<br class="">-def int_hexagon_V6_valignb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubhq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">;<br class="">-<br class="">-def int_hexagon_V6_vsubhq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackoh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">;<br class="">-<br class="">-def int_hexagon_V6_vpackoh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhvsat_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhvsat_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybv_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybv_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddhsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">;<br class="">-<br class="">-def int_hexagon_V6_vaddhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vcombine :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">;<br class="">-<br class="">-def int_hexagon_V6_vcombine_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandqrt_acc :<br class="">-Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">;<br class="">-<br class="">-def int_hexagon_V6_vandqrt_acc_128B :<br class="">-Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaslhv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">;<br class="">-<br class="">-def int_hexagon_V6_vaslhv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vinsertwr :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">;<br class="">-<br class="">-def int_hexagon_V6_vinsertwr_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubh_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubh_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshuffb :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">;<br class="">-<br class="">-def int_hexagon_V6_vshuffb_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vand :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">;<br class="">-<br class="">-def int_hexagon_V6_vand_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhv :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhv_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsuisat_acc :<br class="">-Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsuisat_acc_128B :<br class="">-Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsububsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsububsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdsaduh_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdsaduh_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuh_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuh_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vcl0h :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">;<br class="">-<br class="">-def int_hexagon_V6_vcl0h_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhus_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhus_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpybv_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpybv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrsadubi :<br class="">-Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vrsadubi_128B :<br class="">-Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_dv_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_dv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshufeh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">;<br class="">-<br class="">-def int_hexagon_V6_vshufeh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyewuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyewuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhsrs :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">;<br class="">-<br class="">-def int_hexagon_V6_vmpyhsrs_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_dv_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_dv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddubh :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">;<br class="">-<br class="">-def int_hexagon_V6_vaddubh_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrwh :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">;<br class="">-<br class="">-def int_hexagon_V6_vasrwh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">;<br class="">-<br class="">-def int_hexagon_V6_ld0 :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ld0">;<br class="">-<br class="">-def int_hexagon_V6_ld0_128B :<br class="">-Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ld0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpopcounth :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">;<br class="">-<br class="">-def int_hexagon_V6_vpopcounth_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldnt0 :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldnt0_128B :<br class="">-Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgth_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">;<br class="">-<br class="">-def int_hexagon_V6_vgth_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddubsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddubsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackeh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">;<br class="">-<br class="">-def int_hexagon_V6_vpackeh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyh :<br class="">-Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyh_128B :<br class="">-Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vminh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">;<br class="">-<br class="">-def int_hexagon_V6_vminh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_scalar2 :<br class="">-Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">;<br class="">-<br class="">-def int_hexagon_V6_pred_scalar2_128B :<br class="">-Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdealh :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">;<br class="">-<br class="">-def int_hexagon_V6_vdealh_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vpackwh_sat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">;<br class="">-<br class="">-def int_hexagon_V6_vpackwh_sat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaslh :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">;<br class="">-<br class="">-def int_hexagon_V6_vaslh_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vor :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">;<br class="">-<br class="">-def int_hexagon_V6_vor_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiowh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiowh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_oracc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_oracc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandvrt :<br class="">-Hexagon_v512i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">;<br class="">-<br class="">-def int_hexagon_V6_vandvrt_128B :<br class="">-Hexagon_v1024i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqh_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">;<br class="">-<br class="">-def int_hexagon_V6_veqh_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vadduhw :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">;<br class="">-<br class="">-def int_hexagon_V6_vadduhw_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vcl0w :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">;<br class="">-<br class="">-def int_hexagon_V6_vcl0w_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyihb :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">;<br class="">-<br class="">-def int_hexagon_V6_vmpyihb_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtmpybus :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">;<br class="">-<br class="">-def int_hexagon_V6_vtmpybus_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;<br class="">-<br class="">-def int_hexagon_V6_vd0 :<br class="">-Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">;<br class="">-<br class="">-def int_hexagon_V6_vd0_128B :<br class="">-Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqh_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">;<br class="">-<br class="">-def int_hexagon_V6_veqh_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">;<br class="">-<br class="">-def int_hexagon_V6_vdmpybus_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpybus :<br class="">-Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">;<br class="">-<br class="">-def int_hexagon_V6_vmpybus_128B :<br class="">-Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandvrt_acc :<br class="">-Hexagon_v512i1_v512i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">;<br class="">-<br class="">-def int_hexagon_V6_vandvrt_acc_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vassign :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">;<br class="">-<br class="">-def int_hexagon_V6_vassign_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddwnq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">;<br class="">-<br class="">-def int_hexagon_V6_vaddwnq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">;<br class="">-<br class="">-def int_hexagon_V6_vgtub_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_dv :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhb_dv_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vunpackb :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">;<br class="">-<br class="">-def int_hexagon_V6_vunpackb_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vunpackh :<br class="">-Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">;<br class="">-<br class="">-def int_hexagon_V6_vunpackh_128B :<br class="">-Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpahb_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpahb_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddbnq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">;<br class="">-<br class="">-def int_hexagon_V6_vaddbnq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlalignbi :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vlalignbi_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vsatwh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">;<br class="">-<br class="">-def int_hexagon_V6_vsatwh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">;<br class="">-<br class="">-def int_hexagon_V6_vgtuh_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyihb_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyihb_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusv_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusv_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrdelta :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">;<br class="">-<br class="">-def int_hexagon_V6_vrdelta_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">;<br class="">-<br class="">-def int_hexagon_V6_vroundwh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">;<br class="">-<br class="">-def int_hexagon_V6_vroundwh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddw_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddw_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwb_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwb_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubbq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">;<br class="">-<br class="">-def int_hexagon_V6_vsubbq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqh_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">;<br class="">-<br class="">-def int_hexagon_V6_veqh_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_valignbi :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_valignbi_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vaddwsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">;<br class="">-<br class="">-def int_hexagon_V6_vaddwsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqw_and :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">;<br class="">-<br class="">-def int_hexagon_V6_veqw_and_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff ub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff ub">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff ub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff ub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vshuffeb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">;<br class="">-<br class="">-def int_hexagon_V6_vshuffeb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff uh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff uh">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff uh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff uh_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqw_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">;<br class="">-<br class="">-def int_hexagon_V6_veqw_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgth :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">;<br class="">-<br class="">-def int_hexagon_V6_vgth_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtb :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtw :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubwq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">;<br class="">-<br class="">-def int_hexagon_V6_vsubwq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vnot :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">;<br class="">-<br class="">-def int_hexagon_V6_vnot_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">;<br class="">-<br class="">-def int_hexagon_V6_vgtb_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_or :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">;<br class="">-<br class="">-def int_hexagon_V6_vgtuw_or_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddubsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">;<br class="">-<br class="">-def int_hexagon_V6_vaddubsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmaxw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">;<br class="">-<br class="">-def int_hexagon_V6_vmaxw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaslwv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">;<br class="">-<br class="">-def int_hexagon_V6_vaslwv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabsw_sat :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">;<br class="">-<br class="">-def int_hexagon_V6_vabsw_sat_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubwsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubwsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vroundhub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">;<br class="">-<br class="">-def int_hexagon_V6_vroundhub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhisat_acc :<br class="">-Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhisat_acc_128B :<br class="">-Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpabus :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">;<br class="">-<br class="">-def int_hexagon_V6_vmpabus_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">;<br class="">-<br class="">-def int_hexagon_V6_vassignp :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">;<br class="">-<br class="">-def int_hexagon_V6_vassignp_128B :<br class="">-Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqb :<br class="">-Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">;<br class="">-<br class="">-def int_hexagon_V6_veqb_128B :<br class="">-Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsububh :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">;<br class="">-<br class="">-def int_hexagon_V6_vsububh_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">;<br class="">-<br class="">-def int_hexagon_V6_lvsplatw :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">;<br class="">-<br class="">-def int_hexagon_V6_lvsplatw_128B :<br class="">-Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddhnq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">;<br class="">-<br class="">-def int_hexagon_V6_vaddhnq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsusat :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsusat_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_not :<br class="">-Hexagon_v512i1_v512i1_Intrinsic<"HEXAGON_V6_pred_not">;<br class="">-<br class="">-def int_hexagon_V6_pred_not_128B :<br class="">-Hexagon_v1024i1_v1024i1_Intrinsic<"HEXAGON_V6_pred_not_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_oracc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_oracc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiewh_acc :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiewh_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdealvdd :<br class="">-Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">;<br class="">-<br class="">-def int_hexagon_V6_vdealvdd_128B :<br class="">-Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">;<br class="">-<br class="">-def int_hexagon_V6_vavgw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsusat_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;<br class="">-<br class="">-def int_hexagon_V6_vdmpyhsusat_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">;<br class="">-<br class="">-def int_hexagon_V6_vgtw_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyhb_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vtmpyhb_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddhw :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">;<br class="">-<br class="">-def int_hexagon_V6_vaddhw_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddhq :<br class="">-Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">;<br class="">-<br class="">-def int_hexagon_V6_vaddhq_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubv :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubv_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">;<br class="">-<br class="">-def int_hexagon_V6_vsubh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubi :<br class="">-Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vrmpyubi_128B :<br class="">-Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vminw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">;<br class="">-<br class="">-def int_hexagon_V6_vminw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyubv_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyubv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_xor :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_xor">;<br class="">-<br class="">-def int_hexagon_V6_pred_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_veqb_xor :<br class="">-Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">;<br class="">-<br class="">-def int_hexagon_V6_veqb_xor_128B :<br class="">-Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiewuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiewuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpybusv_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpybusv_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavguhrnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">;<br class="">-<br class="">-def int_hexagon_V6_vavguhrnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_rnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_rnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubwsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">;<br class="">-<br class="">-def int_hexagon_V6_vsubwsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubuhw :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">;<br class="">-<br class="">-def int_hexagon_V6_vsubuhw_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusi_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vrmpybusi_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vasrw :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">;<br class="">-<br class="">-def int_hexagon_V6_vasrw_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrh :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">;<br class="">-<br class="">-def int_hexagon_V6_vasrh_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhv :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhv_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrhbrndsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrhbrndsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubuhsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubuhsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff w :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff w">;<br class="">-<br class="">-def int_hexagon_V6_vabs<br class="">diff w_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff w_128B">;<br class="">-<br class="">-// V62 HVX Instructions.<br class="">-<br class="">-def int_hexagon_V6_vandnqrt_acc :<br class="">-Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;<br class="">-<br class="">-def int_hexagon_V6_vandnqrt_acc_128B :<br class="">-Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddclbh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">;<br class="">-<br class="">-def int_hexagon_V6_vaddclbh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_64_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyowh_64_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyewuh_64 :<br class="">-Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;<br class="">-<br class="">-def int_hexagon_V6_vmpyewuh_64_128B :<br class="">-Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsatuwuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">;<br class="">-<br class="">-def int_hexagon_V6_vsatuwuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_shuffeqh :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqh">;<br class="">-<br class="">-def int_hexagon_V6_shuffeqh_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;<br class="">-<br class="">-def int_hexagon_V6_shuffeqw :<br class="">-Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqw">;<br class="">-<br class="">-def int_hexagon_V6_shuffeqw_128B :<br class="">-Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldcnpnt0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldcnpnt0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubcarry :<br class="">-Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;<br class="">-<br class="">-def int_hexagon_V6_vsubcarry_128B :<br class="">-Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;<br class="">-<br class="">-def int_hexagon_V6_vasrhbsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrhbsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vminb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">;<br class="">-<br class="">-def int_hexagon_V6_vminb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpauhb_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpauhb_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddhw_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">;<br class="">-<br class="">-def int_hexagon_V6_vaddhw_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlsrb :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">;<br class="">-<br class="">-def int_hexagon_V6_vlsrb_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwhi :<br class="">-Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vlutvwhi_128B :<br class="">-Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vaddububb_sat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">;<br class="">-<br class="">-def int_hexagon_V6_vaddububb_sat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubbsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubbsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldtp0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0">;<br class="">-<br class="">-def int_hexagon_V6_ldtp0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_oracci :<br class="">-Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_oracci_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vsubuwsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vsubuwsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldpnt0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldpnt0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandvnqv :<br class="">-Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">;<br class="">-<br class="">-def int_hexagon_V6_vandvnqv_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;<br class="">-<br class="">-def int_hexagon_V6_lvsplatb :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">;<br class="">-<br class="">-def int_hexagon_V6_lvsplatb_128B :<br class="">-Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;<br class="">-<br class="">-def int_hexagon_V6_lvsplath :<br class="">-Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">;<br class="">-<br class="">-def int_hexagon_V6_lvsplath_128B :<br class="">-Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldtpnt0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldtpnt0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_nm :<br class="">-Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_nm_128B :<br class="">-Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldnpnt0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldnpnt0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpauhb :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">;<br class="">-<br class="">-def int_hexagon_V6_vmpauhb_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldtnp0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0">;<br class="">-<br class="">-def int_hexagon_V6_ldtnp0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrounduhub :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">;<br class="">-<br class="">-def int_hexagon_V6_vrounduhub_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vadduhw_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">;<br class="">-<br class="">-def int_hexagon_V6_vadduhw_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldcp0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0">;<br class="">-<br class="">-def int_hexagon_V6_ldcp0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vadduwsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">;<br class="">-<br class="">-def int_hexagon_V6_vadduwsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldtnpnt0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldtnpnt0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddbsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">;<br class="">-<br class="">-def int_hexagon_V6_vaddbsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandnqrt :<br class="">-Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">;<br class="">-<br class="">-def int_hexagon_V6_vandnqrt_128B :<br class="">-Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwub_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwub_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmaxb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">;<br class="">-<br class="">-def int_hexagon_V6_vmaxb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vandvqv :<br class="">-Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">;<br class="">-<br class="">-def int_hexagon_V6_vandvqv_128B :<br class="">-Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddcarry :<br class="">-Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;<br class="">-<br class="">-def int_hexagon_V6_vaddcarry_128B :<br class="">-Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;<br class="">-<br class="">-def int_hexagon_V6_vasrwuhrndsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;<br class="">-<br class="">-def int_hexagon_V6_vasrwuhrndsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvbi :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vlutvvbi_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [ImmArg<2>]>;<br class="">-<br class="">-def int_hexagon_V6_vsubuwsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">;<br class="">-<br class="">-def int_hexagon_V6_vsubuwsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddbsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vaddbsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldnp0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0">;<br class="">-<br class="">-def int_hexagon_V6_ldnp0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasruwuhrndsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;<br class="">-<br class="">-def int_hexagon_V6_vasruwuhrndsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrounduwuh :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">;<br class="">-<br class="">-def int_hexagon_V6_vrounduwuh_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_nm :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;<br class="">-<br class="">-def int_hexagon_V6_vlutvvb_nm_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;<br class="">-<br class="">-def int_hexagon_V6_pred_scalar2v2 :<br class="">-Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;<br class="">-<br class="">-def int_hexagon_V6_pred_scalar2v2_128B :<br class="">-Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldp0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0">;<br class="">-<br class="">-def int_hexagon_V6_ldp0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddubh_acc :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vaddubh_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaddclbw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">;<br class="">-<br class="">-def int_hexagon_V6_vaddclbw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldcpnt0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0">;<br class="">-<br class="">-def int_hexagon_V6_ldcpnt0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vadduwsat_dv :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;<br class="">-<br class="">-def int_hexagon_V6_vadduwsat_dv_128B :<br class="">-Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwub :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">;<br class="">-<br class="">-def int_hexagon_V6_vmpyiwub_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsubububb_sat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">;<br class="">-<br class="">-def int_hexagon_V6_vsubububb_sat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;<br class="">-<br class="">-def int_hexagon_V6_ldcnp0 :<br class="">-Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0">;<br class="">-<br class="">-def int_hexagon_V6_ldcnp0_128B :<br class="">-Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_oracci :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vlutvwh_oracci_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [ImmArg<3>]>;<br class="">-<br class="">-def int_hexagon_V6_vsubbsat :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">;<br class="">-<br class="">-def int_hexagon_V6_vsubbsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;<br class="">-<br class="">-// V65 HVX Instructions.<br class="">-<br class="">-def int_hexagon_V6_vasruhubrndsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;<br class="">-<br class="">-def int_hexagon_V6_vasruhubrndsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybub_rtt :<br class="">-Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybub_rtt_128B :<br class="">-Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpahhsat :<br class="">-Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">;<br class="">-<br class="">-def int_hexagon_V6_vmpahhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavguwrnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">;<br class="">-<br class="">-def int_hexagon_V6_vavguwrnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vnavgb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">;<br class="">-<br class="">-def int_hexagon_V6_vnavgb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasrh_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vasrh_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpauhuhsat :<br class="">-Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;<br class="">-<br class="">-def int_hexagon_V6_vmpauhuhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyh_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyh_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybub_rtt_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpybub_rtt_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgb :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">;<br class="">-<br class="">-def int_hexagon_V6_vavgb_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vaslh_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">;<br class="">-<br class="">-def int_hexagon_V6_vaslh_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavguw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">;<br class="">-<br class="">-def int_hexagon_V6_vavguw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vlut4 :<br class="">-Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">;<br class="">-<br class="">-def int_hexagon_V6_vlut4_128B :<br class="">-Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhe_acc :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhe_acc_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_rtt :<br class="">-Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_rtt_128B :<br class="">-Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpsuhuhsat :<br class="">-Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;<br class="">-<br class="">-def int_hexagon_V6_vmpsuhuhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasruhubsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">;<br class="">-<br class="">-def int_hexagon_V6_vasruhubsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhe :<br class="">-Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">;<br class="">-<br class="">-def int_hexagon_V6_vmpyuhe_128B :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_rtt_acc :<br class="">-Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;<br class="">-<br class="">-def int_hexagon_V6_vrmpyub_rtt_acc_128B :<br class="">-Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasruwuhsat :<br class="">-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">;<br class="">-<br class="">-def int_hexagon_V6_vasruwuhsat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpabuu_acc :<br class="">-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;<br class="">-<br class="">-def int_hexagon_V6_vmpabuu_acc_128B :<br class="">-Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;<br class="">-<br class="">-def int_hexagon_V6_vprefixqw :<br class="">-Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqw">;<br class="">-<br class="">-def int_hexagon_V6_vprefixqw_128B :<br class="">-Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vprefixqh :<br class="">-Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqh">;<br class="">-<br class="">-def int_hexagon_V6_vprefixqh_128B :<br class="">-Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;<br class="">-<br class="">-def int_hexagon_V6_vprefixqb :<br class="">-Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqb">;<br class="">-<br class="">-def int_hexagon_V6_vprefixqb_128B :<br class="">-Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabsb :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">;<br class="">-<br class="">-def int_hexagon_V6_vabsb_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">;<br class="">-<br class="">-def int_hexagon_V6_vavgbrnd :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">;<br class="">-<br class="">-def int_hexagon_V6_vavgbrnd_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;<br class="">-<br class="">-def int_hexagon_V6_vdd0 :<br class="">-Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">;<br class="">-<br class="">-def int_hexagon_V6_vdd0_128B :<br class="">-Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">;<br class="">-<br class="">-def int_hexagon_V6_vmpabuu :<br class="">-Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">;<br class="">-<br class="">-def int_hexagon_V6_vmpabuu_128B :<br class="">-Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;<br class="">-<br class="">-def int_hexagon_V6_vabsb_sat :<br class="">-Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">;<br class="">-<br class="">-def int_hexagon_V6_vabsb_sat_128B :<br class="">-Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;<br class="">-<br class="">-// V66 HVX Instructions.<br class="">-<br class="">-def int_hexagon_V6_vaddcarrysat :<br class="">-Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">;<br class="">-<br class="">-def int_hexagon_V6_vaddcarrysat_128B :<br class="">-Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">;<br class="">-<br class="">-def int_hexagon_V6_vasr_into :<br class="">-Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">;<br class="">-<br class="">-def int_hexagon_V6_vasr_into_128B :<br class="">-Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">;<br class="">-<br class="">-def int_hexagon_V6_vsatdw :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">;<br class="">-<br class="">-def int_hexagon_V6_vsatdw_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">;<br class="">-<br class="">-def int_hexagon_V6_vrotr :<br class="">-Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">;<br class="">-<br class="">-def int_hexagon_V6_vrotr_128B :<br class="">-Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">;<br class="">-<br class="">+include "llvm/IR/IntrinsicsHexagonDep.td"<br class=""><br class="">diff --git a/llvm/include/llvm/IR/IntrinsicsHexagonDep.td b/llvm/include/llvm/IR/IntrinsicsHexagonDep.td<br class="">new file mode 100644<br class="">index 000000000000..bf0f6ad78eec<br class="">--- /dev/null<br class="">+++ b/llvm/include/llvm/IR/IntrinsicsHexagonDep.td<br class="">@@ -0,0 +1,6058 @@<br class="">+//===----------------------------------------------------------------------===//<br class="">+//<br class="">+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.<br class="">+// See <a href="https://llvm.org/LICENSE.txt" class="">https://llvm.org/LICENSE.txt</a> for license information.<br class="">+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception<br class="">+//<br class="">+//===----------------------------------------------------------------------===//<br class="">+// Automatically generated file, do not edit!<br class="">+//===----------------------------------------------------------------------===//<br class="">+<br class="">+// tag : C2_cmpeq<br class="">+class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : C2_cmpeqp<br class="">+class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : C2_not<br class="">+class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : C4_and_and<br class="">+class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : C2_vmux<br class="">+class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : C2_mask<br class="">+class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : A4_vcmpbeqi<br class="">+class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : A4_boundscheck<br class="">+class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : M2_mpyd_acc_hh_s0<br class="">+class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : M2_mpyd_hh_s0<br class="">+class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : M2_vmpy2es_s0<br class="">+class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : M2_vmac2es_s0<br class="">+class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : M2_vrcmpys_s1<br class="">+class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : M2_vrcmpys_acc_s1<br class="">+class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : S4_vrcrotate_acc<br class="">+class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : A2_addsp<br class="">+class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : A2_vconj<br class="">+class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : A2_sat<br class="">+class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sfadd<br class="">+class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_float_ty,llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sffma<br class="">+class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sffma_sc<br class="">+class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sfcmpeq<br class="">+class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_float_ty,llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sfclass<br class="">+class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sfimm_p<br class="">+class Hexagon_float_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_sffixupr<br class="">+class Hexagon_float_float_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_dfadd<br class="">+class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_double_ty], [llvm_double_ty,llvm_double_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_dfmpylh<br class="">+class Hexagon_double_doubledoubledouble_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_double_ty], [llvm_double_ty,llvm_double_ty,llvm_double_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_dfcmpeq<br class="">+class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_double_ty,llvm_double_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_dfclass<br class="">+class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_dfimm_p<br class="">+class Hexagon_double_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_double_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_sf2df<br class="">+class Hexagon_double_float_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_double_ty], [llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_df2sf<br class="">+class Hexagon_float_double_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_double_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_ud2sf<br class="">+class Hexagon_float_i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_float_ty], [llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_ud2df<br class="">+class Hexagon_double_i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_double_ty], [llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_sf2uw<br class="">+class Hexagon_i32_float_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_sf2ud<br class="">+class Hexagon_i64_float_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_float_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_df2uw<br class="">+class Hexagon_i32_double_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_double_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : F2_conv_df2ud<br class="">+class Hexagon_i64_double_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_double_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : S2_insert<br class="">+class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : S2_insert_rp<br class="">+class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : Y2_dcfetch<br class="">+class Hexagon__ptr_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : Y4_l2fetch<br class="">+class Hexagon__ptri32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : Y5_l2fetch<br class="">+class Hexagon__ptri64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32__Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32__Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_i64_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i64_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v4i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v4i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v4i32_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v4i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v4i32v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v4i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v8i32v64i32v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v8i32_ty,llvm_v64i32_ty,llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v64i32v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32v4i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v4i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag :<br class="">+class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vS32b_qpred_ai<br class="">+class Hexagon__v512i1ptrv16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vS32b_qpred_ai<br class="">+class Hexagon__v1024i1ptrv32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_valignb<br class="">+class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vror<br class="">+class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vunpackub<br class="">+class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vunpackob<br class="">+class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vpackeb<br class="">+class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vdmpyhvsat_acc<br class="">+class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vdmpyhisat<br class="">+class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vdmpyhisat_acc<br class="">+class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vdmpyhisat_acc<br class="">+class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vrmpyubi<br class="">+class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vrmpyubi<br class="">+class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vrmpyubi_acc<br class="">+class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vrmpyubi_acc<br class="">+class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vasr_into<br class="">+class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddcarrysat<br class="">+class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddcarrysat<br class="">+class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddcarry<br class="">+class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic<<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_NonGCC_Intrinsic<<br class="">+ [llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddcarry<br class="">+class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B<<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_NonGCC_Intrinsic<<br class="">+ [llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddubh<br class="">+class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vd0<br class="">+class Hexagon_v16i32__Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddbq<br class="">+class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vaddbq<br class="">+class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vabsb<br class="">+class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vmpyub<br class="">+class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vmpyub<br class="">+class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vmpyub_acc<br class="">+class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vmpyub_acc<br class="">+class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandqrt<br class="">+class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandqrt<br class="">+class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandqrt_acc<br class="">+class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandqrt_acc<br class="">+class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandvrt<br class="">+class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandvrt<br class="">+class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandvrt_acc<br class="">+class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandvrt_acc<br class="">+class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandvqv<br class="">+class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vandvqv<br class="">+class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgtw<br class="">+class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgtw<br class="">+class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgtw_and<br class="">+class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgtw_and<br class="">+class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_pred_scalar2<br class="">+class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_pred_scalar2<br class="">+class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_shuffeqw<br class="">+class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_shuffeqw<br class="">+class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_pred_not<br class="">+class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v512i1_ty], [llvm_v512i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_pred_not<br class="">+class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v1024i1_ty], [llvm_v1024i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vswap<br class="">+class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vswap<br class="">+class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vshuffvdd<br class="">+class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_extractw<br class="">+class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_lvsplatw<br class="">+class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vlutvvb_oracc<br class="">+class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vlutvwh_oracc<br class="">+class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vmpahhsat<br class="">+class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vlut4<br class="">+class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_hi<br class="">+class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermw<br class="">+class Hexagon__ptri32i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermw<br class="">+class Hexagon__ptri32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermhw<br class="">+class Hexagon__ptri32i32v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermwq<br class="">+class Hexagon__ptrv512i1i32i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermwq<br class="">+class Hexagon__ptrv1024i1i32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermhwq<br class="">+class Hexagon__ptrv512i1i32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vgathermhwq<br class="">+class Hexagon__ptrv1024i1i32i32v64i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermw<br class="">+class Hexagon__i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermw<br class="">+class Hexagon__i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermwq<br class="">+class Hexagon__v512i1i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_v512i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermwq<br class="">+class Hexagon__v1024i1i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_v1024i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermhw<br class="">+class Hexagon__i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermhw<br class="">+class Hexagon__i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermhwq<br class="">+class Hexagon__v512i1i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_v512i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vscattermhwq<br class="">+class Hexagon__v1024i1i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [], [llvm_v1024i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vprefixqb<br class="">+class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v16i32_ty], [llvm_v512i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// tag : V6_vprefixqb<br class="">+class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix,<br class="">+ list<IntrinsicProperty> intr_properties = [IntrNoMem]><br class="">+ : Hexagon_Intrinsic<GCCIntSuffix,<br class="">+ [llvm_v32i32_ty], [llvm_v1024i1_ty],<br class="">+ intr_properties>;<br class="">+<br class="">+// V5 Scalar Instructions.<br class="">+<br class="">+def int_hexagon_C2_cmpeq :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">;<br class="">+<br class="">+def int_hexagon_C2_cmpgt :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;<br class="">+<br class="">+def int_hexagon_C2_cmpgtu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;<br class="">+<br class="">+def int_hexagon_C2_cmpeqp :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;<br class="">+<br class="">+def int_hexagon_C2_cmpgtp :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;<br class="">+<br class="">+def int_hexagon_C2_cmpgtup :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">;<br class="">+<br class="">+def int_hexagon_A4_rcmpeqi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_rcmpneqi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_rcmpeq :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;<br class="">+<br class="">+def int_hexagon_A4_rcmpneq :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">;<br class="">+<br class="">+def int_hexagon_C2_bitsset :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;<br class="">+<br class="">+def int_hexagon_C2_bitsclr :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">;<br class="">+<br class="">+def int_hexagon_C4_nbitsset :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;<br class="">+<br class="">+def int_hexagon_C4_nbitsclr :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">;<br class="">+<br class="">+def int_hexagon_C2_cmpeqi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C2_cmpgti :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C2_cmpgtui :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C2_cmpgei :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C2_cmpgeui :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C2_cmplt :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;<br class="">+<br class="">+def int_hexagon_C2_cmpltu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;<br class="">+<br class="">+def int_hexagon_C2_bitsclri :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C4_nbitsclri :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C4_cmpneqi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C4_cmpltei :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C4_cmplteui :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C4_cmpneq :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">;<br class="">+<br class="">+def int_hexagon_C4_cmplte :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">;<br class="">+<br class="">+def int_hexagon_C4_cmplteu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">;<br class="">+<br class="">+def int_hexagon_C2_and :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">;<br class="">+<br class="">+def int_hexagon_C2_or :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">;<br class="">+<br class="">+def int_hexagon_C2_xor :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">;<br class="">+<br class="">+def int_hexagon_C2_andn :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;<br class="">+<br class="">+def int_hexagon_C2_not :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">;<br class="">+<br class="">+def int_hexagon_C2_orn :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;<br class="">+<br class="">+def int_hexagon_C4_and_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">;<br class="">+<br class="">+def int_hexagon_C4_and_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">;<br class="">+<br class="">+def int_hexagon_C4_or_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">;<br class="">+<br class="">+def int_hexagon_C4_or_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">;<br class="">+<br class="">+def int_hexagon_C4_and_andn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">;<br class="">+<br class="">+def int_hexagon_C4_and_orn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;<br class="">+<br class="">+def int_hexagon_C4_or_andn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;<br class="">+<br class="">+def int_hexagon_C4_or_orn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">;<br class="">+<br class="">+def int_hexagon_C2_pxfer_map :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;<br class="">+<br class="">+def int_hexagon_C2_any8 :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;<br class="">+<br class="">+def int_hexagon_C2_all8 :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">;<br class="">+<br class="">+def int_hexagon_C2_vitpack :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">;<br class="">+<br class="">+def int_hexagon_C2_mux :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">;<br class="">+<br class="">+def int_hexagon_C2_muxii :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<1>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_C2_muxir :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_C2_muxri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_C2_vmux :<br class="">+Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;<br class="">+<br class="">+def int_hexagon_C2_mask :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">;<br class="">+<br class="">+def int_hexagon_A2_vcmpbeq :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">;<br class="">+<br class="">+def int_hexagon_A4_vcmpbeqi :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_vcmpbeq_any :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;<br class="">+<br class="">+def int_hexagon_A2_vcmpbgtu :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">;<br class="">+<br class="">+def int_hexagon_A4_vcmpbgtui :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_vcmpbgt :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">;<br class="">+<br class="">+def int_hexagon_A4_vcmpbgti :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cmpbeq :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">;<br class="">+<br class="">+def int_hexagon_A4_cmpbeqi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cmpbgtu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;<br class="">+<br class="">+def int_hexagon_A4_cmpbgtui :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cmpbgt :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;<br class="">+<br class="">+def int_hexagon_A4_cmpbgti :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_vcmpheq :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">;<br class="">+<br class="">+def int_hexagon_A2_vcmphgt :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">;<br class="">+<br class="">+def int_hexagon_A2_vcmphgtu :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;<br class="">+<br class="">+def int_hexagon_A4_vcmpheqi :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_vcmphgti :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_vcmphgtui :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cmpheq :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;<br class="">+<br class="">+def int_hexagon_A4_cmphgt :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">;<br class="">+<br class="">+def int_hexagon_A4_cmphgtu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;<br class="">+<br class="">+def int_hexagon_A4_cmpheqi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cmphgti :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cmphgtui :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_vcmpweq :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">;<br class="">+<br class="">+def int_hexagon_A2_vcmpwgt :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">;<br class="">+<br class="">+def int_hexagon_A2_vcmpwgtu :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;<br class="">+<br class="">+def int_hexagon_A4_vcmpweqi :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_vcmpwgti :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_vcmpwgtui :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_boundscheck :<br class="">+Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;<br class="">+<br class="">+def int_hexagon_A4_tlbmatch :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">;<br class="">+<br class="">+def int_hexagon_C2_tfrpr :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">;<br class="">+<br class="">+def int_hexagon_C2_tfrrp :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">;<br class="">+<br class="">+def int_hexagon_C4_fastcorner9 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">;<br class="">+<br class="">+def int_hexagon_C4_fastcorner9_not :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_hh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_hh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_hl_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_hl_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_lh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_lh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_ll_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_ll_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_hh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_hh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_hl_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_hl_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_lh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_lh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_ll_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_ll_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_hh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_hh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_hl_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_hl_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_lh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_lh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_ll_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_acc_sat_ll_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_hh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_hh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_hl_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_hl_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_lh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_lh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_ll_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_nac_sat_ll_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_hh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_hh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_hl_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_hl_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_lh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_lh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_ll_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_ll_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_hh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_hh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_hl_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_hl_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_lh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_lh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_ll_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_ll_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_hh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_hh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_hl_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_hl_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_lh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_lh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_ll_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_rnd_ll_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_hh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_hh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_hl_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_hl_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_lh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_lh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_ll_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_sat_rnd_ll_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_hh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_hh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_hl_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_hl_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_lh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_lh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_ll_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_acc_ll_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_hh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_hh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_hl_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_hl_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_lh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_lh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_ll_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_nac_ll_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_hh_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_hh_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_hl_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_hl_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_lh_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_lh_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_ll_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_ll_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_hh_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_hh_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_hl_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_hl_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_lh_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_lh_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_ll_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyd_rnd_ll_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_hh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_hh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_hl_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_hl_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_lh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_lh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_ll_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_acc_ll_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_hh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_hh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_hl_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_hl_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_lh_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_lh_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_ll_s0 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_nac_ll_s1 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_hh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_hh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_hl_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_hl_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_lh_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_lh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_ll_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_ll_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_hh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_hh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_hl_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_hl_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_lh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_lh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_ll_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_acc_ll_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_hh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_hh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_hl_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_hl_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_lh_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_lh_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_ll_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_nac_ll_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_hh_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_hh_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_hl_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_hl_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_lh_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_lh_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_ll_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpyud_ll_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpysmi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_M2_macsip :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M2_macsin :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M2_dpmpyss_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;<br class="">+<br class="">+def int_hexagon_M2_dpmpyss_acc_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;<br class="">+<br class="">+def int_hexagon_M2_dpmpyss_nac_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;<br class="">+<br class="">+def int_hexagon_M2_dpmpyuu_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;<br class="">+<br class="">+def int_hexagon_M2_dpmpyuu_acc_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;<br class="">+<br class="">+def int_hexagon_M2_dpmpyuu_nac_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;<br class="">+<br class="">+def int_hexagon_M2_mpy_up :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;<br class="">+<br class="">+def int_hexagon_M2_mpy_up_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;<br class="">+<br class="">+def int_hexagon_M2_mpy_up_s1_sat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;<br class="">+<br class="">+def int_hexagon_M2_mpyu_up :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;<br class="">+<br class="">+def int_hexagon_M2_mpysu_up :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">;<br class="">+<br class="">+def int_hexagon_M2_dpmpyss_rnd_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;<br class="">+<br class="">+def int_hexagon_M4_mac_up_s1_sat :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;<br class="">+<br class="">+def int_hexagon_M4_nac_up_s1_sat :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;<br class="">+<br class="">+def int_hexagon_M2_mpyi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;<br class="">+<br class="">+def int_hexagon_M2_mpyui :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">;<br class="">+<br class="">+def int_hexagon_M2_maci :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">;<br class="">+<br class="">+def int_hexagon_M2_acci :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">;<br class="">+<br class="">+def int_hexagon_M2_accii :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M2_nacci :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">;<br class="">+<br class="">+def int_hexagon_M2_naccii :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M2_subacc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;<br class="">+<br class="">+def int_hexagon_M4_mpyrr_addr :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">;<br class="">+<br class="">+def int_hexagon_M4_mpyri_addr_u2 :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_M4_mpyri_addr :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M4_mpyri_addi :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M4_mpyrr_addi :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_M2_vmpy2s_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2s_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;<br class="">+<br class="">+def int_hexagon_M2_vmac2s_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">;<br class="">+<br class="">+def int_hexagon_M2_vmac2s_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2su_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2su_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;<br class="">+<br class="">+def int_hexagon_M2_vmac2su_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">;<br class="">+<br class="">+def int_hexagon_M2_vmac2su_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2s_s0pack :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2s_s1pack :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;<br class="">+<br class="">+def int_hexagon_M2_vmac2 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2es_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;<br class="">+<br class="">+def int_hexagon_M2_vmpy2es_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;<br class="">+<br class="">+def int_hexagon_M2_vmac2es_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;<br class="">+<br class="">+def int_hexagon_M2_vmac2es_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;<br class="">+<br class="">+def int_hexagon_M2_vmac2es :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">;<br class="">+<br class="">+def int_hexagon_M2_vrmac_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">;<br class="">+<br class="">+def int_hexagon_M2_vrmpy_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">;<br class="">+<br class="">+def int_hexagon_M2_vdmpyrs_s0 :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;<br class="">+<br class="">+def int_hexagon_M2_vdmpyrs_s1 :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;<br class="">+<br class="">+def int_hexagon_M5_vrmpybuu :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;<br class="">+<br class="">+def int_hexagon_M5_vrmacbuu :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">;<br class="">+<br class="">+def int_hexagon_M5_vrmpybsu :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">;<br class="">+<br class="">+def int_hexagon_M5_vrmacbsu :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">;<br class="">+<br class="">+def int_hexagon_M5_vmpybuu :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">;<br class="">+<br class="">+def int_hexagon_M5_vmpybsu :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">;<br class="">+<br class="">+def int_hexagon_M5_vmacbuu :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;<br class="">+<br class="">+def int_hexagon_M5_vmacbsu :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">;<br class="">+<br class="">+def int_hexagon_M5_vdmpybsu :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">;<br class="">+<br class="">+def int_hexagon_M5_vdmacbsu :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">;<br class="">+<br class="">+def int_hexagon_M2_vdmacs_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">;<br class="">+<br class="">+def int_hexagon_M2_vdmacs_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">;<br class="">+<br class="">+def int_hexagon_M2_vdmpys_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">;<br class="">+<br class="">+def int_hexagon_M2_vdmpys_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">;<br class="">+<br class="">+def int_hexagon_M2_cmpyrs_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmpyrs_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;<br class="">+<br class="">+def int_hexagon_M2_cmpyrsc_s0 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmpyrsc_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;<br class="">+<br class="">+def int_hexagon_M2_cmacs_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmacs_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">;<br class="">+<br class="">+def int_hexagon_M2_cmacsc_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmacsc_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">;<br class="">+<br class="">+def int_hexagon_M2_cmpys_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmpys_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">;<br class="">+<br class="">+def int_hexagon_M2_cmpysc_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmpysc_s1 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">;<br class="">+<br class="">+def int_hexagon_M2_cnacs_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">;<br class="">+<br class="">+def int_hexagon_M2_cnacs_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">;<br class="">+<br class="">+def int_hexagon_M2_cnacsc_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;<br class="">+<br class="">+def int_hexagon_M2_cnacsc_s1 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpys_s1 :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpys_acc_s1 :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpys_s1rp :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;<br class="">+<br class="">+def int_hexagon_M2_mmacls_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmacls_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmachs_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmachs_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyl_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyl_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyh_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyh_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmacls_rs0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmacls_rs1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">;<br class="">+<br class="">+def int_hexagon_M2_mmachs_rs0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmachs_rs1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyl_rs0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyl_rs1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyh_rs0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyh_rs1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyeh_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyeh_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyeh_acc_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyeh_acc_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyoh_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyoh_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyoh_acc_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;<br class="">+<br class="">+def int_hexagon_M4_vrmpyoh_acc_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;<br class="">+<br class="">+def int_hexagon_M2_hmmpyl_rs1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;<br class="">+<br class="">+def int_hexagon_M2_hmmpyh_rs1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;<br class="">+<br class="">+def int_hexagon_M2_hmmpyl_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;<br class="">+<br class="">+def int_hexagon_M2_hmmpyh_s1 :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmaculs_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmaculs_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmacuhs_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmacuhs_s1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyul_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyul_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyuh_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyuh_s1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;<br class="">+<br class="">+def int_hexagon_M2_mmaculs_rs0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmaculs_rs1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;<br class="">+<br class="">+def int_hexagon_M2_mmacuhs_rs0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmacuhs_rs1 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyul_rs0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyul_rs1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;<br class="">+<br class="">+def int_hexagon_M2_mmpyuh_rs0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;<br class="">+<br class="">+def int_hexagon_M2_mmpyuh_rs1 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;<br class="">+<br class="">+def int_hexagon_M2_vrcmaci_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;<br class="">+<br class="">+def int_hexagon_M2_vrcmacr_s0 :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;<br class="">+<br class="">+def int_hexagon_M2_vrcmaci_s0c :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;<br class="">+<br class="">+def int_hexagon_M2_vrcmacr_s0c :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;<br class="">+<br class="">+def int_hexagon_M2_cmaci_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmacr_s0 :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpyi_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpyr_s0 :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpyi_s0c :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;<br class="">+<br class="">+def int_hexagon_M2_vrcmpyr_s0c :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;<br class="">+<br class="">+def int_hexagon_M2_cmpyi_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;<br class="">+<br class="">+def int_hexagon_M2_cmpyr_s0 :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;<br class="">+<br class="">+def int_hexagon_M4_cmpyi_wh :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;<br class="">+<br class="">+def int_hexagon_M4_cmpyr_wh :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;<br class="">+<br class="">+def int_hexagon_M4_cmpyi_whc :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">;<br class="">+<br class="">+def int_hexagon_M4_cmpyr_whc :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;<br class="">+<br class="">+def int_hexagon_M2_vcmpy_s0_sat_i :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;<br class="">+<br class="">+def int_hexagon_M2_vcmpy_s0_sat_r :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;<br class="">+<br class="">+def int_hexagon_M2_vcmpy_s1_sat_i :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;<br class="">+<br class="">+def int_hexagon_M2_vcmpy_s1_sat_r :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;<br class="">+<br class="">+def int_hexagon_M2_vcmac_s0_sat_i :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;<br class="">+<br class="">+def int_hexagon_M2_vcmac_s0_sat_r :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;<br class="">+<br class="">+def int_hexagon_S2_vcrotate :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">;<br class="">+<br class="">+def int_hexagon_S4_vrcrotate_acc :<br class="">+Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_S4_vrcrotate :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_vcnegh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;<br class="">+<br class="">+def int_hexagon_S2_vrcnegh :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;<br class="">+<br class="">+def int_hexagon_M4_pmpyw :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;<br class="">+<br class="">+def int_hexagon_M4_vpmpyh :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">;<br class="">+<br class="">+def int_hexagon_M4_pmpyw_acc :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">;<br class="">+<br class="">+def int_hexagon_M4_vpmpyh_acc :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;<br class="">+<br class="">+def int_hexagon_A2_add :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">;<br class="">+<br class="">+def int_hexagon_A2_sub :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">;<br class="">+<br class="">+def int_hexagon_A2_addsat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;<br class="">+<br class="">+def int_hexagon_A2_subsat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">;<br class="">+<br class="">+def int_hexagon_A2_addi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_addh_l16_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">;<br class="">+<br class="">+def int_hexagon_A2_addh_l16_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;<br class="">+<br class="">+def int_hexagon_A2_addh_l16_sat_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;<br class="">+<br class="">+def int_hexagon_A2_addh_l16_sat_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;<br class="">+<br class="">+def int_hexagon_A2_subh_l16_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">;<br class="">+<br class="">+def int_hexagon_A2_subh_l16_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">;<br class="">+<br class="">+def int_hexagon_A2_subh_l16_sat_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;<br class="">+<br class="">+def int_hexagon_A2_subh_l16_sat_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_lh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_hh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_sat_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_sat_lh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_sat_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;<br class="">+<br class="">+def int_hexagon_A2_addh_h16_sat_hh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_lh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_hh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_sat_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_sat_lh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_sat_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;<br class="">+<br class="">+def int_hexagon_A2_subh_h16_sat_hh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;<br class="">+<br class="">+def int_hexagon_A2_aslh :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">;<br class="">+<br class="">+def int_hexagon_A2_asrh :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">;<br class="">+<br class="">+def int_hexagon_A2_addp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">;<br class="">+<br class="">+def int_hexagon_A2_addpsat :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">;<br class="">+<br class="">+def int_hexagon_A2_addsp :<br class="">+Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;<br class="">+<br class="">+def int_hexagon_A2_subp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">;<br class="">+<br class="">+def int_hexagon_A2_neg :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">;<br class="">+<br class="">+def int_hexagon_A2_negsat :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">;<br class="">+<br class="">+def int_hexagon_A2_abs :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">;<br class="">+<br class="">+def int_hexagon_A2_abssat :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;<br class="">+<br class="">+def int_hexagon_A2_vconj :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;<br class="">+<br class="">+def int_hexagon_A2_negp :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">;<br class="">+<br class="">+def int_hexagon_A2_absp :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">;<br class="">+<br class="">+def int_hexagon_A2_max :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;<br class="">+<br class="">+def int_hexagon_A2_maxu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">;<br class="">+<br class="">+def int_hexagon_A2_min :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">;<br class="">+<br class="">+def int_hexagon_A2_minu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">;<br class="">+<br class="">+def int_hexagon_A2_maxp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">;<br class="">+<br class="">+def int_hexagon_A2_maxup :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;<br class="">+<br class="">+def int_hexagon_A2_minp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;<br class="">+<br class="">+def int_hexagon_A2_minup :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">;<br class="">+<br class="">+def int_hexagon_A2_tfr :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">;<br class="">+<br class="">+def int_hexagon_A2_tfrsi :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_A2_tfrp :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">;<br class="">+<br class="">+def int_hexagon_A2_tfrpi :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_A2_zxtb :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">;<br class="">+<br class="">+def int_hexagon_A2_sxtb :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">;<br class="">+<br class="">+def int_hexagon_A2_zxth :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">;<br class="">+<br class="">+def int_hexagon_A2_sxth :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">;<br class="">+<br class="">+def int_hexagon_A2_combinew :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">;<br class="">+<br class="">+def int_hexagon_A4_combineri :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_combineir :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_A2_combineii :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<0>, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_combine_hh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">;<br class="">+<br class="">+def int_hexagon_A2_combine_hl :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;<br class="">+<br class="">+def int_hexagon_A2_combine_lh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">;<br class="">+<br class="">+def int_hexagon_A2_combine_ll :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">;<br class="">+<br class="">+def int_hexagon_A2_tfril :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_tfrih :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_and :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">;<br class="">+<br class="">+def int_hexagon_A2_or :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">;<br class="">+<br class="">+def int_hexagon_A2_xor :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">;<br class="">+<br class="">+def int_hexagon_A2_not :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;<br class="">+<br class="">+def int_hexagon_M2_xor_xacc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">;<br class="">+<br class="">+def int_hexagon_M4_xor_xacc :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">;<br class="">+<br class="">+def int_hexagon_A4_andn :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">;<br class="">+<br class="">+def int_hexagon_A4_orn :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">;<br class="">+<br class="">+def int_hexagon_A4_andnp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">;<br class="">+<br class="">+def int_hexagon_A4_ornp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">;<br class="">+<br class="">+def int_hexagon_S4_addaddi :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_subaddi :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_M4_and_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;<br class="">+<br class="">+def int_hexagon_M4_and_andn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;<br class="">+<br class="">+def int_hexagon_M4_and_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">;<br class="">+<br class="">+def int_hexagon_M4_and_xor :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;<br class="">+<br class="">+def int_hexagon_M4_or_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;<br class="">+<br class="">+def int_hexagon_M4_or_andn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;<br class="">+<br class="">+def int_hexagon_M4_or_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">;<br class="">+<br class="">+def int_hexagon_M4_or_xor :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">;<br class="">+<br class="">+def int_hexagon_S4_or_andix :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_or_andi :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_or_ori :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_M4_xor_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;<br class="">+<br class="">+def int_hexagon_M4_xor_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">;<br class="">+<br class="">+def int_hexagon_M4_xor_andn :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;<br class="">+<br class="">+def int_hexagon_A2_subri :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_A2_andir :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_orir :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A2_andp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">;<br class="">+<br class="">+def int_hexagon_A2_orp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;<br class="">+<br class="">+def int_hexagon_A2_xorp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">;<br class="">+<br class="">+def int_hexagon_A2_notp :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">;<br class="">+<br class="">+def int_hexagon_A2_sxtw :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">;<br class="">+<br class="">+def int_hexagon_A2_sat :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;<br class="">+<br class="">+def int_hexagon_A2_roundsat :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">;<br class="">+<br class="">+def int_hexagon_A2_sath :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;<br class="">+<br class="">+def int_hexagon_A2_satuh :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">;<br class="">+<br class="">+def int_hexagon_A2_satub :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">;<br class="">+<br class="">+def int_hexagon_A2_satb :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;<br class="">+<br class="">+def int_hexagon_A2_vaddub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">;<br class="">+<br class="">+def int_hexagon_A2_vaddb_map :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">;<br class="">+<br class="">+def int_hexagon_A2_vaddubs :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">;<br class="">+<br class="">+def int_hexagon_A2_vaddh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;<br class="">+<br class="">+def int_hexagon_A2_vaddhs :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">;<br class="">+<br class="">+def int_hexagon_A2_vadduhs :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">;<br class="">+<br class="">+def int_hexagon_A5_vaddhubs :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;<br class="">+<br class="">+def int_hexagon_A2_vaddw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;<br class="">+<br class="">+def int_hexagon_A2_vaddws :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;<br class="">+<br class="">+def int_hexagon_S4_vxaddsubw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;<br class="">+<br class="">+def int_hexagon_S4_vxsubaddw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;<br class="">+<br class="">+def int_hexagon_S4_vxaddsubh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">;<br class="">+<br class="">+def int_hexagon_S4_vxsubaddh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;<br class="">+<br class="">+def int_hexagon_S4_vxaddsubhr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">;<br class="">+<br class="">+def int_hexagon_S4_vxsubaddhr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">;<br class="">+<br class="">+def int_hexagon_A2_svavgh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;<br class="">+<br class="">+def int_hexagon_A2_svavghs :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;<br class="">+<br class="">+def int_hexagon_A2_svnavgh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;<br class="">+<br class="">+def int_hexagon_A2_svaddh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">;<br class="">+<br class="">+def int_hexagon_A2_svaddhs :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">;<br class="">+<br class="">+def int_hexagon_A2_svadduhs :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">;<br class="">+<br class="">+def int_hexagon_A2_svsubh :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">;<br class="">+<br class="">+def int_hexagon_A2_svsubhs :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;<br class="">+<br class="">+def int_hexagon_A2_svsubuhs :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">;<br class="">+<br class="">+def int_hexagon_A2_vraddub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">;<br class="">+<br class="">+def int_hexagon_A2_vraddub_acc :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">;<br class="">+<br class="">+def int_hexagon_M2_vraddh :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">;<br class="">+<br class="">+def int_hexagon_M2_vradduh :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">;<br class="">+<br class="">+def int_hexagon_A2_vsubub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;<br class="">+<br class="">+def int_hexagon_A2_vsubb_map :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">;<br class="">+<br class="">+def int_hexagon_A2_vsububs :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">;<br class="">+<br class="">+def int_hexagon_A2_vsubh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">;<br class="">+<br class="">+def int_hexagon_A2_vsubhs :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">;<br class="">+<br class="">+def int_hexagon_A2_vsubuhs :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">;<br class="">+<br class="">+def int_hexagon_A2_vsubw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">;<br class="">+<br class="">+def int_hexagon_A2_vsubws :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;<br class="">+<br class="">+def int_hexagon_A2_vabsh :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">;<br class="">+<br class="">+def int_hexagon_A2_vabshsat :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">;<br class="">+<br class="">+def int_hexagon_A2_vabsw :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">;<br class="">+<br class="">+def int_hexagon_A2_vabswsat :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;<br class="">+<br class="">+def int_hexagon_M2_vabs<br class="">diff w :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabs<br class="">diff w">;<br class="">+<br class="">+def int_hexagon_M2_vabs<br class="">diff h :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabs<br class="">diff h">;<br class="">+<br class="">+def int_hexagon_A2_vrsadub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">;<br class="">+<br class="">+def int_hexagon_A2_vrsadub_acc :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;<br class="">+<br class="">+def int_hexagon_A2_vavgub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;<br class="">+<br class="">+def int_hexagon_A2_vavguh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;<br class="">+<br class="">+def int_hexagon_A2_vavgh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">;<br class="">+<br class="">+def int_hexagon_A2_vnavgh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">;<br class="">+<br class="">+def int_hexagon_A2_vavgw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">;<br class="">+<br class="">+def int_hexagon_A2_vnavgw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;<br class="">+<br class="">+def int_hexagon_A2_vavgwr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">;<br class="">+<br class="">+def int_hexagon_A2_vnavgwr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">;<br class="">+<br class="">+def int_hexagon_A2_vavgwcr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;<br class="">+<br class="">+def int_hexagon_A2_vnavgwcr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">;<br class="">+<br class="">+def int_hexagon_A2_vavghcr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">;<br class="">+<br class="">+def int_hexagon_A2_vnavghcr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;<br class="">+<br class="">+def int_hexagon_A2_vavguw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;<br class="">+<br class="">+def int_hexagon_A2_vavguwr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;<br class="">+<br class="">+def int_hexagon_A2_vavgubr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">;<br class="">+<br class="">+def int_hexagon_A2_vavguhr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">;<br class="">+<br class="">+def int_hexagon_A2_vavghr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">;<br class="">+<br class="">+def int_hexagon_A2_vnavghr :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;<br class="">+<br class="">+def int_hexagon_A4_round_ri :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_round_rr :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;<br class="">+<br class="">+def int_hexagon_A4_round_ri_sat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_round_rr_sat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">;<br class="">+<br class="">+def int_hexagon_A4_cround_ri :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_cround_rr :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">;<br class="">+<br class="">+def int_hexagon_A4_vrminh :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;<br class="">+<br class="">+def int_hexagon_A4_vrmaxh :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">;<br class="">+<br class="">+def int_hexagon_A4_vrminuh :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">;<br class="">+<br class="">+def int_hexagon_A4_vrmaxuh :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">;<br class="">+<br class="">+def int_hexagon_A4_vrminw :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;<br class="">+<br class="">+def int_hexagon_A4_vrmaxw :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;<br class="">+<br class="">+def int_hexagon_A4_vrminuw :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;<br class="">+<br class="">+def int_hexagon_A4_vrmaxuw :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">;<br class="">+<br class="">+def int_hexagon_A2_vminb :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">;<br class="">+<br class="">+def int_hexagon_A2_vmaxb :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;<br class="">+<br class="">+def int_hexagon_A2_vminub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">;<br class="">+<br class="">+def int_hexagon_A2_vmaxub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">;<br class="">+<br class="">+def int_hexagon_A2_vminh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">;<br class="">+<br class="">+def int_hexagon_A2_vmaxh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;<br class="">+<br class="">+def int_hexagon_A2_vminuh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">;<br class="">+<br class="">+def int_hexagon_A2_vmaxuh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">;<br class="">+<br class="">+def int_hexagon_A2_vminw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">;<br class="">+<br class="">+def int_hexagon_A2_vmaxw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;<br class="">+<br class="">+def int_hexagon_A2_vminuw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">;<br class="">+<br class="">+def int_hexagon_A2_vmaxuw :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">;<br class="">+<br class="">+def int_hexagon_A4_modwrapu :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">;<br class="">+<br class="">+def int_hexagon_F2_sfadd :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfsub :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfmpy :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffma :<br class="">+Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffma_sc :<br class="">+Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffms :<br class="">+Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffma_lib :<br class="">+Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffms_lib :<br class="">+Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfcmpeq :<br class="">+Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfcmpgt :<br class="">+Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfcmpge :<br class="">+Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfcmpuo :<br class="">+Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfmax :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfmin :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sfclass :<br class="">+Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_F2_sfimm_p :<br class="">+Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_F2_sfimm_n :<br class="">+Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_F2_sffixupn :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffixupd :<br class="">+Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_sffixupr :<br class="">+Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_dfcmpeq :<br class="">+Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_dfcmpgt :<br class="">+Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_dfcmpge :<br class="">+Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_dfcmpuo :<br class="">+Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_dfclass :<br class="">+Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_F2_dfimm_p :<br class="">+Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_F2_dfimm_n :<br class="">+Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2df :<br class="">+Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2sf :<br class="">+Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">;<br class="">+<br class="">+def int_hexagon_F2_conv_uw2sf :<br class="">+Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;<br class="">+<br class="">+def int_hexagon_F2_conv_uw2df :<br class="">+Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">;<br class="">+<br class="">+def int_hexagon_F2_conv_w2sf :<br class="">+Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;<br class="">+<br class="">+def int_hexagon_F2_conv_w2df :<br class="">+Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;<br class="">+<br class="">+def int_hexagon_F2_conv_ud2sf :<br class="">+Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">;<br class="">+<br class="">+def int_hexagon_F2_conv_ud2df :<br class="">+Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;<br class="">+<br class="">+def int_hexagon_F2_conv_d2sf :<br class="">+Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;<br class="">+<br class="">+def int_hexagon_F2_conv_d2df :<br class="">+Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2uw :<br class="">+Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2w :<br class="">+Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2ud :<br class="">+Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2d :<br class="">+Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2uw :<br class="">+Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2w :<br class="">+Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2ud :<br class="">+Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2d :<br class="">+Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2uw_chop :<br class="">+Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2w_chop :<br class="">+Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2ud_chop :<br class="">+Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_sf2d_chop :<br class="">+Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2uw_chop :<br class="">+Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2w_chop :<br class="">+Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2ud_chop :<br class="">+Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;<br class="">+<br class="">+def int_hexagon_F2_conv_df2d_chop :<br class="">+Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_p_xor :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_p_xor :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_p_xor :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_p_xor :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;<br class="">+<br class="">+def int_hexagon_S2_asr_r_r_sat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_r_sat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_r_xacc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r_xacc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_p_xacc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_p_xacc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_r_sat :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r_rnd :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_r_rnd_goodsyntax :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p_rnd :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_p_rnd_goodsyntax :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S4_lsli :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg<0>]>;<br class="">+<br class="">+def int_hexagon_S2_addasl_rrri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_andi_asl_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_ori_asl_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_addi_asl_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_subi_asl_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_andi_lsr_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_ori_lsr_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_addi_lsr_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S4_subi_lsr_ri :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg<0>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_valignib :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_valignrb :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">;<br class="">+<br class="">+def int_hexagon_S2_vspliceib :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_vsplicerb :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">;<br class="">+<br class="">+def int_hexagon_S2_vsplatrh :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">;<br class="">+<br class="">+def int_hexagon_S2_vsplatrb :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">;<br class="">+<br class="">+def int_hexagon_S2_insert :<br class="">+Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_S2_tableidxb_goodsyntax :<br class="">+Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_S2_tableidxh_goodsyntax :<br class="">+Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_S2_tableidxw_goodsyntax :<br class="">+Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_S2_tableidxd_goodsyntax :<br class="">+Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_A4_bitspliti :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_A4_bitsplit :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">;<br class="">+<br class="">+def int_hexagon_S4_extract :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<1>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_extractu :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<1>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_insertp :<br class="">+Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<2>, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_S4_extractp :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<1>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_extractup :<br class="">+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<1>, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S2_insert_rp :<br class="">+Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">;<br class="">+<br class="">+def int_hexagon_S4_extract_rp :<br class="">+Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;<br class="">+<br class="">+def int_hexagon_S2_extractu_rp :<br class="">+Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;<br class="">+<br class="">+def int_hexagon_S2_insertp_rp :<br class="">+Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;<br class="">+<br class="">+def int_hexagon_S4_extractp_rp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">;<br class="">+<br class="">+def int_hexagon_S2_extractup_rp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;<br class="">+<br class="">+def int_hexagon_S2_tstbit_i :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S4_ntstbit_i :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_setbit_i :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_togglebit_i :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_clrbit_i :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_tstbit_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;<br class="">+<br class="">+def int_hexagon_S4_ntstbit_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;<br class="">+<br class="">+def int_hexagon_S2_setbit_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">;<br class="">+<br class="">+def int_hexagon_S2_togglebit_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;<br class="">+<br class="">+def int_hexagon_S2_clrbit_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">;<br class="">+<br class="">+def int_hexagon_S2_asr_i_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_r_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">;<br class="">+<br class="">+def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S5_asrhub_sat :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S5_vasrhrnd_goodsyntax :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_r_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_vh :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;<br class="">+<br class="">+def int_hexagon_S2_asr_i_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_i_svw_trun :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_r_svw_trun :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;<br class="">+<br class="">+def int_hexagon_S2_lsr_i_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asl_i_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_asr_r_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">;<br class="">+<br class="">+def int_hexagon_S2_asl_r_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">;<br class="">+<br class="">+def int_hexagon_S2_lsr_r_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;<br class="">+<br class="">+def int_hexagon_S2_lsl_r_vw :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">;<br class="">+<br class="">+def int_hexagon_S2_vrndpackwh :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">;<br class="">+<br class="">+def int_hexagon_S2_vrndpackwhs :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">;<br class="">+<br class="">+def int_hexagon_S2_vsxtbh :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">;<br class="">+<br class="">+def int_hexagon_S2_vzxtbh :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;<br class="">+<br class="">+def int_hexagon_S2_vsathub :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">;<br class="">+<br class="">+def int_hexagon_S2_svsathub :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">;<br class="">+<br class="">+def int_hexagon_S2_svsathb :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">;<br class="">+<br class="">+def int_hexagon_S2_vsathb :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">;<br class="">+<br class="">+def int_hexagon_S2_vtrunohb :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">;<br class="">+<br class="">+def int_hexagon_S2_vtrunewh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">;<br class="">+<br class="">+def int_hexagon_S2_vtrunowh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">;<br class="">+<br class="">+def int_hexagon_S2_vtrunehb :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">;<br class="">+<br class="">+def int_hexagon_S2_vsxthw :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;<br class="">+<br class="">+def int_hexagon_S2_vzxthw :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;<br class="">+<br class="">+def int_hexagon_S2_vsatwh :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">;<br class="">+<br class="">+def int_hexagon_S2_vsatwuh :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">;<br class="">+<br class="">+def int_hexagon_S2_packhl :<br class="">+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;<br class="">+<br class="">+def int_hexagon_A2_swiz :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">;<br class="">+<br class="">+def int_hexagon_S2_vsathub_nopack :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">;<br class="">+<br class="">+def int_hexagon_S2_vsathb_nopack :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;<br class="">+<br class="">+def int_hexagon_S2_vsatwh_nopack :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;<br class="">+<br class="">+def int_hexagon_S2_vsatwuh_nopack :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;<br class="">+<br class="">+def int_hexagon_S2_shuffob :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">;<br class="">+<br class="">+def int_hexagon_S2_shuffeb :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">;<br class="">+<br class="">+def int_hexagon_S2_shuffoh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">;<br class="">+<br class="">+def int_hexagon_S2_shuffeh :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">;<br class="">+<br class="">+def int_hexagon_S5_popcountp :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">;<br class="">+<br class="">+def int_hexagon_S4_parity :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">;<br class="">+<br class="">+def int_hexagon_S2_parityp :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;<br class="">+<br class="">+def int_hexagon_S2_lfsp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">;<br class="">+<br class="">+def int_hexagon_S2_clbnorm :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">;<br class="">+<br class="">+def int_hexagon_S4_clbaddi :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S4_clbpnorm :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">;<br class="">+<br class="">+def int_hexagon_S4_clbpaddi :<br class="">+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S2_clb :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">;<br class="">+<br class="">+def int_hexagon_S2_cl0 :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">;<br class="">+<br class="">+def int_hexagon_S2_cl1 :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">;<br class="">+<br class="">+def int_hexagon_S2_clbp :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">;<br class="">+<br class="">+def int_hexagon_S2_cl0p :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;<br class="">+<br class="">+def int_hexagon_S2_cl1p :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">;<br class="">+<br class="">+def int_hexagon_S2_brev :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">;<br class="">+<br class="">+def int_hexagon_S2_brevp :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">;<br class="">+<br class="">+def int_hexagon_S2_ct0 :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">;<br class="">+<br class="">+def int_hexagon_S2_ct1 :<br class="">+Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">;<br class="">+<br class="">+def int_hexagon_S2_ct0p :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">;<br class="">+<br class="">+def int_hexagon_S2_ct1p :<br class="">+Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">;<br class="">+<br class="">+def int_hexagon_S2_interleave :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;<br class="">+<br class="">+def int_hexagon_S2_deinterleave :<br class="">+Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">;<br class="">+<br class="">+def int_hexagon_Y2_dcfetch :<br class="">+Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>;<br class="">+<br class="">+def int_hexagon_Y2_dczeroa :<br class="">+Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>;<br class="">+<br class="">+def int_hexagon_Y2_dccleana :<br class="">+Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>;<br class="">+<br class="">+def int_hexagon_Y2_dccleaninva :<br class="">+Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>;<br class="">+<br class="">+def int_hexagon_Y2_dcinva :<br class="">+Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>;<br class="">+<br class="">+def int_hexagon_Y4_l2fetch :<br class="">+Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>;<br class="">+<br class="">+def int_hexagon_Y5_l2fetch :<br class="">+Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>;<br class="">+<br class="">+// V60 Scalar Instructions.<br class="">+<br class="">+def int_hexagon_S6_rol_i_r :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_p :<br class="">+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg<1>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_r_acc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_p_acc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_r_nac :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_p_nac :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_r_xacc :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_p_xacc :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_r_and :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_r_or :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_p_and :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_S6_rol_i_p_or :<br class="">+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+// V62 Scalar Instructions.<br class="">+<br class="">+def int_hexagon_M6_vabs<br class="">diff b :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabs<br class="">diff b">;<br class="">+<br class="">+def int_hexagon_M6_vabs<br class="">diff ub :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabs<br class="">diff ub">;<br class="">+<br class="">+def int_hexagon_S6_vsplatrbp :<br class="">+Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">;<br class="">+<br class="">+def int_hexagon_S6_vtrunehb_ppp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;<br class="">+<br class="">+def int_hexagon_S6_vtrunohb_ppp :<br class="">+Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;<br class="">+<br class="">+// V65 Scalar Instructions.<br class="">+<br class="">+def int_hexagon_A6_vcmpbeq_notany :<br class="">+Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;<br class="">+<br class="">+// V66 Scalar Instructions.<br class="">+<br class="">+def int_hexagon_M2_mnaci :<br class="">+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">;<br class="">+<br class="">+def int_hexagon_F2_dfadd :<br class="">+Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_F2_dfsub :<br class="">+Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>;<br class="">+<br class="">+def int_hexagon_S2_mask :<br class="">+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<0>, ImmArg<1>]>;<br class="">+<br class="">+// V60 HVX Instructions.<br class="">+<br class="">+def int_hexagon_V6_vS32b_qpred_ai :<br class="">+Hexagon__v512i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_qpred_ai_128B :<br class="">+Hexagon__v1024i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_nqpred_ai :<br class="">+Hexagon__v512i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_nqpred_ai_128B :<br class="">+Hexagon__v1024i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_nt_qpred_ai :<br class="">+Hexagon__v512i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_nt_qpred_ai_128B :<br class="">+Hexagon__v1024i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_nt_nqpred_ai :<br class="">+Hexagon__v512i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :<br class="">+Hexagon__v1024i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_valignb :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">;<br class="">+<br class="">+def int_hexagon_V6_valignb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlalignb :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">;<br class="">+<br class="">+def int_hexagon_V6_vlalignb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">;<br class="">+<br class="">+def int_hexagon_V6_valignbi :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_valignbi_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vlalignbi :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vlalignbi_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vror :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">;<br class="">+<br class="">+def int_hexagon_V6_vror_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">;<br class="">+<br class="">+def int_hexagon_V6_vunpackub :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">;<br class="">+<br class="">+def int_hexagon_V6_vunpackub_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vunpackb :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">;<br class="">+<br class="">+def int_hexagon_V6_vunpackb_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vunpackuh :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">;<br class="">+<br class="">+def int_hexagon_V6_vunpackuh_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vunpackh :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">;<br class="">+<br class="">+def int_hexagon_V6_vunpackh_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vunpackob :<br class="">+Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">;<br class="">+<br class="">+def int_hexagon_V6_vunpackob_128B :<br class="">+Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">;<br class="">+<br class="">+def int_hexagon_V6_vunpackoh :<br class="">+Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">;<br class="">+<br class="">+def int_hexagon_V6_vunpackoh_128B :<br class="">+Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackeb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">;<br class="">+<br class="">+def int_hexagon_V6_vpackeb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackeh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">;<br class="">+<br class="">+def int_hexagon_V6_vpackeh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackob :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">;<br class="">+<br class="">+def int_hexagon_V6_vpackob_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackoh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">;<br class="">+<br class="">+def int_hexagon_V6_vpackoh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackhub_sat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">;<br class="">+<br class="">+def int_hexagon_V6_vpackhub_sat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackhb_sat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">;<br class="">+<br class="">+def int_hexagon_V6_vpackhb_sat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackwuh_sat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;<br class="">+<br class="">+def int_hexagon_V6_vpackwuh_sat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpackwh_sat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">;<br class="">+<br class="">+def int_hexagon_V6_vpackwh_sat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vzb :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">;<br class="">+<br class="">+def int_hexagon_V6_vzb_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsb :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">;<br class="">+<br class="">+def int_hexagon_V6_vsb_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vzh :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">;<br class="">+<br class="">+def int_hexagon_V6_vzh_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsh :<br class="">+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">;<br class="">+<br class="">+def int_hexagon_V6_vsh_128B :<br class="">+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_dv :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_dv_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_dv_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpybus_dv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_dv :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_dv_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_dv_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhb_dv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhvsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhvsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhvsat_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhvsat_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsat :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsat_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsat_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsat_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhisat :<br class="">+Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhisat_128B :<br class="">+Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhisat_acc :<br class="">+Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhisat_acc_128B :<br class="">+Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsusat :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsusat_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsusat_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsusat_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsuisat :<br class="">+Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsuisat_128B :<br class="">+Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsuisat_acc :<br class="">+Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdmpyhsuisat_acc_128B :<br class="">+Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyb :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyb_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyb_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyb_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vtmpybus :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">;<br class="">+<br class="">+def int_hexagon_V6_vtmpybus_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;<br class="">+<br class="">+def int_hexagon_V6_vtmpybus_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;<br class="">+<br class="">+def int_hexagon_V6_vtmpybus_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyhb :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyhb_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyhb_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vtmpyhb_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyub_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubv_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubv_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybv_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybv_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubi :<br class="">+Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubi_128B :<br class="">+Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubi_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpyubi_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpybus :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybus_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybus_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybus_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusi :<br class="">+Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusi_128B :<br class="">+Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusi_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusi_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusv_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vrmpybusv_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdsaduh :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">;<br class="">+<br class="">+def int_hexagon_V6_vdsaduh_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdsaduh_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vdsaduh_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrsadubi :<br class="">+Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vrsadubi_128B :<br class="">+Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vrsadubi_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vrsadubi_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vasrw :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">;<br class="">+<br class="">+def int_hexagon_V6_vasrw_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaslw :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">;<br class="">+<br class="">+def int_hexagon_V6_vaslw_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlsrw :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">;<br class="">+<br class="">+def int_hexagon_V6_vlsrw_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrwv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">;<br class="">+<br class="">+def int_hexagon_V6_vasrwv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaslwv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">;<br class="">+<br class="">+def int_hexagon_V6_vaslwv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlsrwv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">;<br class="">+<br class="">+def int_hexagon_V6_vlsrwv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrh :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">;<br class="">+<br class="">+def int_hexagon_V6_vasrh_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaslh :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">;<br class="">+<br class="">+def int_hexagon_V6_vaslh_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlsrh :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">;<br class="">+<br class="">+def int_hexagon_V6_vlsrh_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrhv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">;<br class="">+<br class="">+def int_hexagon_V6_vasrhv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaslhv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">;<br class="">+<br class="">+def int_hexagon_V6_vaslhv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlsrhv :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">;<br class="">+<br class="">+def int_hexagon_V6_vlsrhv_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrwh :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">;<br class="">+<br class="">+def int_hexagon_V6_vasrwh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrwhsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrwhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrwhrndsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrwhrndsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrwuhsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrwuhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vroundwh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">;<br class="">+<br class="">+def int_hexagon_V6_vroundwh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vroundwuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">;<br class="">+<br class="">+def int_hexagon_V6_vroundwuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrhubsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrhubsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrhubrndsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrhubrndsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrhbrndsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrhbrndsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vroundhb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">;<br class="">+<br class="">+def int_hexagon_V6_vroundhb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vroundhub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">;<br class="">+<br class="">+def int_hexagon_V6_vroundhub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaslw_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">;<br class="">+<br class="">+def int_hexagon_V6_vaslw_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrw_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">;<br class="">+<br class="">+def int_hexagon_V6_vasrw_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">;<br class="">+<br class="">+def int_hexagon_V6_vaddb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">;<br class="">+<br class="">+def int_hexagon_V6_vsubb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddb_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddb_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubb_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubb_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">;<br class="">+<br class="">+def int_hexagon_V6_vaddh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">;<br class="">+<br class="">+def int_hexagon_V6_vsubh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddh_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddh_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubh_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubh_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">;<br class="">+<br class="">+def int_hexagon_V6_vaddw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">;<br class="">+<br class="">+def int_hexagon_V6_vsubw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddw_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddw_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubw_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubw_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddubsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">;<br class="">+<br class="">+def int_hexagon_V6_vaddubsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddubsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddubsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsububsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">;<br class="">+<br class="">+def int_hexagon_V6_vsububsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsububsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsububsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vadduhsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">;<br class="">+<br class="">+def int_hexagon_V6_vadduhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vadduhsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vadduhsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubuhsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">;<br class="">+<br class="">+def int_hexagon_V6_vsubuhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubuhsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubuhsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddhsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">;<br class="">+<br class="">+def int_hexagon_V6_vaddhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddhsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddhsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubhsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">;<br class="">+<br class="">+def int_hexagon_V6_vsubhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubhsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubhsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddwsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">;<br class="">+<br class="">+def int_hexagon_V6_vaddwsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddwsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddwsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubwsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">;<br class="">+<br class="">+def int_hexagon_V6_vsubwsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubwsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubwsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">;<br class="">+<br class="">+def int_hexagon_V6_vavgub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgubrnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">;<br class="">+<br class="">+def int_hexagon_V6_vavgubrnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavguh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">;<br class="">+<br class="">+def int_hexagon_V6_vavguh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavguhrnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">;<br class="">+<br class="">+def int_hexagon_V6_vavguhrnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">;<br class="">+<br class="">+def int_hexagon_V6_vavgh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavghrnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">;<br class="">+<br class="">+def int_hexagon_V6_vavghrnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnavgh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">;<br class="">+<br class="">+def int_hexagon_V6_vnavgh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">;<br class="">+<br class="">+def int_hexagon_V6_vavgw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgwrnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">;<br class="">+<br class="">+def int_hexagon_V6_vavgwrnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnavgw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">;<br class="">+<br class="">+def int_hexagon_V6_vnavgw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff ub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff ub">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff ub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff ub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff uh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff uh">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff uh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff uh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff h :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff h">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff h_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff h_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff w :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff w">;<br class="">+<br class="">+def int_hexagon_V6_vabs<br class="">diff w_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabs<br class="">diff w_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnavgub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">;<br class="">+<br class="">+def int_hexagon_V6_vnavgub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddubh :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">;<br class="">+<br class="">+def int_hexagon_V6_vaddubh_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsububh :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">;<br class="">+<br class="">+def int_hexagon_V6_vsububh_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddhw :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">;<br class="">+<br class="">+def int_hexagon_V6_vaddhw_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubhw :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">;<br class="">+<br class="">+def int_hexagon_V6_vsubhw_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vadduhw :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">;<br class="">+<br class="">+def int_hexagon_V6_vadduhw_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubuhw :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">;<br class="">+<br class="">+def int_hexagon_V6_vsubuhw_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vd0 :<br class="">+Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">;<br class="">+<br class="">+def int_hexagon_V6_vd0_128B :<br class="">+Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddbq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">;<br class="">+<br class="">+def int_hexagon_V6_vaddbq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubbq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">;<br class="">+<br class="">+def int_hexagon_V6_vsubbq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddbnq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">;<br class="">+<br class="">+def int_hexagon_V6_vaddbnq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubbnq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">;<br class="">+<br class="">+def int_hexagon_V6_vsubbnq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddhq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">;<br class="">+<br class="">+def int_hexagon_V6_vaddhq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubhq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">;<br class="">+<br class="">+def int_hexagon_V6_vsubhq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddhnq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">;<br class="">+<br class="">+def int_hexagon_V6_vaddhnq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubhnq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">;<br class="">+<br class="">+def int_hexagon_V6_vsubhnq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddwq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">;<br class="">+<br class="">+def int_hexagon_V6_vaddwq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubwq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">;<br class="">+<br class="">+def int_hexagon_V6_vsubwq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddwnq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">;<br class="">+<br class="">+def int_hexagon_V6_vaddwnq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubwnq :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">;<br class="">+<br class="">+def int_hexagon_V6_vsubwnq_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabsh :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">;<br class="">+<br class="">+def int_hexagon_V6_vabsh_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabsh_sat :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">;<br class="">+<br class="">+def int_hexagon_V6_vabsh_sat_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabsw :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">;<br class="">+<br class="">+def int_hexagon_V6_vabsw_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabsw_sat :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">;<br class="">+<br class="">+def int_hexagon_V6_vabsw_sat_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpybv :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">;<br class="">+<br class="">+def int_hexagon_V6_vmpybv_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpybv_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpybv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyubv :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">;<br class="">+<br class="">+def int_hexagon_V6_vmpyubv_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyubv_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyubv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpybusv :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">;<br class="">+<br class="">+def int_hexagon_V6_vmpybusv_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpybusv_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpybusv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpabusv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">;<br class="">+<br class="">+def int_hexagon_V6_vmpabusv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpabuuv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">;<br class="">+<br class="">+def int_hexagon_V6_vmpabuuv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhv :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhv_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhv_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhv :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhv_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhv_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhv_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhvsrs :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhvsrs_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhus :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhus_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhus_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhus_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyih :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">;<br class="">+<br class="">+def int_hexagon_V6_vmpyih_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyih_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyih_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyewuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyewuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_rnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_rnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_sacc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_sacc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_rnd_sacc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_rnd_sacc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyieoh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyieoh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiewuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiewuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiowh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiowh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiewh_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiewh_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiewuh_acc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiewuh_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyub :<br class="">+Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">;<br class="">+<br class="">+def int_hexagon_V6_vmpyub_128B :<br class="">+Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyub_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyub_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpybus :<br class="">+Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">;<br class="">+<br class="">+def int_hexagon_V6_vmpybus_128B :<br class="">+Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpybus_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpybus_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpabus :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">;<br class="">+<br class="">+def int_hexagon_V6_vmpabus_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpabus_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpabus_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpahb :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">;<br class="">+<br class="">+def int_hexagon_V6_vmpahb_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpahb_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpahb_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyh :<br class="">+Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyh_128B :<br class="">+Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhsat_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhsat_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhss :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhss_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhsrs :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">;<br class="">+<br class="">+def int_hexagon_V6_vmpyhsrs_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuh :<br class="">+Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuh_128B :<br class="">+Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuh_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuh_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyihb :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">;<br class="">+<br class="">+def int_hexagon_V6_vmpyihb_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyihb_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyihb_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwb :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwb_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwb_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwb_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwh :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwh_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwh_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwh_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vand :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">;<br class="">+<br class="">+def int_hexagon_V6_vand_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">;<br class="">+<br class="">+def int_hexagon_V6_vor :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">;<br class="">+<br class="">+def int_hexagon_V6_vor_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vxor :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">;<br class="">+<br class="">+def int_hexagon_V6_vxor_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnot :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">;<br class="">+<br class="">+def int_hexagon_V6_vnot_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandqrt :<br class="">+Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt">;<br class="">+<br class="">+def int_hexagon_V6_vandqrt_128B :<br class="">+Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandqrt_acc :<br class="">+Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">;<br class="">+<br class="">+def int_hexagon_V6_vandqrt_acc_128B :<br class="">+Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandvrt :<br class="">+Hexagon_v512i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">;<br class="">+<br class="">+def int_hexagon_V6_vandvrt_128B :<br class="">+Hexagon_v1024i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandvrt_acc :<br class="">+Hexagon_v512i1_v512i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">;<br class="">+<br class="">+def int_hexagon_V6_vandvrt_acc_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtw :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">;<br class="">+<br class="">+def int_hexagon_V6_vgtw_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqw :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">;<br class="">+<br class="">+def int_hexagon_V6_veqw_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqw_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">;<br class="">+<br class="">+def int_hexagon_V6_veqw_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqw_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">;<br class="">+<br class="">+def int_hexagon_V6_veqw_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqw_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">;<br class="">+<br class="">+def int_hexagon_V6_veqw_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgth :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">;<br class="">+<br class="">+def int_hexagon_V6_vgth_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgth_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">;<br class="">+<br class="">+def int_hexagon_V6_vgth_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgth_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">;<br class="">+<br class="">+def int_hexagon_V6_vgth_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgth_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">;<br class="">+<br class="">+def int_hexagon_V6_vgth_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqh :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">;<br class="">+<br class="">+def int_hexagon_V6_veqh_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqh_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">;<br class="">+<br class="">+def int_hexagon_V6_veqh_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqh_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">;<br class="">+<br class="">+def int_hexagon_V6_veqh_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqh_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">;<br class="">+<br class="">+def int_hexagon_V6_veqh_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtb :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">;<br class="">+<br class="">+def int_hexagon_V6_vgtb_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqb :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">;<br class="">+<br class="">+def int_hexagon_V6_veqb_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqb_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">;<br class="">+<br class="">+def int_hexagon_V6_veqb_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqb_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">;<br class="">+<br class="">+def int_hexagon_V6_veqb_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_veqb_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">;<br class="">+<br class="">+def int_hexagon_V6_veqb_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">;<br class="">+<br class="">+def int_hexagon_V6_vgtuw_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">;<br class="">+<br class="">+def int_hexagon_V6_vgtuh_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtub :<br class="">+Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_128B :<br class="">+Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_and :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_or :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_xor :<br class="">+Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">;<br class="">+<br class="">+def int_hexagon_V6_vgtub_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_or :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or">;<br class="">+<br class="">+def int_hexagon_V6_pred_or_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_and :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and">;<br class="">+<br class="">+def int_hexagon_V6_pred_and_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_not :<br class="">+Hexagon_v512i1_v512i1_Intrinsic<"HEXAGON_V6_pred_not">;<br class="">+<br class="">+def int_hexagon_V6_pred_not_128B :<br class="">+Hexagon_v1024i1_v1024i1_Intrinsic<"HEXAGON_V6_pred_not_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_xor :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_xor">;<br class="">+<br class="">+def int_hexagon_V6_pred_xor_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_and_n :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and_n">;<br class="">+<br class="">+def int_hexagon_V6_pred_and_n_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_or_n :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or_n">;<br class="">+<br class="">+def int_hexagon_V6_pred_or_n_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_scalar2 :<br class="">+Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">;<br class="">+<br class="">+def int_hexagon_V6_pred_scalar2_128B :<br class="">+Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmux :<br class="">+Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">;<br class="">+<br class="">+def int_hexagon_V6_vmux_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">;<br class="">+<br class="">+def int_hexagon_V6_vswap :<br class="">+Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">;<br class="">+<br class="">+def int_hexagon_V6_vswap_128B :<br class="">+Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmaxub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">;<br class="">+<br class="">+def int_hexagon_V6_vmaxub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vminub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">;<br class="">+<br class="">+def int_hexagon_V6_vminub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmaxuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">;<br class="">+<br class="">+def int_hexagon_V6_vmaxuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vminuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">;<br class="">+<br class="">+def int_hexagon_V6_vminuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmaxh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">;<br class="">+<br class="">+def int_hexagon_V6_vmaxh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vminh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">;<br class="">+<br class="">+def int_hexagon_V6_vminh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmaxw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">;<br class="">+<br class="">+def int_hexagon_V6_vmaxw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vminw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">;<br class="">+<br class="">+def int_hexagon_V6_vminw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsathub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">;<br class="">+<br class="">+def int_hexagon_V6_vsathub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsatwh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">;<br class="">+<br class="">+def int_hexagon_V6_vsatwh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshuffeb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">;<br class="">+<br class="">+def int_hexagon_V6_vshuffeb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshuffob :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">;<br class="">+<br class="">+def int_hexagon_V6_vshuffob_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshufeh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">;<br class="">+<br class="">+def int_hexagon_V6_vshufeh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshufoh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">;<br class="">+<br class="">+def int_hexagon_V6_vshufoh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshuffvdd :<br class="">+Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">;<br class="">+<br class="">+def int_hexagon_V6_vshuffvdd_128B :<br class="">+Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdealvdd :<br class="">+Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">;<br class="">+<br class="">+def int_hexagon_V6_vdealvdd_128B :<br class="">+Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshufoeh :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">;<br class="">+<br class="">+def int_hexagon_V6_vshufoeh_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshufoeb :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">;<br class="">+<br class="">+def int_hexagon_V6_vshufoeb_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdealh :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">;<br class="">+<br class="">+def int_hexagon_V6_vdealh_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdealb :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">;<br class="">+<br class="">+def int_hexagon_V6_vdealb_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdealb4w :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">;<br class="">+<br class="">+def int_hexagon_V6_vdealb4w_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshuffh :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">;<br class="">+<br class="">+def int_hexagon_V6_vshuffh_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vshuffb :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">;<br class="">+<br class="">+def int_hexagon_V6_vshuffb_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">;<br class="">+<br class="">+def int_hexagon_V6_extractw :<br class="">+Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">;<br class="">+<br class="">+def int_hexagon_V6_extractw_128B :<br class="">+Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vinsertwr :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">;<br class="">+<br class="">+def int_hexagon_V6_vinsertwr_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;<br class="">+<br class="">+def int_hexagon_V6_lvsplatw :<br class="">+Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">;<br class="">+<br class="">+def int_hexagon_V6_lvsplatw_128B :<br class="">+Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vassignp :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">;<br class="">+<br class="">+def int_hexagon_V6_vassignp_128B :<br class="">+Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">;<br class="">+<br class="">+def int_hexagon_V6_vassign :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">;<br class="">+<br class="">+def int_hexagon_V6_vassign_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">;<br class="">+<br class="">+def int_hexagon_V6_vcombine :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">;<br class="">+<br class="">+def int_hexagon_V6_vcombine_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdelta :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">;<br class="">+<br class="">+def int_hexagon_V6_vdelta_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrdelta :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">;<br class="">+<br class="">+def int_hexagon_V6_vrdelta_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">;<br class="">+<br class="">+def int_hexagon_V6_vcl0w :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">;<br class="">+<br class="">+def int_hexagon_V6_vcl0w_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">;<br class="">+<br class="">+def int_hexagon_V6_vcl0h :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">;<br class="">+<br class="">+def int_hexagon_V6_vcl0h_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnormamtw :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">;<br class="">+<br class="">+def int_hexagon_V6_vnormamtw_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnormamth :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">;<br class="">+<br class="">+def int_hexagon_V6_vnormamth_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">;<br class="">+<br class="">+def int_hexagon_V6_vpopcounth :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">;<br class="">+<br class="">+def int_hexagon_V6_vpopcounth_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_oracc :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_oracc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh :<br class="">+Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_128B :<br class="">+Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_oracc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_oracc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;<br class="">+<br class="">+def int_hexagon_V6_hi :<br class="">+Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">;<br class="">+<br class="">+def int_hexagon_V6_hi_128B :<br class="">+Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">;<br class="">+<br class="">+def int_hexagon_V6_lo :<br class="">+Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">;<br class="">+<br class="">+def int_hexagon_V6_lo_128B :<br class="">+Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">;<br class="">+<br class="">+// V62 HVX Instructions.<br class="">+<br class="">+def int_hexagon_V6_vlsrb :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">;<br class="">+<br class="">+def int_hexagon_V6_vlsrb_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrwuhrndsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrwuhrndsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasruwuhrndsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;<br class="">+<br class="">+def int_hexagon_V6_vasruwuhrndsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrhbsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">;<br class="">+<br class="">+def int_hexagon_V6_vasrhbsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrounduwuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">;<br class="">+<br class="">+def int_hexagon_V6_vrounduwuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vrounduhub :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">;<br class="">+<br class="">+def int_hexagon_V6_vrounduhub_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vadduwsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">;<br class="">+<br class="">+def int_hexagon_V6_vadduwsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vadduwsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vadduwsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubuwsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">;<br class="">+<br class="">+def int_hexagon_V6_vsubuwsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubuwsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubuwsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddbsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">;<br class="">+<br class="">+def int_hexagon_V6_vaddbsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddbsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vaddbsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubbsat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">;<br class="">+<br class="">+def int_hexagon_V6_vsubbsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubbsat_dv :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;<br class="">+<br class="">+def int_hexagon_V6_vsubbsat_dv_128B :<br class="">+Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddcarry :<br class="">+Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;<br class="">+<br class="">+def int_hexagon_V6_vaddcarry_128B :<br class="">+Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;<br class="">+<br class="">+def int_hexagon_V6_vsubcarry :<br class="">+Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;<br class="">+<br class="">+def int_hexagon_V6_vsubcarry_128B :<br class="">+Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;<br class="">+<br class="">+def int_hexagon_V6_vaddububb_sat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">;<br class="">+<br class="">+def int_hexagon_V6_vaddububb_sat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsubububb_sat :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">;<br class="">+<br class="">+def int_hexagon_V6_vsubububb_sat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddhw_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">;<br class="">+<br class="">+def int_hexagon_V6_vaddhw_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vadduhw_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">;<br class="">+<br class="">+def int_hexagon_V6_vadduhw_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddubh_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vaddubh_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyewuh_64 :<br class="">+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;<br class="">+<br class="">+def int_hexagon_V6_vmpyewuh_64_128B :<br class="">+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_64_acc :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyowh_64_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpauhb :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">;<br class="">+<br class="">+def int_hexagon_V6_vmpauhb_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpauhb_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpauhb_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwub :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwub_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwub_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyiwub_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandnqrt :<br class="">+Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">;<br class="">+<br class="">+def int_hexagon_V6_vandnqrt_128B :<br class="">+Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandnqrt_acc :<br class="">+Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;<br class="">+<br class="">+def int_hexagon_V6_vandnqrt_acc_128B :<br class="">+Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandvqv :<br class="">+Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">;<br class="">+<br class="">+def int_hexagon_V6_vandvqv_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">;<br class="">+<br class="">+def int_hexagon_V6_vandvnqv :<br class="">+Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">;<br class="">+<br class="">+def int_hexagon_V6_vandvnqv_128B :<br class="">+Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;<br class="">+<br class="">+def int_hexagon_V6_pred_scalar2v2 :<br class="">+Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;<br class="">+<br class="">+def int_hexagon_V6_pred_scalar2v2_128B :<br class="">+Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;<br class="">+<br class="">+def int_hexagon_V6_shuffeqw :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqw">;<br class="">+<br class="">+def int_hexagon_V6_shuffeqw_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;<br class="">+<br class="">+def int_hexagon_V6_shuffeqh :<br class="">+Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqh">;<br class="">+<br class="">+def int_hexagon_V6_shuffeqh_128B :<br class="">+Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmaxb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">;<br class="">+<br class="">+def int_hexagon_V6_vmaxb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vminb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">;<br class="">+<br class="">+def int_hexagon_V6_vminb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsatuwuh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">;<br class="">+<br class="">+def int_hexagon_V6_vsatuwuh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;<br class="">+<br class="">+def int_hexagon_V6_lvsplath :<br class="">+Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">;<br class="">+<br class="">+def int_hexagon_V6_lvsplath_128B :<br class="">+Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">;<br class="">+<br class="">+def int_hexagon_V6_lvsplatb :<br class="">+Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">;<br class="">+<br class="">+def int_hexagon_V6_lvsplatb_128B :<br class="">+Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddclbw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">;<br class="">+<br class="">+def int_hexagon_V6_vaddclbw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddclbh :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">;<br class="">+<br class="">+def int_hexagon_V6_vaddclbh_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlutvvbi :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvvbi_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_oracci :<br class="">+Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_oracci_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvwhi :<br class="">+Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvwhi_128B :<br class="">+Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg<2>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_oracci :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_oracci_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg<3>]>;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_nm :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;<br class="">+<br class="">+def int_hexagon_V6_vlutvvb_nm_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_nm :<br class="">+Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;<br class="">+<br class="">+def int_hexagon_V6_vlutvwh_nm_128B :<br class="">+Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;<br class="">+<br class="">+// V65 HVX Instructions.<br class="">+<br class="">+def int_hexagon_V6_vasruwuhsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">;<br class="">+<br class="">+def int_hexagon_V6_vasruwuhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasruhubsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">;<br class="">+<br class="">+def int_hexagon_V6_vasruhubsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasruhubrndsat :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;<br class="">+<br class="">+def int_hexagon_V6_vasruhubrndsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaslh_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vaslh_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasrh_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vasrh_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavguw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">;<br class="">+<br class="">+def int_hexagon_V6_vavguw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavguwrnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">;<br class="">+<br class="">+def int_hexagon_V6_vavguwrnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">;<br class="">+<br class="">+def int_hexagon_V6_vavgb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vavgbrnd :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">;<br class="">+<br class="">+def int_hexagon_V6_vavgbrnd_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;<br class="">+<br class="">+def int_hexagon_V6_vnavgb :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">;<br class="">+<br class="">+def int_hexagon_V6_vnavgb_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vdd0 :<br class="">+Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">;<br class="">+<br class="">+def int_hexagon_V6_vdd0_128B :<br class="">+Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabsb :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">;<br class="">+<br class="">+def int_hexagon_V6_vabsb_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vabsb_sat :<br class="">+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">;<br class="">+<br class="">+def int_hexagon_V6_vabsb_sat_128B :<br class="">+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpabuu :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">;<br class="">+<br class="">+def int_hexagon_V6_vmpabuu_128B :<br class="">+Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpabuu_acc :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpabuu_acc_128B :<br class="">+Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyh_acc :<br class="">+Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyh_acc_128B :<br class="">+Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpahhsat :<br class="">+Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">;<br class="">+<br class="">+def int_hexagon_V6_vmpahhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpauhuhsat :<br class="">+Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;<br class="">+<br class="">+def int_hexagon_V6_vmpauhuhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpsuhuhsat :<br class="">+Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;<br class="">+<br class="">+def int_hexagon_V6_vmpsuhuhsat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vlut4 :<br class="">+Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">;<br class="">+<br class="">+def int_hexagon_V6_vlut4_128B :<br class="">+Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhe :<br class="">+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhe_128B :<br class="">+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhe_acc :<br class="">+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;<br class="">+<br class="">+def int_hexagon_V6_vmpyuhe_acc_128B :<br class="">+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;<br class="">+<br class="">+def int_hexagon_V6_vgathermw :<br class="">+Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermw_128B :<br class="">+Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermh :<br class="">+Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermh_128B :<br class="">+Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermhw :<br class="">+Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermhw_128B :<br class="">+Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermwq :<br class="">+Hexagon__ptrv512i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermwq", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermwq_128B :<br class="">+Hexagon__ptrv1024i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermwq_128B", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermhq :<br class="">+Hexagon__ptrv512i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermhq", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermhq_128B :<br class="">+Hexagon__ptrv1024i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhq_128B", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermhwq :<br class="">+Hexagon__ptrv512i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhwq", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vgathermhwq_128B :<br class="">+Hexagon__ptrv1024i1i32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhwq_128B", [IntrArgMemOnly]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermw :<br class="">+Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermw_128B :<br class="">+Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermh :<br class="">+Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermh_128B :<br class="">+Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermw_add :<br class="">+Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermw_add_128B :<br class="">+Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermh_add :<br class="">+Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermh_add_128B :<br class="">+Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermwq :<br class="">+Hexagon__v512i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermwq", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermwq_128B :<br class="">+Hexagon__v1024i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermwq_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhq :<br class="">+Hexagon__v512i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhq", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhq_128B :<br class="">+Hexagon__v1024i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhq_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhw :<br class="">+Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhw_128B :<br class="">+Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhwq :<br class="">+Hexagon__v512i1i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhwq", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhwq_128B :<br class="">+Hexagon__v1024i1i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhwq_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhw_add :<br class="">+Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vscattermhw_add_128B :<br class="">+Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>;<br class="">+<br class="">+def int_hexagon_V6_vprefixqb :<br class="">+Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqb">;<br class="">+<br class="">+def int_hexagon_V6_vprefixqb_128B :<br class="">+Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;<br class="">+<br class="">+def int_hexagon_V6_vprefixqh :<br class="">+Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqh">;<br class="">+<br class="">+def int_hexagon_V6_vprefixqh_128B :<br class="">+Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;<br class="">+<br class="">+def int_hexagon_V6_vprefixqw :<br class="">+Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqw">;<br class="">+<br class="">+def int_hexagon_V6_vprefixqw_128B :<br class="">+Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;<br class="">+<br class="">+// V66 HVX Instructions.<br class="">+<br class="">+def int_hexagon_V6_vrotr :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">;<br class="">+<br class="">+def int_hexagon_V6_vrotr_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">;<br class="">+<br class="">+def int_hexagon_V6_vasr_into :<br class="">+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">;<br class="">+<br class="">+def int_hexagon_V6_vasr_into_128B :<br class="">+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">;<br class="">+<br class="">+def int_hexagon_V6_vaddcarrysat :<br class="">+Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">;<br class="">+<br class="">+def int_hexagon_V6_vaddcarrysat_128B :<br class="">+Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">;<br class="">+<br class="">+def int_hexagon_V6_vsatdw :<br class="">+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">;<br class="">+<br class="">+def int_hexagon_V6_vsatdw_128B :<br class="">+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">;<br class="">+<br class=""><br class="">diff --git a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td<br class="">index ea9be4589600..d8762e7df313 100644<br class="">--- a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td<br class="">+++ b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td<br class="">@@ -1,2750 +1,2623 @@<br class="">-//===-------------------------------------------------------*- tablegen -*-===//<br class="">+//===----------------------------------------------------------------------===//<br class=""> //<br class=""> // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.<br class=""> // See <a href="https://llvm.org/LICENSE.txt" class="">https://llvm.org/LICENSE.txt</a> for license information.<br class=""> // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception<br class=""> //<br class=""> //===----------------------------------------------------------------------===//<br class="">-// Automatically generated file, please consult code owner before editing.<br class="">+// Automatically generated file, do not edit!<br class=""> //===----------------------------------------------------------------------===//<br class=""><br class=""><br class=""> // V5 Scalar Instructions.<br class=""><br class="">-def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1),<br class="">- (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2),<br class="">- (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1),<br class="">- (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1),<br class="">- (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_brevp DoubleRegs:$src1),<br class="">- (S2_brevp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1),<br class="">- (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2),<br class="">- (C4_cmplte IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1),<br class="">- (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),<br class="">- (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C2_cmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C2_cmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_C2_cmpgtu IntRegs:$src1, IntRegs:$src2),<br class="">- (C2_cmpgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (C2_cmpgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">- (A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1),<br class="">- (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cmpheq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1),<br class="">- (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_not PredRegs:$src1),<br class="">- (C2_not PredRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_tfrpr PredRegs:$src1),<br class="">- (C2_tfrpr PredRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cmpbgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class=""> (A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C2_bitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C2_bitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C4_nbitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C4_nbitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C4_cmpneq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C4_cmplte IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (C4_cmplteu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_tfrpr (C2_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_tfrpr (C2_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_tfrpr (C2_xor (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_tfrpr (C2_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_not PredRegs:$src1),<br class="">+ (C2_tfrpr (C2_not (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_tfrpr (C2_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_and_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_and_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_or_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_or_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_and_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_and_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_or_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">+ (C2_tfrpr (C4_or_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1),<br class="">+ (C2_tfrpr (C2_pxfer_map (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_any8 PredRegs:$src1),<br class="">+ (C2_tfrpr (C2_any8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_all8 PredRegs:$src1),<br class="">+ (C2_tfrpr (C2_all8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_vitpack (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (C2_mux (C2_tfrrp PredRegs:$src1), IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3),<br class="">+ (C2_muxii (C2_tfrrp PredRegs:$src1), s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">+ (C2_muxir (C2_tfrrp PredRegs:$src1), IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3),<br class="">+ (C2_muxri (C2_tfrrp PredRegs:$src1), s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (C2_vmux (C2_tfrrp PredRegs:$src1), DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_mask PredRegs:$src1),<br class="">+ (C2_mask (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_cmpbeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_cmpbgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2),<br class="">- (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1),<br class="">- (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_pxorf PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (A2_pxorf PredRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),<br class="">- (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_all8 PredRegs:$src1),<br class="">- (C2_all8 PredRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2),<br class="">- (C2_bitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpysip IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">- (M2_mpysip IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpysin IntRegs:$src1, u8_0ImmPred_timm:$src2),<br class="">- (M2_mpysin IntRegs:$src1, u8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_cmpheq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_cmphgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_cmphgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A4_boundscheck IntRegs:$src1, DoubleRegs:$src2),<br class="">- (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_tfrpr PredRegs:$src1),<br class="">+ (C2_tfrpr (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C2_tfrrp IntRegs:$src1),<br class="">+ (C2_tfrpr (C2_tfrrp IntRegs:$src1))>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_C4_fastcorner9 PredRegs:$src1, PredRegs:$src2),<br class="">- (C4_fastcorner9 PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2),<br class="">- (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1),<br class="">- (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1),<br class="">- (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),<br class="">- (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1),<br class="">- (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">- (C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1),<br class="">- (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1),<br class="">- (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1),<br class="">- (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_any8 PredRegs:$src1),<br class="">- (C2_any8 PredRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1),<br class="">- (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1),<br class="">- (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+ (C2_tfrpr (C4_fastcorner9 (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2),<br class="">+ (C2_tfrpr (C4_fastcorner9_not (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2),<br class="">- (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred_timm:$src1),<br class="">- (A2_tfrsi s32_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2),<br class="">- (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_negsat IntRegs:$src1),<br class="">- (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1),<br class="">- (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">- (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_tfrpcp DoubleRegs:$src1),<br class="">- (A4_tfrpcp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1),<br class="">- (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_zxth IntRegs:$src1),<br class="">- (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1),<br class="">- (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_addp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),<br class="">- (A4_addp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2),<br class="">- (C2_xor PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1),<br class="">- (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1),<br class="">- (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1),<br class="">- (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_sxth IntRegs:$src1),<br class="">- (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1),<br class="">- (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1),<br class="">- (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vabs<br class="">diff h DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vabs<br class="">diff h DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1),<br class="">- (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vabs<br class="">diff w DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vabs<br class="">diff w DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1),<br class="">- (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3),<br class="">- (S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_tstbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3),<br class="">- (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1),<br class="">- (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1),<br class="">- (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3),<br class="">- (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1),<br class="">- (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_ct0 IntRegs:$src1),<br class="">- (S2_ct0 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1),<br class="">- (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2),<br class="">- (C2_andn PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">- (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_combineii s8_0ImmPred_timm:$src1, u32_0ImmPred_timm:$src2),<br class="">- (A4_combineii s8_0ImmPred_timm:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2),<br class="">- (A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2),<br class="">- (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1),<br class="">- (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2),<br class="">- (C4_nbitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class=""> (M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class=""> (M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred_timm:$src1),<br class="">- (F2_sfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred_timm:$src1),<br class="">- (F2_sfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1),<br class="">- (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2),<br class="">- (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1),<br class="">- (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_minu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">- (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfcmpge IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2),<br class="">- (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_roundsat DoubleRegs:$src1),<br class="">- (A2_roundsat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_ct1p DoubleRegs:$src1),<br class="">- (S2_ct1p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">- (C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_tfrcpp CtrRegs64:$src1),<br class="">- (A4_tfrcpp CtrRegs64:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cmphgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_sath IntRegs:$src1),<br class="">- (A2_sath IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_satb IntRegs:$src1),<br class="">- (A2_satb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4),<br class="">- (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_asrh IntRegs:$src1),<br class="">- (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2),<br class="">- (C2_or PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfinvsqrta IntRegs:$src1),<br class="">- (F2_sfinvsqrta IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_ct0p DoubleRegs:$src1),<br class="">- (S2_ct0p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svaddh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svaddh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_aslh IntRegs:$src1),<br class="">- (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1),<br class="">- (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1),<br class="">- (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3),<br class="">- (C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1),<br class="">- (C2_pxfer_map PredRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2),<br class="">+ (M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3),<br class=""> (M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfrcrr CtrRegs:$src1),<br class="">- (A2_tfrcrr CtrRegs:$src1)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3),<br class=""> (M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2),<br class="">- (C2_orn PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_mask PredRegs:$src1),<br class="">- (C2_mask PredRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2),<br class=""> (M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfrrcr IntRegs:$src1),<br class="">- (A2_tfrrcr IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class=""> (M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1),<br class="">- (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2),<br class="">- (C2_cmpgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1),<br class="">- (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1),<br class="">- (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3),<br class="">- (S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1),<br class="">- (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class=""> (M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2uw IntRegs:$src1),<br class="">- (F2_conv_sf2uw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2ud IntRegs:$src1),<br class="">- (F2_conv_sf2ud IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2uw_chop IntRegs:$src1),<br class="">- (F2_conv_sf2uw_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1),<br class="">- (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2),<br class="">- (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_subp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),<br class="">- (A4_subp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2),<br class="">- (C2_vitpack PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),<br class="">- (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2),<br class="">- (C4_nbitsclr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2),<br class="">- (C2_and PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1),<br class="">- (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1),<br class="">- (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2),<br class="">- (C4_cmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">+ (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3),<br class="">+ (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3),<br class="">+ (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class=""> (M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_clb IntRegs:$src1),<br class="">- (S2_clb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class=""> (M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1),<br class="">- (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred_timm:$src1),<br class="">- (F2_dfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cmphgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred_timm:$src1),<br class="">- (F2_dfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3),<br class="">- (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class=""> (M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3),<br class="">- (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2),<br class="">+ (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2),<br class="">+ (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class=""> (M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfrecipa IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfrecipa IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2),<br class="">- (A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2),<br class="">- (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2),<br class="">- (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2),<br class="">- (C2_cmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1),<br class="">- (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1),<br class="">- (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_satuh IntRegs:$src1),<br class="">- (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_satub IntRegs:$src1),<br class="">- (A2_satub IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2),<br class=""> (M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">- (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2),<br class="">- (C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2),<br class="">- (A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2),<br class="">- (A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3),<br class="">- (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1),<br class="">- (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1),<br class="">- (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1),<br class="">- (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2),<br class="">- (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3),<br class="">- (C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">- (C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_swiz IntRegs:$src1),<br class="">- (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2),<br class="">- (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1),<br class="">- (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1),<br class="">- (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_tfr IntRegs:$src1),<br class="">- (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2),<br class="">- (A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2),<br class="">- (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_brev IntRegs:$src1),<br class="">- (S2_brev IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">- (S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">- (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1),<br class="">- (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4),<br class="">- (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1),<br class="">- (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2),<br class="">- (M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1),<br class="">- (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1),<br class="">- (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1),<br class="">- (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1),<br class="">- (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">- (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1),<br class="">- (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1),<br class="">- (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1),<br class="">- (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2),<br class="">- (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4),<br class="">- (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1),<br class="">- (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1),<br class="">- (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2),<br class="">- (C4_cmplteu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),<br class="">- (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2),<br class="">- (S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">- (S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class=""> (M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_tfrrp IntRegs:$src1),<br class="">- (C2_tfrrp IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_abs IntRegs:$src1),<br class="">- (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cmpbeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1),<br class="">- (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsatwuh DoubleRegs:$src1),<br class="">- (S2_vsatwuh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1),<br class="">- (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2),<br class="">- (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3),<br class="">- (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2),<br class="">- (S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1),<br class="">- (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_parity IntRegs:$src1, IntRegs:$src2),<br class="">- (S4_parity IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">- (A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1),<br class="">- (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">- (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class="">- (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class=""> (M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2),<br class="">- (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1),<br class="">- (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2),<br class="">+ (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class=""> (M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2),<br class="">- (C2_bitsclr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2),<br class="">- (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),<br class="">- (C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4),<br class="">+ (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3),<br class="">+ (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2),<br class="">+ (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2),<br class="">+ (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2),<br class=""> (A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class=""> def: Pat<(int_hexagon_A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2),<br class=""> (A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2),<br class="">- (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">- (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">-def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">-<br class="">-// V55 Scalar Instructions.<br class="">-<br class="">-def: Pat<(int_hexagon_A5_ACS DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">- (A5_ACS DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV55]>;<br class="">-<br class="">-// V60 Scalar Instructions.<br class="">-<br class="">-def: Pat<(int_hexagon_S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">- (S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-def: Pat<(int_hexagon_S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">- (S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">-<br class="">-// V62 Scalar Instructions.<br class="">-<br class="">-def: Pat<(int_hexagon_S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">-def: Pat<(int_hexagon_V6_ldntnt0 IntRegs:$src1),<br class="">- (V6_ldntnt0 IntRegs:$src1)>, Requires<[HasV62]>;<br class="">-def: Pat<(int_hexagon_M6_vabs<br class="">diff ub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M6_vabs<br class="">diff ub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">-def: Pat<(int_hexagon_S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">-def: Pat<(int_hexagon_M6_vabs<br class="">diff b DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (M6_vabs<br class="">diff b DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">-def: Pat<(int_hexagon_A6_vminub_RdP DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A6_vminub_RdP DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">-def: Pat<(int_hexagon_S6_vsplatrbp IntRegs:$src1),<br class="">- (S6_vsplatrbp IntRegs:$src1)>, Requires<[HasV62]>;<br class="">-<br class="">-// V65 Scalar Instructions.<br class="">-<br class="">-def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>;<br class="">-<br class="">-// V66 Scalar Instructions.<br class="">-<br class="">-def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>;<br class="">-def: Pat<(int_hexagon_F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2),<br class="">- (F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>;<br class="">-def: Pat<(int_hexagon_M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">- (M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV66]>;<br class="">-def: Pat<(int_hexagon_S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2),<br class="">- (S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV66]>;<br class="">-<br class="">-// V60 HVX Instructions.<br class="">-<br class="">-def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsathub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsathub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">- (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">- (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsuisat_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">- (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">- (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundhb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundhb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackeb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackeb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vtran2x2_map_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackob HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackob_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_lo HvxWR:$src1),<br class="">- (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1),<br class="">- (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldu0 IntRegs:$src1),<br class="">- (V6_ldu0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldu0_128B IntRegs:$src1),<br class="">- (V6_ldu0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_aslh IntRegs:$src1),<br class="">+ (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_asrh IntRegs:$src1),<br class="">+ (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_negsat IntRegs:$src1),<br class="">+ (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_abs IntRegs:$src1),<br class="">+ (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),<br class="">+ (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1),<br class="">+ (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1),<br class="">+ (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),<br class="">+ (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_minu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_tfr IntRegs:$src1),<br class="">+ (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred_timm:$src1),<br class="">+ (A2_tfrsi s32_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1),<br class="">+ (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1),<br class="">+ (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1),<br class="">+ (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_zxth IntRegs:$src1),<br class="">+ (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_sxth IntRegs:$src1),<br class="">+ (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2),<br class="">+ (A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2),<br class="">+ (A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2),<br class="">+ (A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2),<br class="">+ (A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">+ (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3),<br class="">+ (S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">+ (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">+ (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),<br class="">+ (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2),<br class="">+ (A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2),<br class="">+ (A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1),<br class="">+ (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1),<br class="">+ (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1),<br class="">+ (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_roundsat DoubleRegs:$src1),<br class="">+ (A2_roundsat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_sath IntRegs:$src1),<br class="">+ (A2_sath IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_satuh IntRegs:$src1),<br class="">+ (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_satub IntRegs:$src1),<br class="">+ (A2_satub IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_satb IntRegs:$src1),<br class="">+ (A2_satb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svaddh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svaddh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2),<br class="">+ (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1),<br class="">+ (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1),<br class="">+ (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1),<br class="">+ (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1),<br class="">+ (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vabs<br class="">diff w DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vabs<br class="">diff w DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_M2_vabs<br class="">diff h DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M2_vabs<br class="">diff h DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4),<br class="">+ (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, (C2_tfrrp PredRegs:$src4))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (F2_sfcmpge IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred_timm:$src1),<br class="">+ (F2_sfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred_timm:$src1),<br class="">+ (F2_sfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2),<br class="">+ (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1),<br class="">+ (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred_timm:$src1),<br class="">+ (F2_dfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred_timm:$src1),<br class="">+ (F2_dfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1),<br class="">+ (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1),<br class="">+ (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1),<br class="">+ (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1),<br class="">+ (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1),<br class="">+ (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1),<br class="">+ (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1),<br class="">+ (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1),<br class="">+ (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1),<br class="">+ (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1),<br class="">+ (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2uw IntRegs:$src1),<br class="">+ (F2_conv_sf2uw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1),<br class="">+ (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2ud IntRegs:$src1),<br class="">+ (F2_conv_sf2ud IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1),<br class="">+ (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1),<br class="">+ (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1),<br class="">+ (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1),<br class="">+ (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1),<br class="">+ (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2uw_chop IntRegs:$src1),<br class="">+ (F2_conv_sf2uw_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1),<br class="">+ (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1),<br class="">+ (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1),<br class="">+ (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1),<br class="">+ (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1),<br class="">+ (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1),<br class="">+ (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1),<br class="">+ (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br class="">+ (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2),<br class="">+ (S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),<br class="">+ (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),<br class="">+ (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1),<br class="">+ (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1),<br class="">+ (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),<br class="">+ (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2),<br class="">+ (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4),<br class="">+ (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3),<br class="">+ (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br class="">+ (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (C2_tfrpr (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (S2_tstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (C2_tfrpr (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">+ (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">+ (S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2),<br class="">+ (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2),<br class="">+ (S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1),<br class="">+ (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1),<br class="">+ (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1),<br class="">+ (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1),<br class="">+ (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1),<br class="">+ (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1),<br class="">+ (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1),<br class="">+ (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1),<br class="">+ (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1),<br class="">+ (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1),<br class="">+ (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1),<br class="">+ (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1),<br class="">+ (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1),<br class="">+ (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsatwuh DoubleRegs:$src1),<br class="">+ (S2_vsatwuh DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2),<br class="">+ (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_A2_swiz IntRegs:$src1),<br class="">+ (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1),<br class="">+ (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1),<br class="">+ (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1),<br class="">+ (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1),<br class="">+ (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1),<br class="">+ (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_parity IntRegs:$src1, IntRegs:$src2),<br class="">+ (S4_parity IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1),<br class="">+ (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2),<br class="">+ (S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1),<br class="">+ (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2),<br class="">+ (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_clb IntRegs:$src1),<br class="">+ (S2_clb IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1),<br class="">+ (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1),<br class="">+ (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1),<br class="">+ (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1),<br class="">+ (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1),<br class="">+ (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_brev IntRegs:$src1),<br class="">+ (S2_brev IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_brevp DoubleRegs:$src1),<br class="">+ (S2_brevp DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_ct0 IntRegs:$src1),<br class="">+ (S2_ct0 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1),<br class="">+ (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_ct0p DoubleRegs:$src1),<br class="">+ (S2_ct0p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_ct1p DoubleRegs:$src1),<br class="">+ (S2_ct1p DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1),<br class="">+ (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1),<br class="">+ (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y2_dcfetch IntRegs:$src1),<br class="">+ (Y2_dcfetch IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y2_dczeroa IntRegs:$src1),<br class="">+ (Y2_dczeroa IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y2_dccleana IntRegs:$src1),<br class="">+ (Y2_dccleana IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y2_dccleaninva IntRegs:$src1),<br class="">+ (Y2_dccleaninva IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y2_dcinva IntRegs:$src1),<br class="">+ (Y2_dcinva IntRegs:$src1)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y4_l2fetch IntRegs:$src1, IntRegs:$src2),<br class="">+ (Y4_l2fetch IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;<br class="">+def: Pat<(int_hexagon_Y5_l2fetch IntRegs:$src1, DoubleRegs:$src2),<br class="">+ (Y5_l2fetch IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;<br class="">+<br class="">+// V60 Scalar Instructions.<br class="">+<br class="">+def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2),<br class="">+ (S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+def: Pat<(int_hexagon_S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),<br class="">+ (S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>;<br class="">+<br class="">+// V62 Scalar Instructions.<br class="">+<br class="">+def: Pat<(int_hexagon_M6_vabs<br class="">diff b DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M6_vabs<br class="">diff b DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">+def: Pat<(int_hexagon_M6_vabs<br class="">diff ub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (M6_vabs<br class="">diff ub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">+def: Pat<(int_hexagon_S6_vsplatrbp IntRegs:$src1),<br class="">+ (S6_vsplatrbp IntRegs:$src1)>, Requires<[HasV62]>;<br class="">+def: Pat<(int_hexagon_S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">+def: Pat<(int_hexagon_S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>;<br class="">+<br class="">+// V65 Scalar Instructions.<br class="">+<br class="">+def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (C2_tfrpr (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV65]>;<br class="">+<br class="">+// V66 Scalar Instructions.<br class="">+<br class="">+def: Pat<(int_hexagon_M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br class="">+ (M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV66]>;<br class="">+def: Pat<(int_hexagon_F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>;<br class="">+def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2),<br class="">+ (F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>;<br class="">+def: Pat<(int_hexagon_S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2),<br class="">+ (S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV66]>;<br class="">+<br class="">+// V60 HVX Instructions.<br class="">+<br class="">+def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),<br class="">+ (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vlalignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsh HvxVR:$src1),<br class="">- (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1),<br class="">- (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsb HvxVR:$src1),<br class="">- (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsb_128B HvxVR:$src1),<br class="">- (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1),<br class="">- (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1),<br class="">- (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1),<br class="">- (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1),<br class="">- (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhisat_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vzh HvxVR:$src1),<br class="">- (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vzh_128B HvxVR:$src1),<br class="">- (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_valignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vror HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vror_128B HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1),<br class="">- (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1),<br class="">- (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1),<br class="">- (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1),<br class="">- (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1),<br class="">+ (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1),<br class="">+ (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1),<br class="">+ (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1),<br class="">+ (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1),<br class="">+ (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1),<br class="">+ (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1),<br class="">+ (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1),<br class="">+ (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2),<br class="">+ (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2),<br class="">+ (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2),<br class="">+ (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2),<br class="">+ (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackeb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackeb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackob HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackob_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vzb HvxVR:$src1),<br class=""> (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vzb_128B HvxVR:$src1),<br class=""> (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsb HvxVR:$src1),<br class="">+ (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsb_128B HvxVR:$src1),<br class="">+ (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vzh HvxVR:$src1),<br class="">+ (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vzh_128B HvxVR:$src1),<br class="">+ (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsh HvxVR:$src1),<br class="">+ (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1),<br class="">+ (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpybus HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpybus_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2),<br class=""> (V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vdmpybus_dv_128B HvxWR:$src1, IntRegs:$src2),<br class=""> (V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpybus_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_dv_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhisat_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsuisat_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vtmpyb HvxWR:$src1, IntRegs:$src2),<br class=""> (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vtmpyb_128B HvxWR:$src1, IntRegs:$src2),<br class=""> (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vrmpyubv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">+ (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">+ (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">+ (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">+ (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybus HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybus_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">+ (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">+ (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">+ (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">+ (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrmpybusv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">+ (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">+ (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">+ (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">+ (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vaslw HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vaslw_128B HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1),<br class="">- (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1),<br class="">- (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2),<br class="">- (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2),<br class="">- (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2),<br class="">- (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2),<br class="">- (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vasrwhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff h HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff h HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff h_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff h HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1),<br class="">- (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1),<br class="">- (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1),<br class="">- (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1),<br class="">- (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2),<br class="">- (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2),<br class="">- (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_hi HvxWR:$src1),<br class="">- (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1),<br class="">- (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vasrwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundhb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundhb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundhub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vroundhub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubw HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubw_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubw_dv HvxWR:$src1, HvxWR:$src2),<br class=""> (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubw_dv_128B HvxWR:$src1, HvxWR:$src2),<br class=""> (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybus HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybus_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubhsat HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubhsat_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">- (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">- (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1),<br class="">- (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1),<br class="">- (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2),<br class=""> (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vaddwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class=""> (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1),<br class="">- (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1),<br class="">- (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff ub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff ub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff ub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff ub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff uh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff uh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff uh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff uh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff h HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff h HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff h_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff h HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff w HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabs<br class="">diff w_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vabs<br class="">diff w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vd0 ),<br class="">+ (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vd0_128B ),<br class="">+ (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">- (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">- (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffb HvxVR:$src1),<br class="">- (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffb_128B HvxVR:$src1),<br class="">- (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1),<br class="">- (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1),<br class="">- (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhus_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1),<br class="">+ (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1),<br class="">+ (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1),<br class="">+ (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1),<br class="">+ (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1),<br class="">+ (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1),<br class="">+ (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1),<br class="">+ (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1),<br class="">+ (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpybv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">- (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">- (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufeh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshufeh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyewuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyewuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpybus_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ld0 IntRegs:$src1),<br class="">- (V6_ld0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ld0_128B IntRegs:$src1),<br class="">- (V6_ld0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1),<br class="">- (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1),<br class="">- (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldnt0 IntRegs:$src1),<br class="">- (V6_ldnt0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldnt0_128B IntRegs:$src1),<br class="">- (V6_ldnt0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1),<br class="">- (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1),<br class="">- (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1),<br class="">- (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1),<br class="">- (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhus_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyewuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyewuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyiowh HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyiowh_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">- (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">- (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1),<br class="">- (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1),<br class="">- (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vd0 ),<br class="">- (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vd0_128B ),<br class="">- (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpybus HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpybus_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpybus HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpybus_128B HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vassign HvxVR:$src1),<br class="">- (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1),<br class="">- (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhb_dv_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1),<br class="">- (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1),<br class="">- (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1),<br class="">- (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1),<br class="">- (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class=""> (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpahb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class=""> (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsatwh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsatwh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class=""> (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyihb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class=""> (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class=""> (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyiwb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class=""> (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_valignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vnot HvxVR:$src1),<br class="">+ (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1),<br class="">+ (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2),<br class="">+ (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2),<br class="">+ (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">+ (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">+ (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_veqw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff ub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff ub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff ub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff ub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff uh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff uh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff uh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff uh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_veqw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">@@ -2753,584 +2626,664 @@ def: Pat<(int_hexagon_V6_vgth HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vgth_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vgtb HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vgtb_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vnot HvxVR:$src1),<br class="">- (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1),<br class="">- (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vgtb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtuw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1),<br class="">- (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1),<br class="">- (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundhub HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vroundhub_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1),<br class="">- (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1),<br class="">- (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_veqb HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_veqb_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_lvsplatw IntRegs:$src1),<br class="">- (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_lvsplatw_128B IntRegs:$src1),<br class="">- (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1),<br class="">- (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1),<br class="">- (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">- (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwh_oracc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">- (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">- (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3),<br class="">- (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1),<br class="">+ (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1),<br class="">+ (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_pred_xor HvxQR:$src1, HvxQR:$src2),<br class=""> (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_pred_xor_128B HvxQR:$src1, HvxQR:$src2),<br class=""> (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">- (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybusi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4),<br class="">- (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff w HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabs<br class="">diff w_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vabs<br class="">diff w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1),<br class="">+ (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1),<br class="">+ (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsathub HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsathub_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsatwh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsatwh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufeh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufeh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1),<br class="">+ (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1),<br class="">+ (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1),<br class="">+ (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1),<br class="">+ (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1),<br class="">+ (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1),<br class="">+ (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffb HvxVR:$src1),<br class="">+ (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vshuffb_128B HvxVR:$src1),<br class="">+ (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_lvsplatw IntRegs:$src1),<br class="">+ (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_lvsplatw_128B IntRegs:$src1),<br class="">+ (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1),<br class="">+ (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1),<br class="">+ (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vassign HvxVR:$src1),<br class="">+ (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1),<br class="">+ (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1),<br class="">+ (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1),<br class="">+ (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1),<br class="">+ (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1),<br class="">+ (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1),<br class="">+ (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1),<br class="">+ (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1),<br class="">+ (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1),<br class="">+ (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1),<br class="">+ (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1),<br class="">+ (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">+ (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">+ (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">+ (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwh_oracc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),<br class="">+ (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_hi HvxWR:$src1),<br class="">+ (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1),<br class="">+ (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_lo HvxWR:$src1),<br class="">+ (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1),<br class="">+ (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>;<br class=""><br class=""> // V62 HVX Instructions.<br class=""><br class="">-def: Pat<(int_hexagon_V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">- (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandnqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">- (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsatuwuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsatuwuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2),<br class="">- (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcnpnt0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">- (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">- (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vminb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vminb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vlsrb HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vlsrb_128B HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtp0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtp0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4),<br class="">- (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4),<br class="">- (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldpnt0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldpnt0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvnqv HvxQR:$src1, HvxVR:$src2),<br class="">- (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvnqv_128B HvxQR:$src1, HvxVR:$src2),<br class="">- (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1),<br class="">- (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1),<br class="">- (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1),<br class="">- (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1),<br class="">- (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtpnt0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldnpnt0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtnp0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtnp0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vrounduhub HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vrounduhub_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcp0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcp0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vadduwsat HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vadduwsat_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldtnpnt0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddbsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddbsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandnqrt HvxQR:$src1, IntRegs:$src2),<br class="">- (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandnqrt_128B HvxQR:$src1, IntRegs:$src2),<br class="">- (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmaxb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvqv HvxQR:$src1, HvxVR:$src2),<br class="">- (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vandvqv_128B HvxQR:$src1, HvxVR:$src2),<br class="">- (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">- (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">- (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">- (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubuwsat HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vsubuwsat_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddbsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddbsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2),<br class=""> (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vaddbsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class=""> (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldnp0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldnp0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">+ (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">+ (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">+ (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">+ (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">+ (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddubh_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">+ (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyiwub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandnqrt HvxQR:$src1, IntRegs:$src2),<br class="">+ (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandnqrt_128B HvxQR:$src1, IntRegs:$src2),<br class="">+ (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">+ (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandnqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),<br class="">+ (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvqv HvxQR:$src1, HvxVR:$src2),<br class="">+ (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvqv_128B HvxQR:$src1, HvxVR:$src2),<br class="">+ (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvnqv HvxQR:$src1, HvxVR:$src2),<br class="">+ (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vandvnqv_128B HvxQR:$src1, HvxVR:$src2),<br class="">+ (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_pred_scalar2v2 IntRegs:$src1),<br class=""> (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_pred_scalar2v2_128B IntRegs:$src1),<br class=""> (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldp0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldp0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddubh_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class="">- (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2),<br class="">+ (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmaxb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vminb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vminb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vsatuwuh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vsatuwuh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1),<br class="">+ (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1),<br class="">+ (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1),<br class="">+ (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1),<br class="">+ (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vaddclbw HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vaddclbw_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcpnt0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2),<br class="">- (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2),<br class="">- (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcnp0 PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_ldcnp0_128B PredRegs:$src1, IntRegs:$src2),<br class="">- (V6_ldcnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4),<br class="">+ (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4),<br class="">+ (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3),<br class="">+ (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4),<br class=""> (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vlutvwh_oracci_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4),<br class=""> (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>;<br class=""><br class=""> // V65 HVX Instructions.<br class=""><br class="">+def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">+ (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class=""> (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2),<br class="">- (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2),<br class="">- (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vdd0 ),<br class="">+ (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vdd0_128B ),<br class="">+ (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1),<br class="">+ (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1),<br class="">+ (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1),<br class="">+ (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1),<br class="">+ (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2),<br class="">+ (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class=""> (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),<br class=""> (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2),<br class="">- (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2),<br class="">- (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">- (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2),<br class="">- (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2),<br class="">- (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">+ (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">+ (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">+ (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">+ (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class=""> (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class=""> (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2),<br class="">+ (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2),<br class="">+ (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2),<br class=""> (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3),<br class="">- (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),<br class="">- (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),<br class="">- (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1),<br class="">- (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1),<br class="">- (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1),<br class="">- (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1),<br class="">- (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),<br class="">+ (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),<br class="">+ (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),<br class="">+ (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),<br class="">+ (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5),<br class="">+ (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5),<br class="">+ (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5),<br class="">+ (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),<br class="">+ (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1),<br class=""> (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1),<br class=""> (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1),<br class="">- (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1),<br class="">- (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vdd0 ),<br class="">- (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vdd0_128B ),<br class="">- (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2),<br class="">- (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1),<br class="">- (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1),<br class="">- (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1),<br class="">+ (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1),<br class="">+ (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1),<br class="">+ (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1),<br class="">+ (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>;<br class=""><br class=""> // V66 HVX Instructions.<br class=""><br class="">-def: Pat<(int_hexagon_V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">- (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vaddcarrysat_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">- (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2),<br class="">+ (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vasr_into_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),<br class=""> (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX128B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">+ (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX64B]>;<br class="">+def: Pat<(int_hexagon_V6_vaddcarrysat_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3),<br class="">+ (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX128B]>;<br class=""> def: Pat<(int_hexagon_V6_vsatdw HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>;<br class=""> def: Pat<(int_hexagon_V6_vsatdw_128B HvxVR:$src1, HvxVR:$src2),<br class=""> (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>;<br class="">-def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>;<br class="">-def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2),<br class="">- (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>;<br class=""><br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class=""><a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br class=""></div></div></blockquote></div><br class=""></div></div></div></blockquote></div><br class=""></div></body></html>