<div dir="ltr">Hi Anna,<div><br></div><div>The reserve_global_reg.ll test was failing on some buildbots which were only building X86 target (e.g. <a href="http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/29248">http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/29248</a>).</div><div><br></div><div>I pushed aea7578fade2563cb5ea60548914667b515c457a to fix this. Please can you confirm this change is correct?</div><div><br></div><div>Thanks</div><div>Russ</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, 18 Nov 2019 at 10:08, Anna Welker via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Anna Welker<br>
Date: 2019-11-18T10:07:37Z<br>
New Revision: 2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77.diff</a><br>
<br>
LOG: [ARM] Allocatable Global Register Variables for ARM<br>
<br>
Provides support for using r6-r11 as globally scoped<br>
register variables. This requires a -ffixed-rN flag<br>
in order to reserve rN against general allocation.<br>
<br>
If for a given GRV declaration the corresponding flag<br>
is not found, or the the register in question is the<br>
target's FP, we fail with a diagnostic.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D68862" rel="noreferrer" target="_blank">https://reviews.llvm.org/D68862</a><br>
<br>
Added: <br>
clang/test/Driver/arm-reserved-reg-options.c<br>
clang/test/Sema/arm-global-regs.c<br>
llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll<br>
llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll<br>
llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll<br>
llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll<br>
llvm/test/CodeGen/Thumb/callee_save_reserved.ll<br>
llvm/test/Feature/reserve_global_reg.ll<br>
<br>
Modified: <br>
clang/docs/ClangCommandLineReference.rst<br>
clang/include/clang/Basic/DiagnosticDriverKinds.td<br>
clang/include/clang/Basic/DiagnosticGroups.td<br>
clang/include/clang/Basic/DiagnosticSemaKinds.td<br>
clang/include/clang/Basic/TargetInfo.h<br>
clang/include/clang/Driver/Options.td<br>
clang/lib/Basic/Targets/ARM.cpp<br>
clang/lib/Basic/Targets/ARM.h<br>
clang/lib/Driver/ToolChains/Arch/ARM.cpp<br>
clang/lib/Sema/SemaDecl.cpp<br>
llvm/lib/Target/ARM/ARM.td<br>
llvm/lib/Target/ARM/ARMAsmPrinter.cpp<br>
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/lib/Target/ARM/ARMSubtarget.cpp<br>
llvm/lib/Target/ARM/ARMSubtarget.h<br>
llvm/lib/Target/ARM/ARMTargetTransformInfo.h<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst<br>
index e8d561fae956..492eec71f2e4 100644<br>
--- a/clang/docs/ClangCommandLineReference.rst<br>
+++ b/clang/docs/ClangCommandLineReference.rst<br>
@@ -2430,10 +2430,31 @@ Enable XNACK (AMDGPU only)<br>
<br>
ARM<br>
---<br>
+<br>
+.. option:: -ffixed-r6<br>
+<br>
+Reserve the r6 register (ARM only)<br>
+<br>
+.. option:: -ffixed-r7<br>
+<br>
+Reserve the r7 register (ARM only)<br>
+<br>
+.. option:: -ffixed-r8<br>
+<br>
+Reserve the r8 register (ARM only)<br>
+<br>
.. option:: -ffixed-r9<br>
<br>
Reserve the r9 register (ARM only)<br>
<br>
+.. option:: -ffixed-r10<br>
+<br>
+Reserve the r10 register (ARM only)<br>
+<br>
+.. option:: -ffixed-r11<br>
+<br>
+Reserve the r11 register (ARM only)<br>
+<br>
.. option:: -mexecute-only, -mno-execute-only, -mpure-code<br>
<br>
Disallow generation of data access to code sections (ARM only)<br>
<br>
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td<br>
index 5ff03e133563..0e309909030e 100644<br>
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td<br>
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td<br>
@@ -464,6 +464,10 @@ def warn_drv_msp430_hwmult_no_device : Warning<"no MCU device specified, but "<br>
"specify a MSP430 device, or -mhwmult to set hardware multiply type "<br>
"explicitly.">, InGroup<InvalidCommandLineArgument>;<br>
<br>
+// Frame pointer reservation.<br>
+def err_reserved_frame_pointer : Error<<br>
+ "'%0' has been specified but '%1' is used as the frame pointer for this target">;<br>
+<br>
def warn_drv_libstdcxx_not_found : Warning<<br>
"include path for libstdc++ headers not found; pass '-stdlib=libc++' on the "<br>
"command line to use the libc++ standard library instead">,<br>
<br>
diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td<br>
index bc66a8253074..6b83bf59ea89 100644<br>
--- a/clang/include/clang/Basic/DiagnosticGroups.td<br>
+++ b/clang/include/clang/Basic/DiagnosticGroups.td<br>
@@ -1115,3 +1115,6 @@ def CrossTU : DiagGroup<"ctu">;<br>
def CTADMaybeUnsupported : DiagGroup<"ctad-maybe-unsupported">;<br>
<br>
def FortifySource : DiagGroup<"fortify-source">;<br>
+<br>
+// Register reservation.<br>
+def FixedRegs : DiagGroup<"fixed-registers">;<br>
<br>
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td<br>
index beb25c5a0892..49ad7c7cc462 100644<br>
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td<br>
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td<br>
@@ -7716,6 +7716,8 @@ let CategoryName = "Inline Assembly Issue" in {<br>
def err_asm_unknown_register_name : Error<"unknown register name '%0' in asm">;<br>
def err_asm_invalid_global_var_reg : Error<"register '%0' unsuitable for "<br>
"global register variables on this target">;<br>
+ def err_asm_missing_fixed_reg_opt : Error<"-ffixed-%0 is required for "<br>
+ "global named register variable declaration">;<br>
def err_asm_register_size_mismatch : Error<"size of register '%0' does not "<br>
"match variable size">;<br>
def err_asm_bad_register_type : Error<"bad type for named register variable">;<br>
<br>
diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h<br>
index 33cecdadc686..cc83f4c34c14 100644<br>
--- a/clang/include/clang/Basic/TargetInfo.h<br>
+++ b/clang/include/clang/Basic/TargetInfo.h<br>
@@ -938,6 +938,12 @@ class TargetInfo : public virtual TransferrableTargetInfo,<br>
return true;<br>
}<br>
<br>
+ /// Check if the register is reserved globally<br>
+ ///<br>
+ /// This function returns true if the register passed in RegName is reserved<br>
+ /// using the corresponding -ffixed-RegName option.<br>
+ virtual bool isRegisterReservedGlobally(StringRef) const { return true; }<br>
+<br>
// validateOutputConstraint, validateInputConstraint - Checks that<br>
// a constraint is valid and provides information about it.<br>
// FIXME: These should return a real error instead of just true/false.<br>
<br>
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td<br>
index 6087b13228dc..3fca181b8784 100644<br>
--- a/clang/include/clang/Driver/Options.td<br>
+++ b/clang/include/clang/Driver/Options.td<br>
@@ -2266,8 +2266,9 @@ def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,<br>
def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,<br>
HelpText<"Allow generation of deprecated IT blocks for ARMv8. It is off by default for ARMv8 Thumb mode">;<br>
def marm : Flag<["-"], "marm">, Alias<mno_thumb>;<br>
-def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,<br>
- HelpText<"Reserve the r9 register (ARM only)">;<br>
+foreach i = {6-11} in<br>
+ def ffixed_r#i : Flag<["-"], "ffixed-r"#i>, Group<m_arm_Features_Group>,<br>
+ HelpText<"Reserve the r"#i#" register (ARM only)">;<br>
def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,<br>
HelpText<"Disallow use of movt/movw pairs (ARM only)">;<br>
def mcrc : Flag<["-"], "mcrc">, Group<m_Group>,<br>
<br>
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp<br>
index 437a77afdc99..92e5e26eba3c 100644<br>
--- a/clang/lib/Basic/Targets/ARM.cpp<br>
+++ b/clang/lib/Basic/Targets/ARM.cpp<br>
@@ -879,6 +879,38 @@ ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {<br>
return llvm::makeArrayRef(GCCRegAliases);<br>
}<br>
<br>
+bool ARMTargetInfo::validateGlobalRegisterVariable(<br>
+ StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const {<br>
+ bool isValid = llvm::StringSwitch<bool>(RegName)<br>
+ .Case("r6", true)<br>
+ .Case("r7", true)<br>
+ .Case("r8", true)<br>
+ .Case("r9", true)<br>
+ .Case("r10", true)<br>
+ .Case("r11", true)<br>
+ .Case("sp", true)<br>
+ .Default(false);<br>
+ HasSizeMismatch = false;<br>
+ return isValid;<br>
+}<br>
+<br>
+bool ARMTargetInfo::isRegisterReservedGlobally(StringRef RegName) const {<br>
+ // The "sp" register does not have a -ffixed-sp option,<br>
+ // so reserve it unconditionally.<br>
+ if (RegName.equals("sp"))<br>
+ return true;<br>
+<br>
+ // reserve rN (N:6-11) registers only if the corresponding<br>
+ // +reserve-rN feature is found<br>
+ const std::vector<std::string> &Features = getTargetOpts().Features;<br>
+ const std::string SearchFeature = "+reserve-" + RegName.str();<br>
+ for (const std::string &Feature : Features) {<br>
+ if (Feature.compare(SearchFeature) == 0)<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
bool ARMTargetInfo::validateAsmConstraint(<br>
const char *&Name, TargetInfo::ConstraintInfo &Info) const {<br>
switch (*Name) {<br>
<br>
diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h<br>
index ce87a6265934..90fb20f8f7a5 100644<br>
--- a/clang/lib/Basic/Targets/ARM.h<br>
+++ b/clang/lib/Basic/Targets/ARM.h<br>
@@ -161,6 +161,9 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {<br>
<br>
ArrayRef<const char *> getGCCRegNames() const override;<br>
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;<br>
+ bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,<br>
+ bool &HasSizeMismatch) const override;<br>
+ bool isRegisterReservedGlobally(StringRef RegName) const override;<br>
bool validateAsmConstraint(const char *&Name,<br>
TargetInfo::ConstraintInfo &Info) const override;<br>
std::string convertConstraint(const char *&Constraint) const override;<br>
<br>
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp<br>
index 68a57310ad40..cca47722c204 100644<br>
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp<br>
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp<br>
@@ -592,11 +592,39 @@ void arm::getARMTargetFeatures(const ToolChain &TC,<br>
Features.push_back("+strict-align");<br>
}<br>
<br>
- // llvm does not support reserving registers in general. There is support<br>
- // for reserving r9 on ARM though (defined as a platform-specific register<br>
- // in ARM EABI).<br>
- if (Args.hasArg(options::OPT_ffixed_r9))<br>
- Features.push_back("+reserve-r9");<br>
+ // Do not allow r9 reservation with -frwpi.<br>
+ if (Args.hasArg(options::OPT_ffixed_r9) && Args.hasArg(options::OPT_frwpi)) {<br>
+ Arg *A = Args.getLastArg(options::OPT_ffixed_r9);<br>
+ Arg *B = Args.getLastArg(options::OPT_frwpi);<br>
+ D.Diag(diag::err_opt_not_valid_with_opt)<br>
+ << A->getAsString(Args) << B->getAsString(Args);<br>
+ }<br>
+<br>
+ // The compiler can still use a FP in certain circumstances,<br>
+ // even when frame pointer elimination is enabled. Thus we should<br>
+ // not allow to reserve a target's FP register.<br>
+ const llvm::opt::OptSpecifier RestrictFPOpt =<br>
+ (Triple.isOSDarwin() || (!Triple.isOSWindows() && Triple.isThumb()))<br>
+ ? options::OPT_ffixed_r7<br>
+ : options::OPT_ffixed_r11;<br>
+ if (Args.hasArg(RestrictFPOpt)) {<br>
+ const std::string OptStr =<br>
+ Args.getLastArg(RestrictFPOpt)->getAsString(Args);<br>
+ const unsigned int SubStrIndex = strlen("ffixed-r");<br>
+ D.Diag(diag::err_reserved_frame_pointer)<br>
+ << OptStr << OptStr.substr(SubStrIndex);<br>
+ }<br>
+<br>
+// Reservation of general purpose registers.<br>
+#define HANDLE_FFIXED_R(n) \<br>
+ if (Args.hasArg(options::OPT_ffixed_r##n)) \<br>
+ Features.push_back("+reserve-r" #n)<br>
+ HANDLE_FFIXED_R(6);<br>
+ HANDLE_FFIXED_R(7);<br>
+ HANDLE_FFIXED_R(8);<br>
+ HANDLE_FFIXED_R(9);<br>
+ HANDLE_FFIXED_R(10);<br>
+ HANDLE_FFIXED_R(11);<br>
<br>
// The kext linker doesn't know how to deal with movw/movt.<br>
if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))<br>
<br>
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp<br>
index aba7049b0a51..b469217108ce 100644<br>
--- a/clang/lib/Sema/SemaDecl.cpp<br>
+++ b/clang/lib/Sema/SemaDecl.cpp<br>
@@ -7009,6 +7009,8 @@ NamedDecl *Sema::ActOnVariableDeclarator(<br>
Diag(E->getExprLoc(), diag::err_asm_invalid_global_var_reg) << Label;<br>
else if (HasSizeMismatch)<br>
Diag(E->getExprLoc(), diag::err_asm_register_size_mismatch) << Label;<br>
+ else if (!TI.isRegisterReservedGlobally(Label))<br>
+ Diag(E->getExprLoc(), diag::err_asm_missing_fixed_reg_opt) << Label;<br>
}<br>
<br>
if (!R->isIntegralType(Context) && !R->isPointerType()) {<br>
<br>
diff --git a/clang/test/Driver/arm-reserved-reg-options.c b/clang/test/Driver/arm-reserved-reg-options.c<br>
new file mode 100644<br>
index 000000000000..e97c717d7e7e<br>
--- /dev/null<br>
+++ b/clang/test/Driver/arm-reserved-reg-options.c<br>
@@ -0,0 +1,35 @@<br>
+// ## FP ARM + Thumb<br>
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R11 %s<br>
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r7 -mthumb -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s<br>
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r11 -mthumb -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// RUN: %clang -target thumbv6m-none-eabi -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s<br>
+// RUN: %clang -target thumbv6m-none-eabi -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// ## FP Darwin (R7)<br>
+// RUN: %clang -target armv6-apple-darwin9 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s<br>
+// RUN: %clang -target armv6-apple-darwin9 -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// RUN: %clang -target armv6-apple-ios3 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s<br>
+// RUN: %clang -target armv6-apple-ios3 -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// RUN: %clang -target armv7s-apple-darwin10 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s<br>
+// RUN: %clang -target armv7s-apple-darwin10 -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// ## FP Windows (R11)<br>
+// RUN: %clang -target armv7-windows -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R11 %s<br>
+// RUN: %clang -target armv7-windows -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s<br>
+<br>
+// ## FRWPI (R9)<br>
+// RUN: %clang -target arm-arm-none-eabi -### -frwpi -ffixed-r9 -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-CONFLICT %s<br>
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r9 -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-VALID %s<br>
+// RUN: %clang -target arm-arm-none-eabi -### -frwpi -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-VALID %s<br>
+<br>
+// CHECK-ERROR-R11: error: '-ffixed-r11' has been specified but 'r11' is used as the frame pointer for this target<br>
+// CHECK-ERROR-R7: error: '-ffixed-r7' has been specified but 'r7' is used as the frame pointer for this target<br>
+// CHECK-NO-ERROR-NOT: may still be used as a frame pointer<br>
+<br>
+// CHECK-RESERVED-FRWPI-CONFLICT: option '-ffixed-r9' cannot be specified with '-frwpi'<br>
+// CHECK-RESERVED-FRWPI-VALID-NOT: option '-ffixed-r9' cannot be specified with '-frwpi'<br>
<br>
diff --git a/clang/test/Sema/arm-global-regs.c b/clang/test/Sema/arm-global-regs.c<br>
new file mode 100644<br>
index 000000000000..753cb60e6838<br>
--- /dev/null<br>
+++ b/clang/test/Sema/arm-global-regs.c<br>
@@ -0,0 +1,20 @@<br>
+// RUN: %clang_cc1 -ffreestanding -fsyntax-only -target-feature +reserve-r9 -verify -triple arm-arm-none-eabi %s<br>
+<br>
+// Check a small subset of valid and invalid global register variable declarations.<br>
+// Also check that for global register variables without -ffixed-reg options it throws an error.<br>
+<br>
+register unsigned arm_r3 __asm("r3"); //expected-error {{register 'r3' unsuitable for global register variables on this target}}<br>
+<br>
+register unsigned arm_r12 __asm("r12"); //expected-error {{register 'r12' unsuitable for global register variables on this target}}<br>
+<br>
+register unsigned arm_r5 __asm("r5"); //expected-error {{register 'r5' unsuitable for global register variables on this target}}<br>
+<br>
+register unsigned arm_r9 __asm("r9");<br>
+<br>
+register unsigned arm_r6 __asm("r6"); //expected-error {{-ffixed-r6 is required for global named register variable declaration}}<br>
+<br>
+register unsigned arm_r7 __asm("r7"); //expected-error {{-ffixed-r7 is required for global named register variable declaration}}<br>
+<br>
+register unsigned *parm_r7 __asm("r7"); //expected-error {{-ffixed-r7 is required for global named register variable declaration}}<br>
+<br>
+register unsigned arm_sp __asm("sp");<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td<br>
index 66bfd4c82e25..285dad1cf29a 100644<br>
--- a/llvm/lib/Target/ARM/ARM.td<br>
+++ b/llvm/lib/Target/ARM/ARM.td<br>
@@ -391,9 +391,11 @@ def FeatureExecuteOnly : SubtargetFeature<"execute-only",<br>
"Enable the generation of "<br>
"execute only code.">;<br>
<br>
-def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",<br>
- "Reserve R9, making it unavailable"<br>
- " as GPR">;<br>
+foreach i = {6-11} in<br>
+ def FeatureReserveR#i : SubtargetFeature<"reserve-r"#i,<br>
+ "ReservedGPRegisters["#i#"]", "true",<br>
+ "Reserve R"#i#", making it "<br>
+ "unavailable as a GPR">;<br>
<br>
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",<br>
"Don't use movt/movw pairs for "<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp<br>
index ed0969fa625b..10153dd2e395 100644<br>
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp<br>
@@ -752,7 +752,7 @@ void ARMAsmPrinter::emitAttributes() {<br>
if (STI.isRWPI())<br>
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,<br>
ARMBuildAttrs::R9IsSB);<br>
- else if (STI.isR9Reserved())<br>
+ else if (STI.isGPRegisterReserved(9))<br>
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,<br>
ARMBuildAttrs::R9Reserved);<br>
else<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
index 4ace52b32e9f..afcdb648cbc8 100644<br>
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
@@ -198,9 +198,11 @@ getReservedRegs(const MachineFunction &MF) const {<br>
markSuperRegs(Reserved, getFramePointerReg(STI));<br>
if (hasBasePointer(MF))<br>
markSuperRegs(Reserved, BasePtr);<br>
- // Some targets reserve R9.<br>
- if (STI.isR9Reserved())<br>
- markSuperRegs(Reserved, ARM::R9);<br>
+ for (size_t R = 0; R < ARM::GPRRegClass.getNumRegs(); ++R) {<br>
+ if (STI.isGPRegisterReserved(R)) {<br>
+ markSuperRegs(Reserved, ARM::R0 + R);<br>
+ }<br>
+ }<br>
// Reserve D16-D31 if the subtarget doesn't support them.<br>
if (!STI.hasD32()) {<br>
static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");<br>
@@ -280,7 +282,7 @@ ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,<br>
case ARM::GPRRegClassID: {<br>
bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()<br>
? TFI->hasFP(MF) : true;<br>
- return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);<br>
+ return 10 - HasFP - STI.getNumGPRegistersReserved();<br>
}<br>
case ARM::SPRRegClassID: // Currently not used as 'rep' register class.<br>
case ARM::DPRRegClassID:<br>
@@ -380,6 +382,11 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {<br>
const MachineFrameInfo &MFI = MF.getFrameInfo();<br>
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();<br>
const ARMFrameLowering *TFI = getFrameLowering(MF);<br>
+ const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();<br>
+<br>
+ // Disable base pointer R6 if -ffixed-r6 is used.<br>
+ if (STI.isGPRegisterReserved(BasePtr - ARM::R0))<br>
+ return false;<br>
<br>
// If we have stack realignment and VLAs, we have no pointer to use to<br>
// access the stack. If we have stack realignment, and a large call frame,<br>
@@ -416,6 +423,7 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {<br>
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {<br>
const MachineRegisterInfo *MRI = &MF.getRegInfo();<br>
const ARMFrameLowering *TFI = getFrameLowering(MF);<br>
+ const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();<br>
// We can't realign the stack if:<br>
// 1. Dynamic stack realignment is explicitly disabled,<br>
// 2. There are VLAs in the function and the base pointer is disabled.<br>
@@ -425,6 +433,9 @@ bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {<br>
// register allocation with frame pointer elimination, it is too late now.<br>
if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))<br>
return false;<br>
+ // Disable base pointer R6 if -ffixed-r6 is used.<br>
+ if (STI.isGPRegisterReserved(BasePtr - ARM::R0))<br>
+ return false;<br>
// We may also need a base pointer if there are dynamic allocas or stack<br>
// pointer adjustments around calls.<br>
if (TFI->hasReservedCallFrame(MF))<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
index 5428bd6c94b3..106894e28f03 100644<br>
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp<br>
@@ -1704,6 +1704,19 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,<br>
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);<br>
for (unsigned i = 0; CSRegs[i]; ++i) {<br>
unsigned Reg = CSRegs[i];<br>
+ if (STI.isRWPI() && Reg == ARM::R9) {<br>
+ // Paranoid check for use of R9 with RWPI. Clobbering R9 with -frwpi will<br>
+ // emit warnings about undefined behaviour but maybe theres's a valid use<br>
+ // case so on that basis allow it to be pushed/popped in the<br>
+ // prologue/epilogue.<br>
+ } else if (Reg > ARM::R0 && ARM::GPRRegClass.contains(Reg) &&<br>
+ STI.isGPRegisterReserved(Reg - ARM::R0)) {<br>
+ LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << " has been reserved and"<br>
+ << " should not be allocatable"<br>
+ << " or spillable.\n");<br>
+ SavedRegs.reset(Reg);<br>
+ continue;<br>
+ }<br>
bool Spilled = false;<br>
if (SavedRegs.test(Reg)) {<br>
Spilled = true;<br>
@@ -1948,7 +1961,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,<br>
LLVM_DEBUG(dbgs() << printReg(Reg, TRI)<br>
<< " is saved low register, RegDeficit = "<br>
<< RegDeficit << "\n");<br>
- } else {<br>
+ } else if (!STI.isGPRegisterReserved(Reg - ARM::R0)) {<br>
AvailableRegs.push_back(Reg);<br>
LLVM_DEBUG(<br>
dbgs()<br>
@@ -1963,7 +1976,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,<br>
--RegDeficit;<br>
LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "<br>
<< RegDeficit << "\n");<br>
- } else {<br>
+ } else if (!STI.isGPRegisterReserved(7)) {<br>
AvailableRegs.push_back(ARM::R7);<br>
LLVM_DEBUG(<br>
dbgs()<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
index c395a4feea70..b1d1d4fd5fc9 100644<br>
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
@@ -5572,9 +5572,15 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {<br>
Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,<br>
const MachineFunction &MF) const {<br>
Register Reg = StringSwitch<unsigned>(RegName)<br>
- .Case("sp", ARM::SP)<br>
- .Default(0);<br>
- if (Reg)<br>
+ .Case("r6", ARM::R6)<br>
+ .Case("r7", ARM::R7)<br>
+ .Case("r8", ARM::R8)<br>
+ .Case("r9", ARM::R9)<br>
+ .Case("r10", ARM::R10)<br>
+ .Case("r11", ARM::R11)<br>
+ .Case("sp", ARM::SP)<br>
+ .Default(ARM::NoRegister);<br>
+ if (Reg != ARM::NoRegister)<br>
return Reg;<br>
report_fatal_error(Twine("Invalid register name \""<br>
+ StringRef(RegName) + "\"."));<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp<br>
index eb4d39b01cbb..7a57376a6895 100644<br>
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp<br>
@@ -98,8 +98,9 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,<br>
const ARMBaseTargetMachine &TM, bool IsLittle,<br>
bool MinSize)<br>
: ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),<br>
- CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),<br>
- TargetTriple(TT), Options(TM.Options), TM(TM),<br>
+ ReservedGPRegisters(ARM::GPRRegClass.getNumRegs()), CPUString(CPU),<br>
+ OptMinSize(MinSize), IsLittle(IsLittle), TargetTriple(TT),<br>
+ Options(TM.Options), TM(TM),<br>
FrameLowering(initializeFrameLowering(CPU, FS)),<br>
// At this point initializeSubtargetDependencies has been called so<br>
// we can query directly.<br>
@@ -253,8 +254,18 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {<br>
(Options.UnsafeFPMath || isTargetDarwin()))<br>
UseNEONForSinglePrecisionFP = true;<br>
<br>
- if (isRWPI())<br>
- ReserveR9 = true;<br>
+ if (isRWPI() || (isTargetMachO() && !HasV6Ops))<br>
+ ReservedGPRegisters.set(9);<br>
+<br>
+ // Throw an error when trying to reserve a target's FP register. It may<br>
+ // be used by the compiler even when frame pointer elimination is enabled.<br>
+ // FIXME: Throw this error if -frame-pointer=none is not set; otherwise<br>
+ // only emit a warning.<br>
+ const int restFP = (useR7AsFramePointer()) ? 7 : 11;<br>
+ if (isGPRegisterReserved(restFP))<br>
+ report_fatal_error(<br>
+ "Register r" + std::to_string(restFP) +<br>
+ " has been specified but is used as the frame pointer for this target.");<br>
<br>
// If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2<br>
if (MVEVectorCostFactor == 0)<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h<br>
index f582a92f6563..c5836a3eca7b 100644<br>
--- a/llvm/lib/Target/ARM/ARMSubtarget.h<br>
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h<br>
@@ -229,8 +229,8 @@ class ARMSubtarget : public ARMGenSubtargetInfo {<br>
/// NoARM - True if subtarget does not support ARM mode execution.<br>
bool NoARM = false;<br>
<br>
- /// ReserveR9 - True if R9 is not available as a general purpose register.<br>
- bool ReserveR9 = false;<br>
+ // ReservedGPRegisters[i] - R#i is not available as a general purpose register<br>
+ BitVector ReservedGPRegisters;<br>
<br>
/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of<br>
/// 32-bit imms (including global addresses).<br>
@@ -763,8 +763,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {<br>
bool isAClass() const { return ARMProcClass == AClass; }<br>
bool isReadTPHard() const { return ReadTPHard; }<br>
<br>
- bool isR9Reserved() const {<br>
- return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;<br>
+ bool isGPRegisterReserved(size_t i) const { return ReservedGPRegisters[i]; }<br>
+ unsigned getNumGPRegistersReserved() const {<br>
+ return ReservedGPRegisters.count();<br>
}<br>
<br>
bool useR7AsFramePointer() const {<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h<br>
index 5bb3bcaf10e7..c1fd01d2df9d 100644<br>
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h<br>
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h<br>
@@ -76,7 +76,9 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {<br>
ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,<br>
ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,<br>
ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,<br>
- ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,<br>
+ ARM::FeatureExecuteOnly, ARM::FeatureReserveR6, ARM::FeatureReserveR7,<br>
+ ARM::FeatureReserveR8, ARM::FeatureReserveR9, ARM::FeatureReserveR10,<br>
+ ARM::FeatureReserveR11, ARM::FeatureNoMovt,<br>
ARM::FeatureNoNegativeImmediates<br>
};<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll b/llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll<br>
new file mode 100644<br>
index 000000000000..0b6fd7443af2<br>
--- /dev/null<br>
+++ b/llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll<br>
@@ -0,0 +1,44 @@<br>
+; Using VLAs(Variable Length Arrays) in a function will use R6 to keep track<br>
+; of the stack frame, and also spill/restore R6 to the stack.<br>
+; This tests that using -ffixed-r6 (-mattr=+reserve-r6) will stop R6<br>
+; being used and also stop it being spilled/restored to the stack.<br>
+; RUN: llc < %s -mcpu=cortex-m0 -mtriple=thumbv7-arm-none-eabi | FileCheck %s --check-prefix=CHECK-STATIC --check-prefix=CHECK-R6<br>
+; RUN: llc < %s -mcpu=cortex-m0 -mtriple=thumbv7-arm-none-eabi -mattr=+reserve-r6 | FileCheck %s --check-prefix=CHECK-STATIC --check-prefix=CHECK-NO-R6<br>
+<br>
+define void @f() #0 {<br>
+entry:<br>
+ %i = alloca i32, align 4<br>
+ store i32 0, i32* %i, align 4<br>
+<br>
+ %saved_stack = alloca i8*, align 4<br>
+ %0 = call i8* @llvm.stacksave()<br>
+ store i8* %0, i8** %saved_stack, align 4<br>
+<br>
+ %__vla_expr0 = alloca i32, align 4<br>
+ %1 = load i32, i32* %i, align 4<br>
+ %vla = alloca double, i32 %1, align 8<br>
+ store i32 %1, i32* %__vla_expr0, align 4<br>
+<br>
+ %2 = load i8*, i8** %saved_stack, align 4<br>
+ call void @llvm.stackrestore(i8* %2)<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare i8* @llvm.stacksave() #1<br>
+declare void @llvm.stackrestore(i8* %ptr) #1<br>
+<br>
+attributes #0 = { noinline nounwind "stackrealign" }<br>
+attributes #1 = { nounwind }<br>
+<br>
+; CHECK-STATIC: push {r4,<br>
+; CHECK-R6: r6<br>
+; CHECK-NO-R6-NOT: r6<br>
+; CHECK-STATIC: lr}<br>
+; CHECK-R6: r6<br>
+; CHECK-NO-R6-NOT: r6<br>
+; CHECK-STATIC: pop {r4,<br>
+; CHECK-R6: r6<br>
+; CHECK-NO-R6-NOT: r6<br>
+; CHECK-STATIC: pc}<br>
+<br>
<br>
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll<br>
new file mode 100644<br>
index 000000000000..e2a4af87dde7<br>
--- /dev/null<br>
+++ b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll<br>
@@ -0,0 +1,63 @@<br>
+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s<br>
+;<br>
+; Equivalent C source code<br>
+; register unsigned r6 asm("r6");<br>
+; void bar(unsigned int i,<br>
+; unsigned int j,<br>
+; unsigned int k,<br>
+; unsigned int l,<br>
+; unsigned int m,<br>
+; unsigned int n,<br>
+; unsigned int o,<br>
+; unsigned int p)<br>
+; {<br>
+; r6 = 10;<br>
+; unsigned int result = i + j + k + l + m + n + o + p;<br>
+; }<br>
+declare void @llvm.write_register.i32(metadata, i32) nounwind<br>
+<br>
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {<br>
+entry:<br>
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}<br>
+; CHECK: {{.*}}mov{{.*}}r6,{{.*}}<br>
+; CHECK-NOT: {{.*}}r6{{.*}}<br>
+ %i.addr = alloca i32, align 4<br>
+ %j.addr = alloca i32, align 4<br>
+ %k.addr = alloca i32, align 4<br>
+ %l.addr = alloca i32, align 4<br>
+ %m.addr = alloca i32, align 4<br>
+ %n.addr = alloca i32, align 4<br>
+ %o.addr = alloca i32, align 4<br>
+ %p.addr = alloca i32, align 4<br>
+ %result = alloca i32, align 4<br>
+ store i32 %i, i32* %i.addr, align 4<br>
+ store i32 %j, i32* %j.addr, align 4<br>
+ store i32 %k, i32* %k.addr, align 4<br>
+ store i32 %l, i32* %l.addr, align 4<br>
+ store i32 %m, i32* %m.addr, align 4<br>
+ store i32 %n, i32* %n.addr, align 4<br>
+ store i32 %o, i32* %o.addr, align 4<br>
+ store i32 %p, i32* %p.addr, align 4<br>
+ call void @llvm.write_register.i32(metadata !0, i32 10)<br>
+ %0 = load i32, i32* %i.addr, align 4<br>
+ %1 = load i32, i32* %j.addr, align 4<br>
+ %add = add i32 %0, %1<br>
+ %2 = load i32, i32* %k.addr, align 4<br>
+ %add1 = add i32 %add, %2<br>
+ %3 = load i32, i32* %l.addr, align 4<br>
+ %add2 = add i32 %add1, %3<br>
+ %4 = load i32, i32* %m.addr, align 4<br>
+ %add3 = add i32 %add2, %4<br>
+ %5 = load i32, i32* %n.addr, align 4<br>
+ %add4 = add i32 %add3, %5<br>
+ %6 = load i32, i32* %o.addr, align 4<br>
+ %add5 = add i32 %add4, %6<br>
+ %7 = load i32, i32* %p.addr, align 4<br>
+ %add6 = add i32 %add5, %7<br>
+ store i32 %add6, i32* %result, align 4<br>
+ ret void<br>
+}<br>
+<br>
+!llvm.named.register.r6 = !{!0}<br>
+!0 = !{!"r6"}<br>
+<br>
<br>
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll<br>
new file mode 100644<br>
index 000000000000..3647c0701a7c<br>
--- /dev/null<br>
+++ b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll<br>
@@ -0,0 +1,57 @@<br>
+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s<br>
+;<br>
+; Equivalent C source code<br>
+; void bar(unsigned int i,<br>
+; unsigned int j,<br>
+; unsigned int k,<br>
+; unsigned int l,<br>
+; unsigned int m,<br>
+; unsigned int n,<br>
+; unsigned int o,<br>
+; unsigned int p)<br>
+; {<br>
+; unsigned int result = i + j + k + l + m + n + o + p;<br>
+; }<br>
+<br>
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {<br>
+entry:<br>
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}<br>
+ %i.addr = alloca i32, align 4<br>
+ %j.addr = alloca i32, align 4<br>
+ %k.addr = alloca i32, align 4<br>
+ %l.addr = alloca i32, align 4<br>
+ %m.addr = alloca i32, align 4<br>
+ %n.addr = alloca i32, align 4<br>
+ %o.addr = alloca i32, align 4<br>
+ %p.addr = alloca i32, align 4<br>
+ %result = alloca i32, align 4<br>
+ store i32 %i, i32* %i.addr, align 4<br>
+ store i32 %j, i32* %j.addr, align 4<br>
+ store i32 %k, i32* %k.addr, align 4<br>
+ store i32 %l, i32* %l.addr, align 4<br>
+ store i32 %m, i32* %m.addr, align 4<br>
+ store i32 %n, i32* %n.addr, align 4<br>
+ store i32 %o, i32* %o.addr, align 4<br>
+ store i32 %p, i32* %p.addr, align 4<br>
+ %0 = load i32, i32* %i.addr, align 4<br>
+ %1 = load i32, i32* %j.addr, align 4<br>
+ %add = add i32 %0, %1<br>
+ %2 = load i32, i32* %k.addr, align 4<br>
+ %add1 = add i32 %add, %2<br>
+ %3 = load i32, i32* %l.addr, align 4<br>
+ %add2 = add i32 %add1, %3<br>
+ %4 = load i32, i32* %m.addr, align 4<br>
+ %add3 = add i32 %add2, %4<br>
+ %5 = load i32, i32* %n.addr, align 4<br>
+ %add4 = add i32 %add3, %5<br>
+ %6 = load i32, i32* %o.addr, align 4<br>
+ %add5 = add i32 %add4, %6<br>
+ %7 = load i32, i32* %p.addr, align 4<br>
+ %add6 = add i32 %add5, %7<br>
+ store i32 %add6, i32* %result, align 4<br>
+; CHECK: {{.*}}r5{{.*}}<br>
+; CHECK-NOT: {{.*}}r6{{.*}}<br>
+ ret void<br>
+; CHECK-NOT: pop {{{.*}}r6,{{.*}}}<br>
+}<br>
+<br>
<br>
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll b/llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll<br>
new file mode 100644<br>
index 000000000000..d1f020936a3d<br>
--- /dev/null<br>
+++ b/llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll<br>
@@ -0,0 +1,58 @@<br>
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s<br>
+;<br>
+; Equivalent C source code<br>
+; void bar(unsigned int i,<br>
+; unsigned int j,<br>
+; unsigned int k,<br>
+; unsigned int l,<br>
+; unsigned int m,<br>
+; unsigned int n,<br>
+; unsigned int o,<br>
+; unsigned int p)<br>
+; {<br>
+; unsigned int result = i + j + k + l + m + n + o + p;<br>
+; }<br>
+<br>
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {<br>
+entry:<br>
+; CHECK: push {{{.*}}r4, r5{{.*}}}<br>
+ %i.addr = alloca i32, align 4<br>
+ %j.addr = alloca i32, align 4<br>
+ %k.addr = alloca i32, align 4<br>
+ %l.addr = alloca i32, align 4<br>
+ %m.addr = alloca i32, align 4<br>
+ %n.addr = alloca i32, align 4<br>
+ %o.addr = alloca i32, align 4<br>
+ %p.addr = alloca i32, align 4<br>
+ %result = alloca i32, align 4<br>
+ store i32 %i, i32* %i.addr, align 4<br>
+ store i32 %j, i32* %j.addr, align 4<br>
+ store i32 %k, i32* %k.addr, align 4<br>
+ store i32 %l, i32* %l.addr, align 4<br>
+ store i32 %m, i32* %m.addr, align 4<br>
+ store i32 %n, i32* %n.addr, align 4<br>
+ store i32 %o, i32* %o.addr, align 4<br>
+ store i32 %p, i32* %p.addr, align 4<br>
+ %0 = load i32, i32* %i.addr, align 4<br>
+ %1 = load i32, i32* %j.addr, align 4<br>
+ %add = add i32 %0, %1<br>
+ %2 = load i32, i32* %k.addr, align 4<br>
+ %add1 = add i32 %add, %2<br>
+ %3 = load i32, i32* %l.addr, align 4<br>
+ %add2 = add i32 %add1, %3<br>
+ %4 = load i32, i32* %m.addr, align 4<br>
+ %add3 = add i32 %add2, %4<br>
+ %5 = load i32, i32* %n.addr, align 4<br>
+ %add4 = add i32 %add3, %5<br>
+ %6 = load i32, i32* %o.addr, align 4<br>
+ %add5 = add i32 %add4, %6<br>
+ %7 = load i32, i32* %p.addr, align 4<br>
+ %add6 = add i32 %add5, %7<br>
+ store i32 %add6, i32* %result, align 4<br>
+; CHECK: {{.*}}r4{{.*}}<br>
+; CHECK: {{.*}}r5{{.*}}<br>
+<br>
+; CHECK: pop {{{.*}}r4, r5{{.*}}}<br>
+ ret void<br>
+}<br>
+<br>
<br>
diff --git a/llvm/test/CodeGen/Thumb/callee_save_reserved.ll b/llvm/test/CodeGen/Thumb/callee_save_reserved.ll<br>
new file mode 100644<br>
index 000000000000..0329d7886a2a<br>
--- /dev/null<br>
+++ b/llvm/test/CodeGen/Thumb/callee_save_reserved.ll<br>
@@ -0,0 +1,15 @@<br>
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi -verify-machineinstrs -frame-pointer=none -mattr=+reserve-r6,+reserve-r8 \<br>
+; RUN: -asm-verbose=false | FileCheck --check-prefix=CHECK-INVALID %s<br>
+<br>
+; Reserved low registers should not be used to correct reg deficit.<br>
+define <4 x i32> @four_high_four_return_reserved() {<br>
+entry:<br>
+ ; CHECK-INVALID-NOT: r{{6|8}}<br>
+ tail call void asm sideeffect "", "~{r8},~{r9}"()<br>
+ %vecinit = insertelement <4 x i32> undef, i32 1, i32 0<br>
+ %vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1<br>
+ %vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2<br>
+ %vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3<br>
+ ret <4 x i32> %vecinit13<br>
+}<br>
+<br>
<br>
diff --git a/llvm/test/Feature/reserve_global_reg.ll b/llvm/test/Feature/reserve_global_reg.ll<br>
new file mode 100644<br>
index 000000000000..06081cae1fb2<br>
--- /dev/null<br>
+++ b/llvm/test/Feature/reserve_global_reg.ll<br>
@@ -0,0 +1,29 @@<br>
+; RUN: not llc < %s -mtriple=thumbv7-apple-darwin -mattr=+reserve-r7 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP7 %s<br>
+; RUN: not llc < %s -mtriple=armv7-windows-msvc -mattr=+reserve-r11 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP11 %s<br>
+; RUN: not llc < %s -mtriple=thumbv7-windows -mattr=+reserve-r11 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP11-2 %s<br>
+<br>
+; int test(int a, int b, int c) {<br>
+; return a + b + c;<br>
+; }<br>
+<br>
+; Function Attrs: noinline nounwind optnone<br>
+define hidden i32 @_Z4testiii(i32 %a, i32 %b, i32 %c) #0 {<br>
+entry:<br>
+ %a.addr = alloca i32, align 4<br>
+ %b.addr = alloca i32, align 4<br>
+ %c.addr = alloca i32, align 4<br>
+ store i32 %a, i32* %a.addr, align 4<br>
+ store i32 %b, i32* %b.addr, align 4<br>
+ store i32 %c, i32* %c.addr, align 4<br>
+ %0 = load i32, i32* %a.addr, align 4<br>
+ %1 = load i32, i32* %b.addr, align 4<br>
+ %add = add nsw i32 %0, %1<br>
+ %2 = load i32, i32* %c.addr, align 4<br>
+ %add1 = add nsw i32 %add, %2<br>
+ ret i32 %add1<br>
+}<br>
+<br>
+; CHECK-RESERVE-FP7: Register r7 has been specified but is used as the frame pointer for this target.<br>
+; CHECK-RESERVE-FP11: Register r11 has been specified but is used as the frame pointer for this target.<br>
+; CHECK-RESERVE-FP11-2: Register r11 has been specified but is used as the frame pointer for this target.<br>
+<br>
<br>
<br>
<br>
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