<div dir="ltr">This change was reverted as it appeared to cause build failures like <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/15642/steps/build%20stage1%20clang/logs/stdio">this</a>:<div><pre style="font-family:"Courier New",courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-stdout">FAILED: lib/Target/WebAssembly/CMakeFiles/LLVMWebAssemblyCodeGen.dir/WebAssemblyISelLowering.cpp.o
/usr/bin/c++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/Target/WebAssembly -I/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/WebAssembly -I/usr/include/libxml2 -Iinclude -I/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/include -fPIC -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wno-maybe-uninitialized -Wdelete-non-virtual-dtor -Wno-comment -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -UNDEBUG -fno-exceptions -fno-rtti -std=c++14 -MD -MT lib/Target/WebAssembly/CMakeFiles/LLVMWebAssemblyCodeGen.dir/WebAssemblyISelLowering.cpp.o -MF lib/Target/WebAssembly/CMakeFiles/LLVMWebAssemblyCodeGen.dir/WebAssemblyISelLowering.cpp.o.d -o lib/Target/WebAssembly/CMakeFiles/LLVMWebAssemblyCodeGen.dir/WebAssemblyISelLowering.cpp.o -c /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp: In member function ‘llvm::SDValue llvm::WebAssemblyTargetLowering::LowerBUILD_VECTOR(llvm::SDValue, llvm::SelectionDAG&) const’:
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1439:63: error: call of overloaded ‘getVTList(<brace-enclosed initializer list>)’ is ambiguous
WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList({VecT}),
^
In file included from /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/include/llvm/CodeGen/TargetLowering.h:35:0,
from /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h:18,
from /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:14:
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/include/llvm/CodeGen/SelectionDAG.h:563:12: note: candidate: llvm::SDVTList llvm::SelectionDAG::getVTList(llvm::EVT)
SDVTList getVTList(EVT VT);
^~~~~~~~~
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/include/llvm/CodeGen/SelectionDAG.h:567:12: note: candidate: llvm::SDVTList llvm::SelectionDAG::getVTList(llvm::ArrayRef<llvm::EVT>)
SDVTList getVTList(ArrayRef<EVT> VTs);
^~~~~~~~~
</span></pre><br class="gmail-Apple-interchange-newline"></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Oct 31, 2019 at 2:22 PM Thomas Lively via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Thomas Lively<br>
Date: 2019-10-31T14:22:30-07:00<br>
New Revision: 11850a6305c5778b180243eb06aefe86762dd4ce<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/11850a6305c5778b180243eb06aefe86762dd4ce" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/11850a6305c5778b180243eb06aefe86762dd4ce</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/11850a6305c5778b180243eb06aefe86762dd4ce.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/11850a6305c5778b180243eb06aefe86762dd4ce.diff</a><br>
<br>
LOG: [WebAssembly] Expand setcc of v2i64<br>
<br>
Summary:<br>
The SIMD spec does not include i64x2 comparisons, so they need to be<br>
expanded. Using setOperationAction to expand them also causes f64x2<br>
comparisons to be expanded, so setCondCodeAction needs to be used<br>
instead. But since there are no legal condition codes, the legalizer<br>
does not know how to expand the comparisons. We therefore manually<br>
unroll the operation, taking care to fill each lane with -1 or 0<br>
rather than 1 or 0 for consistency with the other vector comparisons.<br>
<br>
Reviewers: aheejin<br>
<br>
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D69604" rel="noreferrer" target="_blank">https://reviews.llvm.org/D69604</a><br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp<br>
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h<br>
llvm/test/CodeGen/WebAssembly/simd-comparisons.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp<br>
index f06afdbcea9e..2f698711a746 100644<br>
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp<br>
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp<br>
@@ -189,6 +189,11 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(<br>
setOperationAction(Op, MVT::v2f64, Expand);<br>
}<br>
<br>
+ // Expand operations not supported for i64x2 vectors<br>
+ if (Subtarget->hasUnimplementedSIMD128())<br>
+ for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)<br>
+ setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);<br>
+<br>
// Expand additional SIMD ops that V8 hasn't implemented yet<br>
if (!Subtarget->hasUnimplementedSIMD128()) {<br>
setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);<br>
@@ -1011,6 +1016,8 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,<br>
return LowerBUILD_VECTOR(Op, DAG);<br>
case ISD::VECTOR_SHUFFLE:<br>
return LowerVECTOR_SHUFFLE(Op, DAG);<br>
+ case ISD::SETCC:<br>
+ return LowerSETCC(Op, DAG);<br>
case ISD::SHL:<br>
case ISD::SRA:<br>
case ISD::SRL:<br>
@@ -1472,6 +1479,29 @@ WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,<br>
return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, Op.getValueType(), Ops);<br>
}<br>
<br>
+SDValue WebAssemblyTargetLowering::LowerSETCC(SDValue Op,<br>
+ SelectionDAG &DAG) const {<br>
+ SDLoc DL(Op);<br>
+ // The legalizer does not know how to expand the comparison modes of i64x2<br>
+ // vectors because no comparison modes are supported. We could solve this by<br>
+ // expanding all i64x2 SETCC nodes, but that seems to expand f64x2 SETCC nodes<br>
+ // (which return i64x2 results) as well. So instead we manually unroll i64x2<br>
+ // comparisons here.<br>
+ assert(Subtarget->hasUnimplementedSIMD128());<br>
+ assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);<br>
+ SmallVector<SDValue, 2> LHS, RHS;<br>
+ DAG.ExtractVectorElements(Op->getOperand(0), LHS);<br>
+ DAG.ExtractVectorElements(Op->getOperand(1), RHS);<br>
+ const SDValue &CC = Op->getOperand(2);<br>
+ auto MakeLane = [&](unsigned I) {<br>
+ return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I],<br>
+ DAG.getConstant(uint64_t(-1), DL, MVT::i64),<br>
+ DAG.getConstant(uint64_t(0), DL, MVT::i64), CC);<br>
+ };<br>
+ return DAG.getBuildVector(Op->getValueType(0), DL,<br>
+ {MakeLane(0), MakeLane(1)});<br>
+}<br>
+<br>
SDValue<br>
WebAssemblyTargetLowering::LowerAccessVectorElement(SDValue Op,<br>
SelectionDAG &DAG) const {<br>
<br>
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h<br>
index a53e24a05542..90936670c471 100644<br>
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h<br>
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h<br>
@@ -108,6 +108,7 @@ class WebAssemblyTargetLowering final : public TargetLowering {<br>
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;<br>
};<br>
<br>
diff --git a/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll b/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll<br>
index 2decd38fa84a..3b6af73eb15f 100644<br>
--- a/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll<br>
+++ b/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll<br>
@@ -637,6 +637,156 @@ define <4 x i32> @compare_sext_uge_v4i32 (<4 x i32> %x, <4 x i32> %y) {<br>
ret <4 x i32> %res<br>
}<br>
<br>
+; CHECK-LABEL: compare_eq_v2i64:<br>
+; SIMD128-NEXT: .functype compare_eq_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp eq <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_eq_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_eq_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp eq <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_ne_v2i64:<br>
+; SIMD128-NEXT: .functype compare_ne_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp ne <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_ne_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_ne_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp ne <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_slt_v2i64:<br>
+; SIMD128-NEXT: .functype compare_slt_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp slt <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_slt_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_slt_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp slt <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_ult_v2i64:<br>
+; SIMD128-NEXT: .functype compare_ult_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp ult <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_ult_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_ult_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp ult <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sle_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sle_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp sle <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_sle_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_sle_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp sle <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_ule_v2i64:<br>
+; SIMD128-NEXT: .functype compare_ule_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp ule <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_ule_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_ule_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp ule <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sgt_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sgt_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp sgt <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_sgt_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_sgt_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp sgt <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_ugt_v2i64:<br>
+; SIMD128-NEXT: .functype compare_ugt_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp ugt <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_ugt_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_ugt_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp ugt <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sge_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sge_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp sge <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_sge_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_sge_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp sge <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_uge_v2i64:<br>
+; SIMD128-NEXT: .functype compare_uge_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i1> @compare_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %res = icmp uge <2 x i64> %x, %y<br>
+ ret <2 x i1> %res<br>
+}<br>
+<br>
+; CHECK-LABEL: compare_sext_uge_v2i64:<br>
+; SIMD128-NEXT: .functype compare_sext_uge_v2i64 (v128, v128) -> (v128){{$}}<br>
+define <2 x i64> @compare_sext_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {<br>
+ %cmp = icmp uge <2 x i64> %x, %y<br>
+ %res = sext <2 x i1> %cmp to <2 x i64><br>
+ ret <2 x i64> %res<br>
+}<br>
+<br>
; CHECK-LABEL: compare_oeq_v4f32:<br>
; NO-SIMD128-NOT: f32x4<br>
; SIMD128-NEXT: .functype compare_oeq_v4f32 (v128, v128) -> (v128){{$}}<br>
<br>
<br>
<br>
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</blockquote></div>