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<p>Definitely unnecessary, but this is coming from a
scalar_to_vector unfortunately.</p>
<p>I'm going to investigate doing an explicit zextload from v4i8 to
a v4i32 and then perform as a v16i8 reduction.</p>
<p>Simon.<br>
</p>
<div class="moz-cite-prefix">On 11/10/2019 19:51, Craig Topper
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:CAF7ks-NDUh05tWY50S2ZtK2KvjHnCHcFUpj0ZnuNHmzu_XoWRg@mail.gmail.com">
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<div>Why do the load cases use a movzxdq after the movd? That
seems unnecessary. The movd should have generated 0s already.</div>
<br clear="all">
<div>
<div dir="ltr" class="gmail_signature"
data-smartmail="gmail_signature">~Craig</div>
</div>
<br>
</div>
<br>
<div class="gmail_quote">
<div dir="ltr" class="gmail_attr">On Fri, Oct 11, 2019 at 10:51
AM Simon Pilgrim via llvm-commits <<a
href="mailto:llvm-commits@lists.llvm.org"
moz-do-not-send="true">llvm-commits@lists.llvm.org</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0px 0px 0px
0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author:
rksimon<br>
Date: Fri Oct 11 10:54:15 2019<br>
New Revision: 374579<br>
<br>
URL: <a
href="http://llvm.org/viewvc/llvm-project?rev=374579&view=rev"
rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project?rev=374579&view=rev</a><br>
Log:<br>
[X86][SSE] Add support for v4i8 add reduction<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=374579&r1=374578&r2=374579&view=diff"
rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=374579&r1=374578&r2=374579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 11
10:54:15 2019<br>
@@ -36239,10 +36239,15 @@ static SDValue
combineReductionToHorizon<br>
<br>
SDLoc DL(ExtElt);<br>
<br>
- if (VecVT == MVT::v8i8) {<br>
+ // vXi8 reduction - sub 128-bit vector.<br>
+ if (VecVT == MVT::v4i8 || VecVT == MVT::v8i8) {<br>
+ // Pad with zero.<br>
+ if (VecVT == MVT::v4i8)<br>
+ Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8,
Rdx,<br>
+ DAG.getConstant(0, DL, VecVT));<br>
// Pad with undef.<br>
Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8,
Rdx,<br>
- DAG.getUNDEF(VecVT));<br>
+ DAG.getUNDEF(MVT::v8i8));<br>
Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx,<br>
DAG.getConstant(0, DL, MVT::v16i8));<br>
Rdx = DAG.getBitcast(MVT::v16i8, Rdx);<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll<br>
URL: <a
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll?rev=374579&r1=374578&r2=374579&view=diff"
rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll?rev=374579&r1=374578&r2=374579&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll Fri Oct
11 10:54:15 2019<br>
@@ -1029,44 +1029,36 @@ define i8 @test_v2i8_load(<2 x
i8>* %p)<br>
define i8 @test_v4i8(<4 x i8> %a0) {<br>
; SSE2-LABEL: test_v4i8:<br>
; SSE2: # %bb.0:<br>
-; SSE2-NEXT: movdqa %xmm0, %xmm1<br>
-; SSE2-NEXT: psrld $16, %xmm1<br>
-; SSE2-NEXT: paddb %xmm0, %xmm1<br>
-; SSE2-NEXT: movdqa %xmm1, %xmm0<br>
-; SSE2-NEXT: psrlw $8, %xmm0<br>
-; SSE2-NEXT: paddb %xmm1, %xmm0<br>
+; SSE2-NEXT: pxor %xmm1, %xmm1<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 =
xmm0[0],xmm1[0],xmm0[1],xmm1[1]<br>
+; SSE2-NEXT: psadbw %xmm1, %xmm0<br>
; SSE2-NEXT: movd %xmm0, %eax<br>
; SSE2-NEXT: # kill: def $al killed $al killed $eax<br>
; SSE2-NEXT: retq<br>
;<br>
; SSE41-LABEL: test_v4i8:<br>
; SSE41: # %bb.0:<br>
-; SSE41-NEXT: movdqa %xmm0, %xmm1<br>
-; SSE41-NEXT: psrld $16, %xmm1<br>
-; SSE41-NEXT: paddb %xmm0, %xmm1<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
-; SSE41-NEXT: psrlw $8, %xmm0<br>
-; SSE41-NEXT: paddb %xmm1, %xmm0<br>
-; SSE41-NEXT: pextrb $0, %xmm0, %eax<br>
+; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 =
xmm0[0],zero,xmm0[1],zero<br>
+; SSE41-NEXT: pxor %xmm1, %xmm1<br>
+; SSE41-NEXT: psadbw %xmm0, %xmm1<br>
+; SSE41-NEXT: pextrb $0, %xmm1, %eax<br>
; SSE41-NEXT: # kill: def $al killed $al killed $eax<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: test_v4i8:<br>
; AVX: # %bb.0:<br>
-; AVX-NEXT: vpsrld $16, %xmm0, %xmm1<br>
-; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
-; AVX-NEXT: vpsrlw $8, %xmm0, %xmm1<br>
-; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
+; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 =
xmm0[0],zero,xmm0[1],zero<br>
+; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1<br>
+; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0<br>
; AVX-NEXT: vpextrb $0, %xmm0, %eax<br>
; AVX-NEXT: # kill: def $al killed $al killed $eax<br>
; AVX-NEXT: retq<br>
;<br>
; AVX512-LABEL: test_v4i8:<br>
; AVX512: # %bb.0:<br>
-; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1<br>
-; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
-; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1<br>
-; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
+; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm0 =
xmm0[0],zero,xmm0[1],zero<br>
+; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1<br>
+; AVX512-NEXT: vpsadbw %xmm1, %xmm0, %xmm0<br>
; AVX512-NEXT: vpextrb $0, %xmm0, %eax<br>
; AVX512-NEXT: # kill: def $al killed $al killed $eax<br>
; AVX512-NEXT: retq<br>
@@ -1078,36 +1070,28 @@ define i8 @test_v4i8_load(<4 x
i8>* %p)<br>
; SSE2-LABEL: test_v4i8_load:<br>
; SSE2: # %bb.0:<br>
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; SSE2-NEXT: movdqa %xmm0, %xmm1<br>
-; SSE2-NEXT: psrld $16, %xmm1<br>
-; SSE2-NEXT: paddb %xmm0, %xmm1<br>
-; SSE2-NEXT: movdqa %xmm1, %xmm0<br>
-; SSE2-NEXT: psrlw $8, %xmm0<br>
-; SSE2-NEXT: paddb %xmm1, %xmm0<br>
-; SSE2-NEXT: movd %xmm0, %eax<br>
+; SSE2-NEXT: pxor %xmm1, %xmm1<br>
+; SSE2-NEXT: psadbw %xmm0, %xmm1<br>
+; SSE2-NEXT: movd %xmm1, %eax<br>
; SSE2-NEXT: # kill: def $al killed $al killed $eax<br>
; SSE2-NEXT: retq<br>
;<br>
; SSE41-LABEL: test_v4i8_load:<br>
; SSE41: # %bb.0:<br>
; SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; SSE41-NEXT: movdqa %xmm0, %xmm1<br>
-; SSE41-NEXT: psrld $16, %xmm1<br>
-; SSE41-NEXT: paddb %xmm0, %xmm1<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
-; SSE41-NEXT: psrlw $8, %xmm0<br>
-; SSE41-NEXT: paddb %xmm1, %xmm0<br>
-; SSE41-NEXT: pextrb $0, %xmm0, %eax<br>
+; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 =
xmm0[0],zero,xmm0[1],zero<br>
+; SSE41-NEXT: pxor %xmm1, %xmm1<br>
+; SSE41-NEXT: psadbw %xmm0, %xmm1<br>
+; SSE41-NEXT: pextrb $0, %xmm1, %eax<br>
; SSE41-NEXT: # kill: def $al killed $al killed $eax<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: test_v4i8_load:<br>
; AVX: # %bb.0:<br>
; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; AVX-NEXT: vpsrld $16, %xmm0, %xmm1<br>
-; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
-; AVX-NEXT: vpsrlw $8, %xmm0, %xmm1<br>
-; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
+; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 =
xmm0[0],zero,xmm0[1],zero<br>
+; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1<br>
+; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0<br>
; AVX-NEXT: vpextrb $0, %xmm0, %eax<br>
; AVX-NEXT: # kill: def $al killed $al killed $eax<br>
; AVX-NEXT: retq<br>
@@ -1115,10 +1099,9 @@ define i8 @test_v4i8_load(<4 x
i8>* %p)<br>
; AVX512-LABEL: test_v4i8_load:<br>
; AVX512: # %bb.0:<br>
; AVX512-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1<br>
-; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
-; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1<br>
-; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0<br>
+; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm0 =
xmm0[0],zero,xmm0[1],zero<br>
+; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1<br>
+; AVX512-NEXT: vpsadbw %xmm1, %xmm0, %xmm0<br>
; AVX512-NEXT: vpextrb $0, %xmm0, %eax<br>
; AVX512-NEXT: # kill: def $al killed $al killed $eax<br>
; AVX512-NEXT: retq<br>
<br>
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