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Of course, sorry I missed that one!</div>
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<p style="margin-top: 0px; margin-bottom: 0px;font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">Sam Parker</span></p>
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<p style="margin-top: 0px; margin-bottom: 0px;font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">Compilation Tools Engineer | Arm</span></p>
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<p style="margin-top: 0px; margin-bottom: 0px;font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">. . . . . . . . . . . . . . . . . . . . . . . . . . .</span></p>
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<p style="margin-top: 0px; margin-bottom: 0px;font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">Arm.com</span></p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Galina Kistanova <gkistanova@gmail.com><br>
<b>Sent:</b> 18 September 2019 19:23<br>
<b>To:</b> Sam Parker <Sam.Parker@arm.com><br>
<b>Cc:</b> llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm] r372111 - [ARM][LowOverheadLoops] Add LR def safety check</font>
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<div dir="ltr">Hello Sam,<br>
<br>
It looks like this commit added broken test to the builder llvm-clang-x86_64-expensive-checks-win.<br>
<a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19705">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19705</a>:<br>
. . .<br>
Failing Tests (..):<br>
. . .<br>
LLVM :: CodeGen/Thumb2/LowOverheadLoops/massive.mir<br>
<br>
The builder was already red and did not send notifications on this.<br>
For now it's the only broken test on the builder.<br>
Please have a look?<br>
<br>
Thanks<br>
<br>
Galina</div>
<br>
<div class="x_gmail_quote">
<div dir="ltr" class="x_gmail_attr">On Tue, Sep 17, 2019 at 5:17 AM Sam Parker via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
</div>
<blockquote class="x_gmail_quote" style="margin:0px 0px 0px 0.8ex; border-left:1px solid rgb(204,204,204); padding-left:1ex">
Author: sam_parker<br>
Date: Tue Sep 17 05:19:32 2019<br>
New Revision: 372111<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=372111&view=rev" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=372111&view=rev</a><br>
Log:<br>
[ARM][LowOverheadLoops] Add LR def safety check<br>
<br>
Converting the *LoopStart pseudo instructions into DLS/WLS results in<br>
LR being defined. These instructions were inserted on the assumption<br>
that LR would already contain the loop counter because a mov is<br>
introduced during ISel as the the consumers in the loop can only use<br>
LR. That assumption proved wrong!<br>
<br>
So perform a safety check, finding an appropriate place to insert the<br>
DLS/WLS instructions or revert if this isn't possible.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D67539" rel="noreferrer" target="_blank">
https://reviews.llvm.org/D67539</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir<br>
Removed:<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir<br>
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp Tue Sep 17 05:19:32 2019<br>
@@ -34,6 +34,7 @@ using namespace llvm;<br>
namespace {<br>
<br>
class ARMLowOverheadLoops : public MachineFunctionPass {<br>
+ MachineFunction *MF = nullptr;<br>
const ARMBaseInstrInfo *TII = nullptr;<br>
MachineRegisterInfo *MRI = nullptr;<br>
std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;<br>
@@ -51,9 +52,21 @@ namespace {<br>
<br>
bool runOnMachineFunction(MachineFunction &MF) override;<br>
<br>
+ MachineFunctionProperties getRequiredProperties() const override {<br>
+ return MachineFunctionProperties().set(<br>
+ MachineFunctionProperties::Property::NoVRegs);<br>
+ }<br>
+<br>
+ StringRef getPassName() const override {<br>
+ return ARM_LOW_OVERHEAD_LOOPS_NAME;<br>
+ }<br>
+<br>
+ private:<br>
bool ProcessLoop(MachineLoop *ML);<br>
<br>
- bool RevertNonLoops(MachineFunction &MF);<br>
+ MachineInstr * IsSafeToDefineLR(MachineInstr *MI);<br>
+<br>
+ bool RevertNonLoops();<br>
<br>
void RevertWhile(MachineInstr *MI) const;<br>
<br>
@@ -62,16 +75,9 @@ namespace {<br>
void RevertLoopEnd(MachineInstr *MI) const;<br>
<br>
void Expand(MachineLoop *ML, MachineInstr *Start,<br>
- MachineInstr *Dec, MachineInstr *End, bool Revert);<br>
-<br>
- MachineFunctionProperties getRequiredProperties() const override {<br>
- return MachineFunctionProperties().set(<br>
- MachineFunctionProperties::Property::NoVRegs);<br>
- }<br>
+ MachineInstr *InsertPt, MachineInstr *Dec,<br>
+ MachineInstr *End, bool Revert);<br>
<br>
- StringRef getPassName() const override {<br>
- return ARM_LOW_OVERHEAD_LOOPS_NAME;<br>
- }<br>
};<br>
}<br>
<br>
@@ -80,26 +86,28 @@ char ARMLowOverheadLoops::ID = 0;<br>
INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,<br>
false, false)<br>
<br>
-bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &MF) {<br>
- if (!static_cast<const ARMSubtarget&>(MF.getSubtarget()).hasLOB())<br>
+bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {<br>
+ const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(mf.getSubtarget());<br>
+ if (!ST.hasLOB())<br>
return false;<br>
<br>
- LLVM_DEBUG(dbgs() << "ARM Loops on " << MF.getName() << " ------------- \n");<br>
+ MF = &mf;<br>
+ LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n");<br>
<br>
auto &MLI = getAnalysis<MachineLoopInfo>();<br>
- MRI = &MF.getRegInfo();<br>
- TII = static_cast<const ARMBaseInstrInfo*>(<br>
- MF.getSubtarget().getInstrInfo());<br>
- BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(MF));<br>
+ MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);<br>
+ MRI = &MF->getRegInfo();<br>
+ TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());<br>
+ BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(*MF));<br>
BBUtils->computeAllBlockSizes();<br>
- BBUtils->adjustBBOffsetsAfter(&MF.front());<br>
+ BBUtils->adjustBBOffsetsAfter(&MF->front());<br>
<br>
bool Changed = false;<br>
for (auto ML : MLI) {<br>
if (!ML->getParentLoop())<br>
Changed |= ProcessLoop(ML);<br>
}<br>
- Changed |= RevertNonLoops(MF);<br>
+ Changed |= RevertNonLoops();<br>
return Changed;<br>
}<br>
<br>
@@ -108,6 +116,100 @@ static bool IsLoopStart(MachineInstr &MI<br>
MI.getOpcode() == ARM::t2WhileLoopStart;<br>
}<br>
<br>
+template<typename T><br>
+static MachineInstr* SearchForDef(MachineInstr *Begin, T End, unsigned Reg) {<br>
+ for(auto &MI : make_range(T(Begin), End)) {<br>
+ for (auto &MO : MI.operands()) {<br>
+ if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)<br>
+ continue;<br>
+ return &MI;<br>
+ }<br>
+ }<br>
+ return nullptr;<br>
+}<br>
+<br>
+static MachineInstr* SearchForUse(MachineInstr *Begin,<br>
+ MachineBasicBlock::iterator End,<br>
+ unsigned Reg) {<br>
+ for(auto &MI : make_range(MachineBasicBlock::iterator(Begin), End)) {<br>
+ for (auto &MO : MI.operands()) {<br>
+ if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)<br>
+ continue;<br>
+ return &MI;<br>
+ }<br>
+ }<br>
+ return nullptr;<br>
+}<br>
+<br>
+// Is it safe to define LR with DLS/WLS?<br>
+// LR can defined if it is the operand to start, because it's the same value,<br>
+// or if it's going to be equivalent to the operand to Start.<br>
+MachineInstr *ARMLowOverheadLoops::IsSafeToDefineLR(MachineInstr *Start) {<br>
+<br>
+ auto IsMoveLR = [](MachineInstr *MI, unsigned Reg) {<br>
+ return MI->getOpcode() == ARM::tMOVr &&<br>
+ MI->getOperand(0).getReg() == ARM::LR &&<br>
+ MI->getOperand(1).getReg() == Reg &&<br>
+ MI->getOperand(2).getImm() == ARMCC::AL;<br>
+ };<br>
+<br>
+ MachineBasicBlock *MBB = Start->getParent();<br>
+ unsigned CountReg = Start->getOperand(0).getReg();<br>
+ // Walk forward and backward in the block to find the closest instructions<br>
+ // that define LR. Then also filter them out if they're not a mov lr.<br>
+ MachineInstr *PredLRDef = SearchForDef(Start, MBB->rend(), ARM::LR);<br>
+ if (PredLRDef && !IsMoveLR(PredLRDef, CountReg))<br>
+ PredLRDef = nullptr;<br>
+<br>
+ MachineInstr *SuccLRDef = SearchForDef(Start, MBB->end(), ARM::LR);<br>
+ if (SuccLRDef && !IsMoveLR(SuccLRDef, CountReg))<br>
+ SuccLRDef = nullptr;<br>
+<br>
+ // We've either found one, two or none mov lr instructions... Now figure out<br>
+ // if they are performing the equilvant mov that the Start instruction will.<br>
+ // Do this by scanning forward and backward to see if there's a def of the<br>
+ // register holding the count value. If we find a suitable def, return it as<br>
+ // the insert point. Later, if InsertPt != Start, then we can remove the<br>
+ // redundant instruction.<br>
+ if (SuccLRDef) {<br>
+ MachineBasicBlock::iterator End(SuccLRDef);<br>
+ if (!SearchForDef(Start, End, CountReg)) {<br>
+ return SuccLRDef;<br>
+ } else<br>
+ SuccLRDef = nullptr;<br>
+ }<br>
+ if (PredLRDef) {<br>
+ MachineBasicBlock::reverse_iterator End(PredLRDef);<br>
+ if (!SearchForDef(Start, End, CountReg)) {<br>
+ return PredLRDef;<br>
+ } else<br>
+ PredLRDef = nullptr;<br>
+ }<br>
+<br>
+ // We can define LR because LR already contains the same value.<br>
+ if (Start->getOperand(0).getReg() == ARM::LR)<br>
+ return Start;<br>
+<br>
+ // We've found no suitable LR def and Start doesn't use LR directly. Can we<br>
+ // just define LR anyway? <br>
+ const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();<br>
+ LivePhysRegs LiveRegs(*TRI);<br>
+ LiveRegs.addLiveOuts(*MBB);<br>
+<br>
+ // Not if we've haven't found a suitable mov and LR is live out.<br>
+ if (LiveRegs.contains(ARM::LR))<br>
+ return nullptr;<br>
+<br>
+ // If LR is not live out, we can insert the instruction if nothing else<br>
+ // uses LR after it.<br>
+ if (!SearchForUse(Start, MBB->end(), ARM::LR))<br>
+ return Start;<br>
+<br>
+ LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find suitable insertion point for"<br>
+ << " LR\n");<br>
+ return nullptr;<br>
+}<br>
+<br>
bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {<br>
<br>
bool Changed = false;<br>
@@ -169,11 +271,13 @@ bool ARMLowOverheadLoops::ProcessLoop(Ma<br>
End = &MI;<br>
else if (IsLoopStart(MI))<br>
Start = &MI;<br>
- else if (MI.getDesc().isCall())<br>
+ else if (MI.getDesc().isCall()) {<br>
// TODO: Though the call will require LE to execute again, does this<br>
// mean we should revert? Always executing LE hopefully should be<br>
// faster than performing a sub,cmp,br or even subs,br.<br>
Revert = true;<br>
+ LLVM_DEBUG(dbgs() << "ARM Loops: Found call.\n");<br>
+ }<br>
<br>
if (!Dec || End)<br>
continue;<br>
@@ -237,7 +341,14 @@ bool ARMLowOverheadLoops::ProcessLoop(Ma<br>
Revert = true;<br>
}<br>
<br>
- Expand(ML, Start, Dec, End, Revert);<br>
+ MachineInstr *InsertPt = Revert ? nullptr : IsSafeToDefineLR(Start);<br>
+ if (!InsertPt) {<br>
+ LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n");<br>
+ Revert = true;<br>
+ } else<br>
+ LLVM_DEBUG(dbgs() << "ARM Loops: Start insertion point: " << *InsertPt);<br>
+<br>
+ Expand(ML, Start, InsertPt, Dec, End, Revert);<br>
return true;<br>
}<br>
<br>
@@ -304,33 +415,13 @@ void ARMLowOverheadLoops::RevertLoopEnd(<br>
}<br>
<br>
void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,<br>
+ MachineInstr *InsertPt,<br>
MachineInstr *Dec, MachineInstr *End,<br>
bool Revert) {<br>
<br>
- auto ExpandLoopStart = [this](MachineLoop *ML, MachineInstr *Start) {<br>
- // The trip count should already been held in LR since the instructions<br>
- // within the loop can only read and write to LR. So, there should be a<br>
- // mov to setup the count. WLS/DLS perform this move, so find the original<br>
- // and delete it - inserting WLS/DLS in its place.<br>
- MachineBasicBlock *MBB = Start->getParent();<br>
- MachineInstr *InsertPt = Start;<br>
- for (auto &I : MRI->def_instructions(ARM::LR)) {<br>
- if (I.getParent() != MBB)<br>
- continue;<br>
-<br>
- // Always execute.<br>
- if (!I.getOperand(2).isImm() || I.getOperand(2).getImm() != ARMCC::AL)<br>
- continue;<br>
-<br>
- // Only handle move reg, if the trip count it will need moving into a reg<br>
- // before the setup instruction anyway.<br>
- if (!I.getDesc().isMoveReg() ||<br>
- !I.getOperand(1).isIdenticalTo(Start->getOperand(0)))<br>
- continue;<br>
- InsertPt = &I;<br>
- break;<br>
- }<br>
-<br>
+ auto ExpandLoopStart = [this](MachineLoop *ML, MachineInstr *Start,<br>
+ MachineInstr *InsertPt) {<br>
+ MachineBasicBlock *MBB = InsertPt->getParent();<br>
unsigned Opc = Start->getOpcode() == ARM::t2DoLoopStart ?<br>
ARM::t2DLS : ARM::t2WLS;<br>
MachineInstrBuilder MIB =<br>
@@ -389,18 +480,18 @@ void ARMLowOverheadLoops::Expand(Machine<br>
RevertLoopDec(Dec);<br>
RevertLoopEnd(End);<br>
} else {<br>
- Start = ExpandLoopStart(ML, Start);<br>
+ Start = ExpandLoopStart(ML, Start, InsertPt);<br>
RemoveDeadBranch(Start);<br>
End = ExpandLoopEnd(ML, Dec, End);<br>
RemoveDeadBranch(End);<br>
}<br>
}<br>
<br>
-bool ARMLowOverheadLoops::RevertNonLoops(MachineFunction &MF) {<br>
+bool ARMLowOverheadLoops::RevertNonLoops() {<br>
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting any remaining pseudos...\n");<br>
bool Changed = false;<br>
<br>
- for (auto &MBB : MF) {<br>
+ for (auto &MBB : *MF) {<br>
SmallVector<MachineInstr*, 4> Starts;<br>
SmallVector<MachineInstr*, 4> Decs;<br>
SmallVector<MachineInstr*, 4> Ends;<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir Tue Sep 17 05:19:32 2019<br>
@@ -4,6 +4,9 @@<br>
# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1<br>
<br>
--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {<br>
entry:<br>
%scevgep = getelementptr i32, i32* %q, i32 -1<br>
@@ -15,10 +18,10 @@<br>
%lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]<br>
%lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]<br>
%0 = phi i32 [ %n, %entry ], [ %2, %while.body ]<br>
- %scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1<br>
- %scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
- %1 = load i32, i32* %scevgep7, align 4<br>
- store i32 %1, i32* %scevgep4, align 4<br>
+ %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %1 = load i32, i32* %scevgep6, align 4<br>
+ store i32 %1, i32* %scevgep2, align 4<br>
%scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1<br>
%scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
%2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
@@ -44,7 +47,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -84,6 +87,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.1(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
@@ -96,9 +100,10 @@ body: |<br>
<br>
bb.1.while.body:<br>
successors: %bb.1(0x7c000000), %bb.2(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
<br>
- renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)<br>
- early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)<br>
+ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)<br>
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)<br>
renamable $lr = t2LoopDec killed renamable $lr, 1<br>
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr<br>
tB %bb.2, 14, $noreg<br>
@@ -108,4 +113,3 @@ body: |<br>
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
<br>
...<br>
-<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir Tue Sep 17 05:19:32 2019<br>
@@ -9,7 +9,10 @@<br>
# CHECK: bb.2.for.cond.cleanup:<br>
# CHECK: bb.3.for.header:<br>
<br>
---- | <br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {<br>
entry:<br>
call void @llvm.set.loop.iterations.i32(i32 %N)<br>
@@ -45,9 +48,11 @@<br>
}<br>
<br>
; Function Attrs: nounwind<br>
- declare i32 @llvm.arm.space(i32 immarg, i32) #0 <br>
+ declare i32 @llvm.arm.space(i32 immarg, i32) #0<br>
+ <br>
; Function Attrs: noduplicate nounwind<br>
- declare void @llvm.set.loop.iterations.i32(i32) #1 <br>
+ declare void @llvm.set.loop.iterations.i32(i32) #1<br>
+ <br>
; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1<br>
<br>
@@ -63,7 +68,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -128,6 +133,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.3(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r3, $r7, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
@@ -184,5 +190,3 @@ body: |<br>
tB %bb.1, 14, $noreg<br>
<br>
...<br>
-<br>
-<br>
<br>
Added: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir?rev=372111&view=auto" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir?rev=372111&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir (added)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir Tue Sep 17 05:19:32 2019<br>
@@ -0,0 +1,115 @@<br>
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s<br>
+# CHECK: $lr = t2DLS $r0<br>
+# CHECK-NOT: $lr = tMOVr $r0<br>
+# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1<br>
+<br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
+ define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {<br>
+ entry:<br>
+ %scevgep = getelementptr i32, i32* %q, i32 -1<br>
+ %scevgep3 = getelementptr i32, i32* %p, i32 -1<br>
+ call void @llvm.set.loop.iterations.i32(i32 %n)<br>
+ br label %while.body<br>
+ <br>
+ while.body: ; preds = %while.body, %entry<br>
+ %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]<br>
+ %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]<br>
+ %0 = phi i32 [ %n, %entry ], [ %2, %while.body ]<br>
+ %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %1 = load i32, i32* %scevgep6, align 4<br>
+ store i32 %1, i32* %scevgep2, align 4<br>
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
+ %3 = icmp ne i32 %2, 0<br>
+ br i1 %3, label %while.body, label %while.end<br>
+ <br>
+ while.end: ; preds = %while.body<br>
+ ret i32 0<br>
+ }<br>
+ <br>
+ declare void @llvm.set.loop.iterations.i32(i32) #0<br>
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0<br>
+ <br>
+ attributes #0 = { noduplicate nounwind }<br>
+ attributes #1 = { nounwind }<br>
+<br>
+...<br>
+---<br>
+name: do_copy<br>
+alignment: 2<br>
+exposesReturnsTwice: false<br>
+legalized: false<br>
+regBankSelected: false<br>
+selected: false<br>
+failedISel: false<br>
+tracksRegLiveness: true<br>
+hasWinCFI: false<br>
+registers: []<br>
+liveins:<br>
+ - { reg: '$r0', virtual-reg: '' }<br>
+ - { reg: '$r1', virtual-reg: '' }<br>
+ - { reg: '$r2', virtual-reg: '' }<br>
+frameInfo:<br>
+ isFrameAddressTaken: false<br>
+ isReturnAddressTaken: false<br>
+ hasStackMap: false<br>
+ hasPatchPoint: false<br>
+ stackSize: 8<br>
+ offsetAdjustment: 0<br>
+ maxAlignment: 4<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
+ stackProtector: ''<br>
+ maxCallFrameSize: 0<br>
+ cvBytesOfCalleeSavedRegisters: 0<br>
+ hasOpaqueSPAdjustment: false<br>
+ hasVAStart: false<br>
+ hasMustTailInVarArgFunc: false<br>
+ localFrameSize: 0<br>
+ savePoint: ''<br>
+ restorePoint: ''<br>
+fixedStack: []<br>
+stack:<br>
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+callSites: []<br>
+constants: []<br>
+machineFunctionInfo: {}<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
+ <br>
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
+ frame-setup CFI_INSTRUCTION offset $lr, -4<br>
+ frame-setup CFI_INSTRUCTION offset $r7, -8<br>
+ t2DoLoopStart $r0<br>
+ $lr = tMOVr killed $r0, 14, $noreg<br>
+ renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg<br>
+ renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg<br>
+ <br>
+ bb.1.while.body:<br>
+ successors: %bb.1(0x7c000000), %bb.2(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
+ <br>
+ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)<br>
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)<br>
+ renamable $lr = t2LoopDec killed renamable $lr, 1<br>
+ t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr<br>
+ tB %bb.2, 14, $noreg<br>
+ <br>
+ bb.2.while.end:<br>
+ $r0, dead $cpsr = tMOVi8 0, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
+<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir Tue Sep 17 05:19:32 2019<br>
@@ -5,8 +5,6 @@<br>
# CHECK-NOT: t2LEUpdate<br>
<br>
--- |<br>
- ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.ll'<br>
- source_filename = "/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.ll"<br>
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
target triple = "thumbv8.1m.main"<br>
<br>
@@ -35,15 +33,9 @@<br>
<br>
declare i32 @bar(...) local_unnamed_addr #0<br>
<br>
- ; Function Attrs: noduplicate nounwind<br>
declare void @llvm.set.loop.iterations.i32(i32) #1<br>
- <br>
- ; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1<br>
<br>
- ; Function Attrs: nounwind<br>
- declare void @llvm.stackprotector(i8*, i8**) #2<br>
- <br>
attributes #0 = { "target-features"="+mve.fp" }<br>
attributes #1 = { noduplicate nounwind }<br>
attributes #2 = { nounwind }<br>
@@ -57,7 +49,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -101,6 +93,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.4(0x30000000), %bb.1(0x50000000)<br>
+ liveins: $r0, $r4, $r5, $r7, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 16<br>
@@ -112,6 +105,7 @@ body: |<br>
<br>
bb.1.while.body.preheader:<br>
successors: %bb.2(0x80000000)<br>
+ liveins: $r0<br>
<br>
$lr = tMOVr $r0, 14, $noreg<br>
renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
@@ -119,6 +113,7 @@ body: |<br>
<br>
bb.2.while.body:<br>
successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r4<br>
<br>
$r5 = tMOVr killed $lr, 14, $noreg<br>
tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0<br>
@@ -129,6 +124,8 @@ body: |<br>
tB %bb.3, 14, $noreg<br>
<br>
bb.3.while.end:<br>
+ liveins: $r4<br>
+ <br>
$r0 = tMOVr killed $r4, 14, $noreg<br>
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
<br>
@@ -138,4 +135,3 @@ body: |<br>
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
<br>
...<br>
-<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir Tue Sep 17 05:19:32 2019<br>
@@ -4,7 +4,10 @@<br>
# CHECK-NOT: t2DLS<br>
# CHECK-NOT: t2LEUpdate<br>
<br>
---- | <br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
define i32 @mov_between_dec_end(i32 %n) #0 {<br>
entry:<br>
%cmp6 = icmp eq i32 %n, 0<br>
@@ -15,7 +18,6 @@<br>
br label %while.body<br>
<br>
while.body: ; preds = %while.body, %while.body.preheader<br>
- %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]<br>
%0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]<br>
%1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
%add = add i32 %1, 0<br>
@@ -27,10 +29,7 @@<br>
ret i32 %res.0.lcssa<br>
}<br>
<br>
- ; Function Attrs: noduplicate nounwind<br>
declare void @llvm.set.loop.iterations.i32(i32) #1<br>
- <br>
- ; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1<br>
<br>
attributes #0 = { "target-features"="+mve.fp" }<br>
@@ -46,7 +45,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -56,11 +55,11 @@ frameInfo:<br>
isReturnAddressTaken: false<br>
hasStackMap: false<br>
hasPatchPoint: false<br>
- stackSize: 16<br>
+ stackSize: 8<br>
offsetAdjustment: 0<br>
maxAlignment: 4<br>
- adjustsStack: true<br>
- hasCalls: true<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
stackProtector: ''<br>
maxCallFrameSize: 0<br>
cvBytesOfCalleeSavedRegisters: 0<br>
@@ -78,51 +77,46 @@ stack:<br>
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
callSites: []<br>
constants: []<br>
machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.4(0x30000000), %bb.1(0x50000000)<br>
+ liveins: $r0, $r7, $lr<br>
<br>
- frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
- frame-setup CFI_INSTRUCTION def_cfa_offset 16<br>
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
frame-setup CFI_INSTRUCTION offset $lr, -4<br>
frame-setup CFI_INSTRUCTION offset $r7, -8<br>
- frame-setup CFI_INSTRUCTION offset $r5, -12<br>
- frame-setup CFI_INSTRUCTION offset $r4, -16<br>
tCBZ $r0, %bb.4<br>
<br>
bb.1.while.body.preheader:<br>
successors: %bb.2(0x80000000)<br>
+ liveins: $r0<br>
<br>
$lr = tMOVr $r0, 14, $noreg<br>
- renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
t2DoLoopStart killed $r0<br>
<br>
bb.2.while.body:<br>
successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r4<br>
<br>
- renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg<br>
+ renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r4, 14, $noreg<br>
renamable $lr = t2LoopDec killed renamable $lr, 1<br>
renamable $r4 = tMOVr $lr, 14, $noreg<br>
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
tB %bb.3, 14, $noreg<br>
<br>
bb.3.while.end:<br>
- $r0 = tMOVr killed $r4, 14, $noreg<br>
- tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
+ liveins: $lr<br>
+ <br>
+ $r0 = tMOVr killed $lr, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
<br>
bb.4:<br>
- renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
- $r0 = tMOVr killed $r4, 14, $noreg<br>
- tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
+ renamable $lr = t2MOVi 0, 14, $noreg, $noreg<br>
+ $r0 = tMOVr killed $lr, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
<br>
...<br>
-<br>
<br>
Removed: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir?rev=372110&view=auto" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir?rev=372110&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir (removed)<br>
@@ -1,136 +0,0 @@<br>
-# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s<br>
-<br>
-# CHECK: while.body:<br>
-# CHECK-NOT: t2DLS<br>
-# CHECK-NOT: t2LEUpdate<br>
-<br>
---- | <br>
- define i32 @skip_spill(i32 %n) #0 {<br>
- entry:<br>
- %cmp6 = icmp eq i32 %n, 0<br>
- br i1 %cmp6, label %while.end, label %while.body.preheader<br>
- <br>
- while.body.preheader: ; preds = %entry<br>
- call void @llvm.set.loop.iterations.i32(i32 %n)<br>
- br label %while.body<br>
- <br>
- while.body: ; preds = %while.body, %while.body.preheader<br>
- %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]<br>
- %0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]<br>
- %call = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)()<br>
- %add = add nsw i32 %call, %res.07<br>
- %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
- %2 = icmp ne i32 %1, 0<br>
- br i1 %2, label %while.body, label %while.end<br>
- <br>
- while.end: ; preds = %while.body, %entry<br>
- %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]<br>
- ret i32 %res.0.lcssa<br>
- }<br>
- <br>
- declare i32 @bar(...) local_unnamed_addr #0<br>
- <br>
- ; Function Attrs: noduplicate nounwind<br>
- declare void @llvm.set.loop.iterations.i32(i32) #1<br>
- <br>
- ; Function Attrs: noduplicate nounwind<br>
- declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1<br>
- <br>
- ; Function Attrs: nounwind<br>
- declare void @llvm.stackprotector(i8*, i8**) #2<br>
- <br>
- attributes #0 = { "target-features"="+mve.fp" }<br>
- attributes #1 = { noduplicate nounwind }<br>
- attributes #2 = { nounwind }<br>
-<br>
-...<br>
----<br>
-name: skip_spill<br>
-alignment: 2<br>
-exposesReturnsTwice: false<br>
-legalized: false<br>
-regBankSelected: false<br>
-selected: false<br>
-failedISel: false<br>
-tracksRegLiveness: false<br>
-hasWinCFI: false<br>
-registers: []<br>
-liveins:<br>
- - { reg: '$r0', virtual-reg: '' }<br>
-frameInfo:<br>
- isFrameAddressTaken: false<br>
- isReturnAddressTaken: false<br>
- hasStackMap: false<br>
- hasPatchPoint: false<br>
- stackSize: 16<br>
- offsetAdjustment: 0<br>
- maxAlignment: 4<br>
- adjustsStack: true<br>
- hasCalls: true<br>
- stackProtector: ''<br>
- maxCallFrameSize: 0<br>
- cvBytesOfCalleeSavedRegisters: 0<br>
- hasOpaqueSPAdjustment: false<br>
- hasVAStart: false<br>
- hasMustTailInVarArgFunc: false<br>
- localFrameSize: 0<br>
- savePoint: ''<br>
- restorePoint: ''<br>
-fixedStack: []<br>
-stack:<br>
- - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
-callSites: []<br>
-constants: []<br>
-machineFunctionInfo: {}<br>
-body: |<br>
- bb.0.entry:<br>
- successors: %bb.4(0x30000000), %bb.1(0x50000000)<br>
- <br>
- frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
- frame-setup CFI_INSTRUCTION def_cfa_offset 16<br>
- frame-setup CFI_INSTRUCTION offset $lr, -4<br>
- frame-setup CFI_INSTRUCTION offset $r7, -8<br>
- frame-setup CFI_INSTRUCTION offset $r5, -12<br>
- frame-setup CFI_INSTRUCTION offset $r4, -16<br>
- tCBZ $r0, %bb.4<br>
- <br>
- bb.1.while.body.preheader:<br>
- successors: %bb.2(0x80000000)<br>
- <br>
- $lr = tMOVr $r0, 14, $noreg<br>
- renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
- t2DoLoopStart killed $r0<br>
- <br>
- bb.2.while.body:<br>
- successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
- <br>
- $r5 = tMOVr killed $lr, 14, $noreg<br>
- tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0<br>
- $lr = tMOVr killed $r5, 14, $noreg<br>
- renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg<br>
- renamable $lr = t2LoopDec killed renamable $lr, 1<br>
- t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
- tB %bb.3, 14, $noreg<br>
- <br>
- bb.3.while.end:<br>
- $r0 = tMOVr killed $r4, 14, $noreg<br>
- tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
- <br>
- bb.4:<br>
- renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
- $r0 = tMOVr killed $r4, 14, $noreg<br>
- tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
-<br>
-...<br>
-<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir Tue Sep 17 05:19:32 2019<br>
@@ -4,7 +4,10 @@<br>
# CHECK-NOT: t2DLS<br>
# CHECK-NOT: t2LEUpdate<br>
<br>
---- | <br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
define i32 @mov_between_dec_end(i32 %n) #0 {<br>
entry:<br>
%cmp6 = icmp eq i32 %n, 0<br>
@@ -15,7 +18,6 @@<br>
br label %while.body<br>
<br>
while.body: ; preds = %while.body, %while.body.preheader<br>
- %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]<br>
%0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]<br>
%1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
%add = add i32 %1, 2<br>
@@ -33,6 +35,9 @@<br>
; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1<br>
<br>
+ ; Function Attrs: nounwind<br>
+ declare void @llvm.stackprotector(i8*, i8**) #2<br>
+ <br>
attributes #0 = { "target-features"="+mve.fp" }<br>
attributes #1 = { noduplicate nounwind }<br>
attributes #2 = { nounwind }<br>
@@ -46,7 +51,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -56,11 +61,11 @@ frameInfo:<br>
isReturnAddressTaken: false<br>
hasStackMap: false<br>
hasPatchPoint: false<br>
- stackSize: 16<br>
+ stackSize: 8<br>
offsetAdjustment: 0<br>
maxAlignment: 4<br>
- adjustsStack: true<br>
- hasCalls: true<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
stackProtector: ''<br>
maxCallFrameSize: 0<br>
cvBytesOfCalleeSavedRegisters: 0<br>
@@ -78,51 +83,45 @@ stack:<br>
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
- - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, <br>
- stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
<br>
- debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
callSites: []<br>
constants: []<br>
machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.4(0x30000000), %bb.1(0x50000000)<br>
+ liveins: $r0, $r7, $lr<br>
<br>
- frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
- frame-setup CFI_INSTRUCTION def_cfa_offset 16<br>
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
frame-setup CFI_INSTRUCTION offset $lr, -4<br>
frame-setup CFI_INSTRUCTION offset $r7, -8<br>
- frame-setup CFI_INSTRUCTION offset $r5, -12<br>
- frame-setup CFI_INSTRUCTION offset $r4, -16<br>
tCBZ $r0, %bb.4<br>
<br>
bb.1.while.body.preheader:<br>
successors: %bb.2(0x80000000)<br>
+ liveins: $r0<br>
<br>
$lr = tMOVr $r0, 14, $noreg<br>
- renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
t2DoLoopStart killed $r0<br>
<br>
bb.2.while.body:<br>
successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr<br>
<br>
$r4 = tMOVr $lr, 14, $noreg<br>
renamable $lr = t2LoopDec killed renamable $lr, 1<br>
+ renamable $r0 = t2ADDri renamable $lr, 2, 14, $noreg, $noreg<br>
$lr = tMOVr $r4, 14, $noreg<br>
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
tB %bb.3, 14, $noreg<br>
<br>
bb.3.while.end:<br>
- $r0 = tMOVr killed $r4, 14, $noreg<br>
- tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
+ liveins: $r0<br>
+ <br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
<br>
bb.4:<br>
- renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg<br>
- $r0 = tMOVr killed $r4, 14, $noreg<br>
- tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0<br>
+ renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
<br>
...<br>
-<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir Tue Sep 17 05:19:32 2019<br>
@@ -14,6 +14,9 @@<br>
# CHECK: bb.4.while.end:<br>
<br>
--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {<br>
entry:<br>
%cmp = icmp ugt i32 %N, 2<br>
@@ -23,19 +26,19 @@<br>
%test = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)<br>
br i1 %test, label %while.body.preheader, label %while.end<br>
<br>
- while.body.preheader: ; preds = %entry, %not.preheader<br>
+ while.body.preheader: ; preds = %not.preheader, %entry<br>
%scevgep = getelementptr i16, i16* %a, i32 -1<br>
%scevgep3 = getelementptr i16, i16* %b, i32 -1<br>
br label %while.body<br>
<br>
- while.body: ; preds = %while.body.preheader, %while.body<br>
+ while.body: ; preds = %while.body, %while.body.preheader<br>
%lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]<br>
%lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]<br>
%count = phi i32 [ %count.next, %while.body ], [ %N, %while.body.preheader ]<br>
- %scevgep2 = getelementptr i16, i16* %lsr.iv, i32 1<br>
- %scevgep6 = getelementptr i16, i16* %lsr.iv4, i32 1<br>
- %load = load i16, i16* %scevgep6, align 2<br>
- store i16 %load, i16* %scevgep2, align 2<br>
+ %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1<br>
+ %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1<br>
+ %load = load i16, i16* %scevgep4, align 2<br>
+ store i16 %load, i16* %scevgep7, align 2<br>
%count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)<br>
%cmp1 = icmp ne i32 %count.next, 0<br>
%scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1<br>
@@ -46,13 +49,8 @@<br>
ret void<br>
}<br>
<br>
- ; Function Attrs: noduplicate nounwind<br>
declare i1 @llvm.test.set.loop.iterations.i32(i32) #0<br>
- <br>
- ; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0<br>
- <br>
- ; Function Attrs: nounwind<br>
declare void @llvm.stackprotector(i8*, i8**) #1<br>
<br>
attributes #0 = { noduplicate nounwind }<br>
@@ -67,7 +65,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -107,6 +105,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.1(0x40000000), %bb.2(0x40000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
@@ -118,21 +117,24 @@ body: |<br>
<br>
bb.1.not.preheader:<br>
successors: %bb.2(0x40000000), %bb.4(0x40000000)<br>
+ liveins: $lr, $r0, $r1<br>
<br>
t2WhileLoopStart renamable $lr, %bb.4, implicit-def dead $cpsr<br>
tB %bb.2, 14, $noreg<br>
<br>
bb.2.while.body.preheader:<br>
successors: %bb.3(0x80000000)<br>
+ liveins: $lr, $r0, $r1<br>
<br>
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg<br>
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg<br>
<br>
bb.3.while.body:<br>
successors: %bb.3(0x7c000000), %bb.4(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
<br>
- renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep6)<br>
- early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep2)<br>
+ renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)<br>
+ early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)<br>
renamable $lr = t2LoopDec killed renamable $lr, 1<br>
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr<br>
tB %bb.4, 14, $noreg<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir Tue Sep 17 05:19:32 2019<br>
@@ -13,6 +13,9 @@<br>
# CHECK-NEXT: tB %bb.3, 14<br>
<br>
--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 {<br>
entry:<br>
%0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)<br>
@@ -23,15 +26,15 @@<br>
%scevgep5 = getelementptr i32, i32* %b, i32 -1<br>
br label %do.body<br>
<br>
- do.body: ; preds = %do.body.preheader, %do.body<br>
+ do.body: ; preds = %do.body, %do.body.preheader<br>
%lsr.iv6 = phi i32* [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ]<br>
%lsr.iv = phi i32* [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ]<br>
%1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ]<br>
- %scevgep8 = getelementptr i32, i32* %lsr.iv6, i32 1<br>
- %scevgep4 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep = getelementptr i32, i32* %lsr.iv6, i32 1<br>
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1<br>
%size = call i32 @llvm.arm.space(i32 4096, i32 undef)<br>
- %tmp = load i32, i32* %scevgep8, align 4<br>
- store i32 %tmp, i32* %scevgep4, align 4<br>
+ %tmp = load i32, i32* %scevgep, align 4<br>
+ store i32 %tmp, i32* %scevgep1, align 4<br>
%2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)<br>
%3 = icmp ne i32 %2, 0<br>
%scevgep3 = getelementptr i32, i32* %lsr.iv, i32 1<br>
@@ -51,9 +54,6 @@<br>
; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2<br>
<br>
- ; Function Attrs: nounwind<br>
- declare void @llvm.stackprotector(i8*, i8**) #1<br>
- <br>
attributes #0 = { "target-features"="+lob" }<br>
attributes #1 = { nounwind }<br>
attributes #2 = { noduplicate nounwind }<br>
@@ -67,7 +67,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -107,6 +107,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.1(0x40000000), %bb.3(0x40000000)<br>
+ liveins: $r1, $r2, $r3, $r7, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
@@ -117,6 +118,7 @@ body: |<br>
<br>
bb.1.do.body.preheader:<br>
successors: %bb.2(0x80000000)<br>
+ liveins: $r1, $r2, $r3<br>
<br>
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg<br>
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg<br>
@@ -124,10 +126,11 @@ body: |<br>
<br>
bb.2.do.body:<br>
successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
<br>
dead renamable $r2 = SPACE 4096, undef renamable $r0<br>
- renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep8)<br>
- early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep4)<br>
+ renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep)<br>
+ early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1)<br>
renamable $lr = t2LoopDec killed renamable $lr, 1<br>
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
tB %bb.3, 14, $noreg<br>
@@ -136,4 +139,3 @@ body: |<br>
tPOP_RET 14, $noreg, def $r7, def $pc<br>
<br>
...<br>
-<br>
<br>
Added: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir?rev=372111&view=auto" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir?rev=372111&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir (added)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir Tue Sep 17 05:19:32 2019<br>
@@ -0,0 +1,124 @@<br>
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s<br>
+# CHECK: $lr = t2DLS $r0<br>
+# CHECK: $lr = tMOVr $r0, 14<br>
+# CHECK: $lr = t2LEUpdate renamable $lr, %bb.2<br>
+<br>
+# TODO: Explore the preheader to remove the redundant tMOVr<br>
+<br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
+ define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {<br>
+ entry:<br>
+ %scevgep = getelementptr i32, i32* %q, i32 -1<br>
+ %scevgep3 = getelementptr i32, i32* %p, i32 -1<br>
+ call void @llvm.set.loop.iterations.i32(i32 %n)<br>
+ br label %preheader<br>
+<br>
+ preheader:<br>
+ br label %while.body<br>
+ <br>
+ while.body: ; preds = %while.body, %entry<br>
+ %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]<br>
+ %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]<br>
+ %0 = phi i32 [ %n, %preheader ], [ %2, %while.body ]<br>
+ %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %1 = load i32, i32* %scevgep6, align 4<br>
+ store i32 %1, i32* %scevgep2, align 4<br>
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
+ %3 = icmp ne i32 %2, 0<br>
+ br i1 %3, label %while.body, label %while.end<br>
+ <br>
+ while.end: ; preds = %while.body<br>
+ ret i32 0<br>
+ }<br>
+ <br>
+ declare void @llvm.set.loop.iterations.i32(i32) #0<br>
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0<br>
+ <br>
+ attributes #0 = { noduplicate nounwind }<br>
+ attributes #1 = { nounwind }<br>
+<br>
+...<br>
+---<br>
+name: do_copy<br>
+alignment: 2<br>
+exposesReturnsTwice: false<br>
+legalized: false<br>
+regBankSelected: false<br>
+selected: false<br>
+failedISel: false<br>
+tracksRegLiveness: true<br>
+hasWinCFI: false<br>
+registers: []<br>
+liveins:<br>
+ - { reg: '$r0', virtual-reg: '' }<br>
+ - { reg: '$r1', virtual-reg: '' }<br>
+ - { reg: '$r2', virtual-reg: '' }<br>
+frameInfo:<br>
+ isFrameAddressTaken: false<br>
+ isReturnAddressTaken: false<br>
+ hasStackMap: false<br>
+ hasPatchPoint: false<br>
+ stackSize: 8<br>
+ offsetAdjustment: 0<br>
+ maxAlignment: 4<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
+ stackProtector: ''<br>
+ maxCallFrameSize: 0<br>
+ cvBytesOfCalleeSavedRegisters: 0<br>
+ hasOpaqueSPAdjustment: false<br>
+ hasVAStart: false<br>
+ hasMustTailInVarArgFunc: false<br>
+ localFrameSize: 0<br>
+ savePoint: ''<br>
+ restorePoint: ''<br>
+fixedStack: []<br>
+stack:<br>
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+callSites: []<br>
+constants: []<br>
+machineFunctionInfo: {}<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
+ <br>
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
+ frame-setup CFI_INSTRUCTION offset $lr, -4<br>
+ frame-setup CFI_INSTRUCTION offset $r7, -8<br>
+ t2DoLoopStart $r0<br>
+ renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg<br>
+ renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg<br>
+<br>
+ bb.1.preheader:<br>
+ successors: %bb.2(0x80000000)<br>
+ liveins: $r0<br>
+ $lr = tMOVr $r0, 14, $noreg<br>
+ <br>
+ bb.2.while.body:<br>
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
+ <br>
+ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)<br>
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)<br>
+ renamable $lr = t2LoopDec killed renamable $lr, 1<br>
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
+ tB %bb.3, 14, $noreg<br>
+ <br>
+ bb.3.while.end:<br>
+ $r0, dead $cpsr = tMOVi8 0, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
+<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir?rev=372111&view=auto" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir?rev=372111&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir (added)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir Tue Sep 17 05:19:32 2019<br>
@@ -0,0 +1,122 @@<br>
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s<br>
+# CHECK-NOT: $lr = t2DLS<br>
+# CHECK: $lr = tMOVr $r0, 14<br>
+# CHECK-NOT: $lr = t2LEUpdate<br>
+<br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
+ define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {<br>
+ entry:<br>
+ %scevgep = getelementptr i32, i32* %q, i32 -1<br>
+ %scevgep3 = getelementptr i32, i32* %p, i32 -1<br>
+ call void @llvm.set.loop.iterations.i32(i32 %n)<br>
+ br label %preheader<br>
+<br>
+ preheader:<br>
+ br label %while.body<br>
+ <br>
+ while.body: ; preds = %while.body, %entry<br>
+ %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]<br>
+ %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]<br>
+ %0 = phi i32 [ %n, %preheader ], [ %2, %while.body ]<br>
+ %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %1 = load i32, i32* %scevgep6, align 4<br>
+ store i32 %1, i32* %scevgep2, align 4<br>
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
+ %3 = icmp ne i32 %2, 0<br>
+ br i1 %3, label %while.body, label %while.end<br>
+ <br>
+ while.end: ; preds = %while.body<br>
+ ret i32 0<br>
+ }<br>
+ <br>
+ declare void @llvm.set.loop.iterations.i32(i32) #0<br>
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0<br>
+ <br>
+ attributes #0 = { noduplicate nounwind }<br>
+ attributes #1 = { nounwind }<br>
+<br>
+...<br>
+---<br>
+name: do_copy<br>
+alignment: 2<br>
+exposesReturnsTwice: false<br>
+legalized: false<br>
+regBankSelected: false<br>
+selected: false<br>
+failedISel: false<br>
+tracksRegLiveness: true<br>
+hasWinCFI: false<br>
+registers: []<br>
+liveins:<br>
+ - { reg: '$r0', virtual-reg: '' }<br>
+ - { reg: '$r1', virtual-reg: '' }<br>
+ - { reg: '$r2', virtual-reg: '' }<br>
+frameInfo:<br>
+ isFrameAddressTaken: false<br>
+ isReturnAddressTaken: false<br>
+ hasStackMap: false<br>
+ hasPatchPoint: false<br>
+ stackSize: 8<br>
+ offsetAdjustment: 0<br>
+ maxAlignment: 4<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
+ stackProtector: ''<br>
+ maxCallFrameSize: 0<br>
+ cvBytesOfCalleeSavedRegisters: 0<br>
+ hasOpaqueSPAdjustment: false<br>
+ hasVAStart: false<br>
+ hasMustTailInVarArgFunc: false<br>
+ localFrameSize: 0<br>
+ savePoint: ''<br>
+ restorePoint: ''<br>
+fixedStack: []<br>
+stack:<br>
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+callSites: []<br>
+constants: []<br>
+machineFunctionInfo: {}<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
+ <br>
+ frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp<br>
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
+ frame-setup CFI_INSTRUCTION offset $lr, -4<br>
+ frame-setup CFI_INSTRUCTION offset $r7, -8<br>
+ t2DoLoopStart $r0<br>
+ renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg<br>
+ renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg<br>
+<br>
+ bb.1.preheader:<br>
+ successors: %bb.2(0x80000000)<br>
+ liveins: $r0, $lr<br>
+ $lr = tMOVr $r0, 14, $noreg<br>
+ <br>
+ bb.2.while.body:<br>
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
+ <br>
+ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)<br>
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)<br>
+ renamable $lr = t2LoopDec killed renamable $lr, 1<br>
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
+ tB %bb.3, 14, $noreg<br>
+ <br>
+ bb.3.while.end:<br>
+ $r0, dead $cpsr = tMOVi8 0, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
+<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir?rev=372111&view=auto" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir?rev=372111&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir (added)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir Tue Sep 17 05:19:32 2019<br>
@@ -0,0 +1,122 @@<br>
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s<br>
+# CHECK-NOT: $lr = t2DLS<br>
+# CHECK: $lr = tMOVr $r0, 14<br>
+# CHECK-NOT: $lr = t2LEUpdate<br>
+<br>
+--- |<br>
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+ target triple = "thumbv8.1m.main"<br>
+ <br>
+ define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {<br>
+ entry:<br>
+ %scevgep = getelementptr i32, i32* %q, i32 -1<br>
+ %scevgep3 = getelementptr i32, i32* %p, i32 -1<br>
+ call void @llvm.set.loop.iterations.i32(i32 %n)<br>
+ br label %preheader<br>
+<br>
+ preheader:<br>
+ br label %while.body<br>
+ <br>
+ while.body: ; preds = %while.body, %entry<br>
+ %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]<br>
+ %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]<br>
+ %0 = phi i32 [ %n, %preheader ], [ %2, %while.body ]<br>
+ %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %1 = load i32, i32* %scevgep6, align 4<br>
+ store i32 %1, i32* %scevgep2, align 4<br>
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1<br>
+ %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1<br>
+ %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)<br>
+ %3 = icmp ne i32 %2, 0<br>
+ br i1 %3, label %while.body, label %while.end<br>
+ <br>
+ while.end: ; preds = %while.body<br>
+ ret i32 0<br>
+ }<br>
+ <br>
+ declare void @llvm.set.loop.iterations.i32(i32) #0<br>
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0<br>
+ <br>
+ attributes #0 = { noduplicate nounwind }<br>
+ attributes #1 = { nounwind }<br>
+<br>
+...<br>
+---<br>
+name: do_copy<br>
+alignment: 2<br>
+exposesReturnsTwice: false<br>
+legalized: false<br>
+regBankSelected: false<br>
+selected: false<br>
+failedISel: false<br>
+tracksRegLiveness: true<br>
+hasWinCFI: false<br>
+registers: []<br>
+liveins:<br>
+ - { reg: '$r0', virtual-reg: '' }<br>
+ - { reg: '$r1', virtual-reg: '' }<br>
+ - { reg: '$r2', virtual-reg: '' }<br>
+frameInfo:<br>
+ isFrameAddressTaken: false<br>
+ isReturnAddressTaken: false<br>
+ hasStackMap: false<br>
+ hasPatchPoint: false<br>
+ stackSize: 8<br>
+ offsetAdjustment: 0<br>
+ maxAlignment: 4<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
+ stackProtector: ''<br>
+ maxCallFrameSize: 0<br>
+ cvBytesOfCalleeSavedRegisters: 0<br>
+ hasOpaqueSPAdjustment: false<br>
+ hasVAStart: false<br>
+ hasMustTailInVarArgFunc: false<br>
+ localFrameSize: 0<br>
+ savePoint: ''<br>
+ restorePoint: ''<br>
+fixedStack: []<br>
+stack:<br>
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, <br>
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
<br>
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }<br>
+callSites: []<br>
+constants: []<br>
+machineFunctionInfo: {}<br>
+body: |<br>
+ bb.0.entry:<br>
+ successors: %bb.1(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
+ <br>
+ frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp<br>
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
+ frame-setup CFI_INSTRUCTION offset $lr, -4<br>
+ frame-setup CFI_INSTRUCTION offset $r7, -8<br>
+ t2DoLoopStart $r0<br>
+ renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def $cpsr<br>
+ renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg<br>
+<br>
+ bb.1.preheader:<br>
+ successors: %bb.2(0x80000000)<br>
+ liveins: $r0<br>
+ $lr = tMOVr $r0, 14, $noreg<br>
+ <br>
+ bb.2.while.body:<br>
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
+ <br>
+ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)<br>
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)<br>
+ renamable $lr = t2LoopDec killed renamable $lr, 1<br>
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
+ tB %bb.3, 14, $noreg<br>
+ <br>
+ bb.3.while.end:<br>
+ $r0, dead $cpsr = tMOVi8 0, 14, $noreg<br>
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0<br>
+<br>
+...<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir Tue Sep 17 05:19:32 2019<br>
@@ -3,8 +3,6 @@<br>
# CHECK-NOT: WhileLoopStart<br>
<br>
--- |<br>
- ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.ll'<br>
- source_filename = "while-size-limit.ll"<br>
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
target triple = "thumbv8.1m.main"<br>
<br>
@@ -47,8 +45,10 @@<br>
<br>
; Function Attrs: nounwind<br>
declare i32 @llvm.arm.space(i32 immarg, i32) #1<br>
+ <br>
; Function Attrs: noduplicate nounwind<br>
declare i1 @llvm.test.set.loop.iterations.i32(i32) #2<br>
+ <br>
; Function Attrs: noduplicate nounwind<br>
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2<br>
<br>
@@ -65,7 +65,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -130,6 +130,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.4(0x80000000)<br>
+ liveins: $r0, $r1, $r2, $r3, $r4, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
@@ -192,5 +193,3 @@ body: |<br>
tB %bb.2, 14, $noreg<br>
<br>
...<br>
-<br>
-<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir?rev=372111&r1=372110&r2=372111&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir?rev=372111&r1=372110&r2=372111&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir Tue Sep 17 05:19:32 2019<br>
@@ -10,8 +10,6 @@<br>
# CHECK: $lr = t2LEUpdate renamable $lr<br>
<br>
--- |<br>
- ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.ll'<br>
- source_filename = "/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.ll"<br>
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"<br>
target triple = "thumbv8.1m.main"<br>
<br>
@@ -25,14 +23,14 @@<br>
%scevgep3 = getelementptr i16, i16* %b, i32 -1<br>
br label %while.body<br>
<br>
- while.body: ; preds = %while.body.preheader, %while.body<br>
+ while.body: ; preds = %while.body, %while.body.preheader<br>
%lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]<br>
%lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]<br>
%1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]<br>
- %scevgep2 = getelementptr i16, i16* %lsr.iv, i32 1<br>
- %scevgep6 = getelementptr i16, i16* %lsr.iv4, i32 1<br>
- %2 = load i16, i16* %scevgep6, align 2, !tbaa !2<br>
- store i16 %2, i16* %scevgep2, align 2, !tbaa !2<br>
+ %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1<br>
+ %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1<br>
+ %2 = load i16, i16* %scevgep4, align 2<br>
+ store i16 %2, i16* %scevgep7, align 2<br>
%3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)<br>
%4 = icmp ne i32 %3, 0<br>
%scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1<br>
@@ -48,15 +46,6 @@<br>
<br>
attributes #0 = { noduplicate nounwind }<br>
attributes #1 = { nounwind }<br>
- <br>
- !llvm.module.flags = !{!0, !1}<br>
- <br>
- !0 = !{i32 1, !"wchar_size", i32 4}<br>
- !1 = !{i32 1, !"min_enum_size", i32 4}<br>
- !2 = !{!3, !3, i64 0}<br>
- !3 = !{!"short", !4, i64 0}<br>
- !4 = !{!"omnipotent char", !5, i64 0}<br>
- !5 = !{!"Simple C/C++ TBAA"}<br>
<br>
...<br>
---<br>
@@ -67,7 +56,7 @@ legalized: false<br>
regBankSelected: false<br>
selected: false<br>
failedISel: false<br>
-tracksRegLiveness: false<br>
+tracksRegLiveness: true<br>
hasWinCFI: false<br>
registers: []<br>
liveins:<br>
@@ -107,6 +96,7 @@ machineFunctionInfo: {}<br>
body: |<br>
bb.0.entry:<br>
successors: %bb.1(0x40000000), %bb.3(0x40000000)<br>
+ liveins: $r0, $r1, $r2, $r7, $lr<br>
<br>
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp<br>
frame-setup CFI_INSTRUCTION def_cfa_offset 8<br>
@@ -117,6 +107,7 @@ body: |<br>
<br>
bb.1.while.body.preheader:<br>
successors: %bb.2(0x80000000)<br>
+ liveins: $r0, $r1, $r2<br>
<br>
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg<br>
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg<br>
@@ -124,9 +115,10 @@ body: |<br>
<br>
bb.2.while.body:<br>
successors: %bb.2(0x7c000000), %bb.3(0x04000000)<br>
+ liveins: $lr, $r0, $r1<br>
<br>
- renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep6, !tbaa !2)<br>
- early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep2, !tbaa !2)<br>
+ renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)<br>
+ early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)<br>
renamable $lr = t2LoopDec killed renamable $lr, 1<br>
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr<br>
tB %bb.3, 14, $noreg<br>
@@ -135,4 +127,3 @@ body: |<br>
tPOP_RET 14, $noreg, def $r7, def $pc<br>
<br>
...<br>
-<br>
<br>
<br>
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