<div dir="ltr"><div>Please have a look ASAP?<br><br></div><div>Thanks</div><div><br></div><div>Galina<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Sep 11, 2019 at 1:40 PM Galina Kistanova <<a href="mailto:gkistanova@gmail.com">gkistanova@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Hello Alexander,<br><br>This commit added broken test to the builder llvm-clang-x86_64-expensive-checks-win.<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19594" target="_blank">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19594</a>:<br><br><div>. . .</div>Failing Tests (1):<br> LLVM :: CodeGen/AMDGPU/phi-elimination-end-cf.mir<br><br>The builder was already red and did not send notifications on this.<br>Please have a look?<br><br>Thanks<br><br>Galina</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Sep 10, 2019 at 3:57 AM Alexander Timofeev via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: alex-t<br>
Date: Tue Sep 10 03:58:57 2019<br>
New Revision: 371508<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=371508&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=371508&view=rev</a><br>
Log:<br>
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion.<br>
<br>
Reviewers: rampitec, vpykhtin<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D67101" rel="noreferrer" target="_blank">https://reviews.llvm.org/D67101</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h<br>
llvm/trunk/lib/CodeGen/PHIElimination.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h<br>
llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp<br>
llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-assertion.mir<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h?rev=371508&r1=371507&r2=371508&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h?rev=371508&r1=371507&r2=371508&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h Tue Sep 10 03:58:57 2019<br>
@@ -22,6 +22,7 @@<br>
#include "llvm/CodeGen/MachineCombinerPattern.h"<br>
#include "llvm/CodeGen/MachineFunction.h"<br>
#include "llvm/CodeGen/MachineInstr.h"<br>
+#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
#include "llvm/CodeGen/MachineLoopInfo.h"<br>
#include "llvm/CodeGen/MachineOperand.h"<br>
#include "llvm/CodeGen/MachineOutliner.h"<br>
@@ -1638,6 +1639,28 @@ public:<br>
return false;<br>
}<br>
<br>
+ /// During PHI eleimination lets target to make necessary checks and<br>
+ /// insert the copy to the PHI destination register in a target specific<br>
+ /// manner.<br>
+ virtual MachineInstr *createPHIDestinationCopy(<br>
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,<br>
+ const DebugLoc &DL, Register Src, Register Dst) const {<br>
+ return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)<br>
+ .addReg(Src);<br>
+ }<br>
+<br>
+ /// During PHI eleimination lets target to make necessary checks and<br>
+ /// insert the copy to the PHI destination register in a target specific<br>
+ /// manner.<br>
+ virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator InsPt,<br>
+ const DebugLoc &DL, Register Src,<br>
+ Register SrcSubReg,<br>
+ Register Dst) const {<br>
+ return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)<br>
+ .addReg(Src, 0, SrcSubReg);<br>
+ }<br>
+<br>
/// Returns a \p outliner::OutlinedFunction struct containing target-specific<br>
/// information for a set of outlining candidates.<br>
virtual outliner::OutlinedFunction getOutliningCandidateInfo(<br>
<br>
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=371508&r1=371507&r2=371508&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=371508&r1=371507&r2=371508&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Sep 10 03:58:57 2019<br>
@@ -31,7 +31,9 @@<br>
#include "llvm/CodeGen/MachineRegisterInfo.h"<br>
#include "llvm/CodeGen/SlotIndexes.h"<br>
#include "llvm/CodeGen/TargetInstrInfo.h"<br>
+#include "llvm/CodeGen/TargetLowering.h"<br>
#include "llvm/CodeGen/TargetOpcodes.h"<br>
+#include "llvm/CodeGen/TargetPassConfig.h"<br>
#include "llvm/CodeGen/TargetRegisterInfo.h"<br>
#include "llvm/CodeGen/TargetSubtargetInfo.h"<br>
#include "llvm/Pass.h"<br>
@@ -252,11 +254,12 @@ void PHIElimination::LowerPHINode(Machin<br>
// Insert a register to register copy at the top of the current block (but<br>
// after any remaining phi nodes) which copies the new incoming register<br>
// into the phi node destination.<br>
+ MachineInstr *PHICopy = nullptr;<br>
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();<br>
if (allPhiOperandsUndefined(*MPhi, *MRI))<br>
// If all sources of a PHI node are implicit_def or undef uses, just emit an<br>
// implicit_def instead of a copy.<br>
- BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),<br>
+ PHICopy = BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),<br>
TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);<br>
else {<br>
// Can we reuse an earlier PHI node? This only happens for critical edges,<br>
@@ -273,15 +276,13 @@ void PHIElimination::LowerPHINode(Machin<br>
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);<br>
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);<br>
}<br>
- BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),<br>
- TII->get(TargetOpcode::COPY), DestReg)<br>
- .addReg(IncomingReg);<br>
+ // Give the target possiblity to handle special cases fallthrough otherwise<br>
+ PHICopy = TII->createPHIDestinationCopy(MBB, AfterPHIsIt, MPhi->getDebugLoc(),<br>
+ IncomingReg, DestReg);<br>
}<br>
<br>
// Update live variable information if there is any.<br>
if (LV) {<br>
- MachineInstr &PHICopy = *std::prev(AfterPHIsIt);<br>
-<br>
if (IncomingReg) {<br>
LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);<br>
<br>
@@ -302,7 +303,7 @@ void PHIElimination::LowerPHINode(Machin<br>
// killed. Note that because the value is defined in several places (once<br>
// each for each incoming block), the "def" block and instruction fields<br>
// for the VarInfo is not filled in.<br>
- LV->addVirtualRegisterKilled(IncomingReg, PHICopy);<br>
+ LV->addVirtualRegisterKilled(IncomingReg, *PHICopy);<br>
}<br>
<br>
// Since we are going to be deleting the PHI node, if it is the last use of<br>
@@ -312,15 +313,14 @@ void PHIElimination::LowerPHINode(Machin<br>
<br>
// If the result is dead, update LV.<br>
if (isDead) {<br>
- LV->addVirtualRegisterDead(DestReg, PHICopy);<br>
+ LV->addVirtualRegisterDead(DestReg, *PHICopy);<br>
LV->removeVirtualRegisterDead(DestReg, *MPhi);<br>
}<br>
}<br>
<br>
// Update LiveIntervals for the new copy or implicit def.<br>
if (LIS) {<br>
- SlotIndex DestCopyIndex =<br>
- LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));<br>
+ SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);<br>
<br>
SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);<br>
if (IncomingReg) {<br>
@@ -406,9 +406,9 @@ void PHIElimination::LowerPHINode(Machin<br>
if (DefMI->isImplicitDef())<br>
ImpDefs.insert(DefMI);<br>
} else {<br>
- NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),<br>
- TII->get(TargetOpcode::COPY), IncomingReg)<br>
- .addReg(SrcReg, 0, SrcSubReg);<br>
+ NewSrcInstr =<br>
+ TII->createPHISourceCopy(opBlock, InsertPos, MPhi->getDebugLoc(),<br>
+ SrcReg, SrcSubReg, IncomingReg);<br>
}<br>
}<br>
<br>
@@ -457,7 +457,7 @@ void PHIElimination::LowerPHINode(Machin<br>
}<br>
} else {<br>
// We just inserted this copy.<br>
- KillInst = std::prev(InsertPos);<br>
+ KillInst = NewSrcInstr;<br>
}<br>
}<br>
assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=371508&r1=371507&r2=371508&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=371508&r1=371507&r2=371508&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Tue Sep 10 03:58:57 2019<br>
@@ -6410,3 +6410,31 @@ bool llvm::execMayBeModifiedBeforeAnyUse<br>
return true;<br>
}<br>
}<br>
+<br>
+MachineInstr *SIInstrInfo::createPHIDestinationCopy(<br>
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt,<br>
+ const DebugLoc &DL, Register Src, Register Dst) const {<br>
+ auto Cur = MBB.begin();<br>
+ do {<br>
+ if (!Cur->isPHI() && Cur->readsRegister(Dst))<br>
+ return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);<br>
+ ++Cur;<br>
+ } while (Cur != MBB.end() && Cur != LastPHIIt);<br>
+<br>
+ return TargetInstrInfo::createPHIDestinationCopy(MBB, LastPHIIt, DL, Src,<br>
+ Dst);<br>
+}<br>
+<br>
+MachineInstr *SIInstrInfo::createPHISourceCopy(<br>
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,<br>
+ const DebugLoc &DL, Register Src, Register SrcSubReg, Register Dst) const {<br>
+ if (InsPt != MBB.end() && InsPt->isPseudo() && InsPt->definesRegister(Src)) {<br>
+ InsPt++;<br>
+ return BuildMI(MBB, InsPt, InsPt->getDebugLoc(), get(TargetOpcode::COPY),<br>
+ Dst)<br>
+ .addReg(Src, 0, SrcSubReg)<br>
+ .addReg(AMDGPU::EXEC, RegState::Implicit);<br>
+ }<br>
+ return TargetInstrInfo::createPHISourceCopy(MBB, InsPt, DL, Src, SrcSubReg,<br>
+ Dst);<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=371508&r1=371507&r2=371508&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=371508&r1=371507&r2=371508&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Tue Sep 10 03:58:57 2019<br>
@@ -954,6 +954,17 @@ public:<br>
<br>
bool isBasicBlockPrologue(const MachineInstr &MI) const override;<br>
<br>
+ MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator InsPt,<br>
+ const DebugLoc &DL, Register Src,<br>
+ Register Dst) const override;<br>
+<br>
+ MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,<br>
+ MachineBasicBlock::iterator InsPt,<br>
+ const DebugLoc &DL, Register Src,<br>
+ Register SrcSubReg,<br>
+ Register Dst) const override;<br>
+<br>
/// Return a partially built integer add instruction without carry.<br>
/// Caller must add source operands.<br>
/// For pre-GFX9 it will generate unused carry destination operand.<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=371508&r1=371507&r2=371508&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=371508&r1=371507&r2=371508&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp Tue Sep 10 03:58:57 2019<br>
@@ -400,13 +400,17 @@ void SILowerControlFlow::emitLoop(Machin<br>
<br>
void SILowerControlFlow::emitEndCf(MachineInstr &MI) {<br>
MachineBasicBlock &MBB = *MI.getParent();<br>
+ MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();<br>
+ unsigned CFMask = MI.getOperand(0).getReg();<br>
+ MachineInstr *Def = MRI.getUniqueVRegDef(CFMask);<br>
const DebugLoc &DL = MI.getDebugLoc();<br>
<br>
- MachineBasicBlock::iterator InsPt = MBB.begin();<br>
- MachineInstr *NewMI =<br>
- BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)<br>
- .addReg(Exec)<br>
- .add(MI.getOperand(0));<br>
+ MachineBasicBlock::iterator InsPt =<br>
+ Def && Def->getParent() == &MBB ? std::next(MachineBasicBlock::iterator(Def))<br>
+ : MBB.begin();<br>
+ MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)<br>
+ .addReg(Exec)<br>
+ .add(MI.getOperand(0));<br>
<br>
if (LIS)<br>
LIS->ReplaceMachineInstrInMaps(MI, *NewMI);<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-assertion.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-assertion.mir?rev=371508&r1=371507&r2=371508&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-assertion.mir?rev=371508&r1=371507&r2=371508&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-assertion.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-assertion.mir Tue Sep 10 03:58:57 2019<br>
@@ -26,8 +26,8 @@ body: |<br>
<br>
# CHECK-LABEL: name: foo<br>
# CHECK: bb.3:<br>
-# CHECK-NEXT: %3:sreg_32_xm0 = COPY killed %4<br>
# CHECK-NEXT: dead %2:sreg_32_xm0 = IMPLICIT_DEF<br>
+# CHECK-NEXT: %3:sreg_32_xm0 = COPY killed %4<br>
# CHECK-NEXT: S_NOP 0, implicit killed %3<br>
<br>
<br>
<br>
Added: llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir?rev=371508&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir?rev=371508&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir (added)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir Tue Sep 10 03:58:57 2019<br>
@@ -0,0 +1,54 @@<br>
+# RUN: llc -mtriple amdgcn -run-pass livevars -run-pass phi-node-elimination -o - %s | FileCheck %s<br>
+<br>
+# CHECK-LABEL: phi-cf-test<br>
+# CHECK: bb.0:<br>
+# CHECK: [[COND:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64<br>
+# CHECK: [[IF_SOURCE0:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec<br>
+# CHECK: [[IF_INPUT_REG:%[0-9]+]]:sreg_64 = COPY killed [[IF_SOURCE0]], implicit $exec<br>
+<br>
+# CHECK: bb.1:<br>
+# CHECK: [[END_CF_ARG:%[0-9]+]]:sreg_64 = COPY killed [[IF_INPUT_REG]]<br>
+# CHECK: SI_END_CF killed [[END_CF_ARG]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec<br>
+<br>
+# CHECK: bb.2:<br>
+# CHECK: [[IF_SOURCE1:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec<br>
+# CHECK: [[IF_INPUT_REG]]:sreg_64 = COPY killed [[IF_SOURCE1]], implicit $exec<br>
+<br>
+<br>
+...<br>
+---<br>
+name: phi-cf-test<br>
+tracksRegLiveness: true<br>
+body: |<br>
+<br>
+ bb.0:<br>
+ successors: %bb.3(0x40000000), %bb.2(0x40000000)<br>
+ liveins: $vgpr0<br>
+<br>
+ %5:vgpr_32(s32) = COPY $vgpr0<br>
+ %0:sreg_64 = V_CMP_EQ_U32_e64 0, %5(s32), implicit $exec<br>
+ %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec<br>
+ %22:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec<br>
+ S_BRANCH %bb.3<br>
+<br>
+ bb.2:<br>
+ successors: %bb.3(0x80000000)<br>
+<br>
+ %24:sreg_64 = PHI %20, %bb.3, %22, %bb.0<br>
+ %23:vgpr_32 = PHI %19, %bb.3, %18, %bb.0<br>
+ SI_END_CF %24, implicit-def dead $exec, implicit-def dead $scc, implicit $exec<br>
+ %3:vgpr_32, dead %10:sreg_64 = nsw V_ADD_I32_e64 1, %23, 0, implicit $exec<br>
+<br>
+ bb.3:<br>
+ successors: %bb.3(0x40000000), %bb.2(0x40000000)<br>
+<br>
+ %4:vgpr_32 = PHI %19, %bb.3, %3, %bb.2, %18, %bb.0<br>
+ %15:sreg_32_xm0 = S_MOV_B32 61440<br>
+ %16:sreg_32_xm0 = S_MOV_B32 -1<br>
+ %17:sreg_128 = REG_SEQUENCE undef %14:sreg_32_xm0, %subreg.sub0, undef %12:sreg_32_xm0, %subreg.sub1, %16, %subreg.sub2, %15, %subreg.sub3<br>
+ BUFFER_STORE_DWORD_OFFSET %4, %17, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)<br>
+ %19:vgpr_32 = COPY %4<br>
+ %20:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec<br>
+ S_BRANCH %bb.3<br>
+<br>
+...<br>
<br>
<br>
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</blockquote></div>