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Hello,</div>
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<br>
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It should be fixed by r371761.</div>
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<br>
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Thanks,</div>
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<span style="font-family:Calibri,Helvetica,sans-serif; font-size:11pt">Austin</span></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Galina Kistanova <gkistanova@gmail.com><br>
<b>Sent:</b> Thursday, September 12, 2019 11:11 AM<br>
<b>To:</b> Kerbow, Austin <Austin.Kerbow@amd.com><br>
<b>Cc:</b> llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm] r371671 - AMDGPU: Move m0 initializations earlier</font>
<div> </div>
</div>
<div>[CAUTION: External Email]
<div>
<div dir="ltr">Hello Austin,<br>
<br>
It looks like your commit added more broken tests to the builder:<br>
<a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19619">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19619</a><br>
. . .<br>
Failing Tests (71):<br>
LLVM :: CodeGen/AMDGPU/amdgpu.private-memory.ll<br>
LLVM :: CodeGen/AMDGPU/array-ptr-calc-i32.ll<br>
LLVM :: CodeGen/AMDGPU/atomic_load_local.ll<br>
LLVM :: CodeGen/AMDGPU/atomic_store_local.ll<br>
LLVM :: CodeGen/AMDGPU/captured-frame-index.ll<br>
LLVM :: CodeGen/AMDGPU/cf-loop-on-constant.ll<br>
LLVM :: CodeGen/AMDGPU/cgp-addressing-modes.ll<br>
LLVM :: CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll<br>
LLVM :: CodeGen/AMDGPU/ds-combine-large-stride.ll<br>
LLVM :: CodeGen/AMDGPU/ds-sub-offset.ll<br>
LLVM :: CodeGen/AMDGPU/ds_read2.ll<br>
LLVM :: CodeGen/AMDGPU/ds_read2_superreg.ll<br>
LLVM :: CodeGen/AMDGPU/ds_read2st64.ll<br>
LLVM :: CodeGen/AMDGPU/ds_write2.ll<br>
LLVM :: CodeGen/AMDGPU/ds_write2st64.ll<br>
LLVM :: CodeGen/AMDGPU/extload.ll<br>
LLVM :: CodeGen/AMDGPU/fence-barrier.ll<br>
LLVM :: CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll<br>
LLVM :: CodeGen/AMDGPU/frame-index-elimination.ll<br>
LLVM :: CodeGen/AMDGPU/function-args.ll<br>
LLVM :: CodeGen/AMDGPU/function-returns.ll<br>
LLVM :: CodeGen/AMDGPU/gep-address-space.ll<br>
LLVM :: CodeGen/AMDGPU/hsa-group-segment.ll<br>
LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll<br>
LLVM :: CodeGen/AMDGPU/indirect-private-64.ll<br>
LLVM :: CodeGen/AMDGPU/insert-subvector-unused-scratch.ll<br>
LLVM :: CodeGen/AMDGPU/lds-alignment.ll<br>
LLVM :: CodeGen/AMDGPU/lds-bounds.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll<br>
LLVM :: CodeGen/AMDGPU/llvm.memcpy.ll<br>
LLVM :: CodeGen/AMDGPU/load-hi16.ll<br>
LLVM :: CodeGen/AMDGPU/load-lo16.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-f32-no-ds128.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-f32.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-f64.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-i1.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-i16.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-i32.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-i64.ll<br>
LLVM :: CodeGen/AMDGPU/load-local-i8.ll<br>
LLVM :: CodeGen/AMDGPU/load-select-ptr.ll<br>
LLVM :: CodeGen/AMDGPU/local-64.ll<br>
LLVM :: CodeGen/AMDGPU/local-atomics-fp.ll<br>
LLVM :: CodeGen/AMDGPU/local-memory.amdgcn.ll<br>
LLVM :: CodeGen/AMDGPU/local-memory.ll<br>
LLVM :: CodeGen/AMDGPU/merge-m0.mir<br>
LLVM :: CodeGen/AMDGPU/merge-stores.ll<br>
LLVM :: CodeGen/AMDGPU/nested-loop-conditions.ll<br>
LLVM :: CodeGen/AMDGPU/phi-elimination-end-cf.mir<br>
LLVM :: CodeGen/AMDGPU/private-memory-atomics.ll<br>
LLVM :: CodeGen/AMDGPU/promote-alloca-globals.ll<br>
LLVM :: CodeGen/AMDGPU/promote-alloca-no-opts.ll<br>
LLVM :: CodeGen/AMDGPU/reduce-store-width-alignment.ll<br>
LLVM :: CodeGen/AMDGPU/reorder-stores.ll<br>
LLVM :: CodeGen/AMDGPU/schedule-ilp.ll<br>
LLVM :: CodeGen/AMDGPU/schedule-regpressure-limit.ll<br>
LLVM :: CodeGen/AMDGPU/schedule-regpressure-limit2.ll<br>
LLVM :: CodeGen/AMDGPU/schedule-regpressure-limit3.ll<br>
LLVM :: CodeGen/AMDGPU/shl_add_ptr.ll<br>
LLVM :: CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll<br>
LLVM :: CodeGen/AMDGPU/store-barrier.ll<br>
LLVM :: CodeGen/AMDGPU/store-local.ll<br>
LLVM :: CodeGen/AMDGPU/store-v3i64.ll<br>
LLVM :: CodeGen/AMDGPU/store-weird-sizes.ll<br>
LLVM :: CodeGen/AMDGPU/unaligned-load-store.ll<br>
LLVM :: CodeGen/AMDGPU/vectorize-global-local.ll<br>
. . .<br>
<br>
The builder was already red and did not send notifications on this.<br>
Please have a look ASAP?<br>
<br>
Thanks<br>
<br>
Galina</div>
<br>
<div class="x_gmail_quote">
<div dir="ltr" class="x_gmail_attr">On Wed, Sep 11, 2019 at 2:26 PM Austin Kerbow via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
</div>
<blockquote class="x_gmail_quote" style="margin:0px 0px 0px 0.8ex; border-left:1px solid rgb(204,204,204); padding-left:1ex">
Author: kerbowa<br>
Date: Wed Sep 11 14:28:41 2019<br>
New Revision: 371671<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=371671&view=rev" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=371671&view=rev</a><br>
Log:<br>
AMDGPU: Move m0 initializations earlier<br>
<br>
Summary:<br>
After hoisting and merging m0 initializations schedule them as early as<br>
possible in the MBB. This helps the scheduler avoid hazards in some<br>
cases.<br>
<br>
Reviewers: rampitec, arsenm<br>
<br>
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D67450" rel="noreferrer" target="_blank">
https://reviews.llvm.org/D67450</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp<br>
llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp?rev=371671&r1=371670&r2=371671&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp?rev=371671&r1=371670&r2=371671&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp Wed Sep 11 14:28:41 2019<br>
@@ -466,6 +466,7 @@ getFirstNonPrologue(MachineBasicBlock *M<br>
// executioon.<br>
static bool hoistAndMergeSGPRInits(unsigned Reg,<br>
const MachineRegisterInfo &MRI,<br>
+ const TargetRegisterInfo *TRI,<br>
MachineDominatorTree &MDT,<br>
const TargetInstrInfo *TII) {<br>
// List of inits by immediate value.<br>
@@ -480,7 +481,7 @@ static bool hoistAndMergeSGPRInits(unsig<br>
<br>
for (auto &MI : MRI.def_instructions(Reg)) {<br>
MachineOperand *Imm = nullptr;<br>
- for (auto &MO: MI.operands()) {<br>
+ for (auto &MO : MI.operands()) {<br>
if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||<br>
(!MO.isImm() && !MO.isReg()) || (MO.isImm() && Imm)) {<br>
Imm = nullptr;<br>
@@ -585,8 +586,41 @@ static bool hoistAndMergeSGPRInits(unsig<br>
}<br>
}<br>
<br>
- for (auto MI : MergedInstrs)<br>
- MI->removeFromParent();<br>
+ // Remove initializations that were merged into another.<br>
+ for (auto &Init : Inits) {<br>
+ auto &Defs = Init.second;<br>
+ for (auto I = Defs.begin(); I != Defs.end(); ++I)<br>
+ if (MergedInstrs.count(*I)) {<br>
+ (*I)->eraseFromParent();<br>
+ I = Defs.erase(I);<br>
+ }<br>
+ }<br>
+<br>
+ // Try to schedule SGPR initializations as early as possible in the MBB.<br>
+ for (auto &Init : Inits) {<br>
+ auto &Defs = Init.second;<br>
+ for (auto MI : Defs) {<br>
+ auto MBB = MI->getParent();<br>
+ MachineInstr &BoundaryMI = *getFirstNonPrologue(MBB, TII);<br>
+ MachineBasicBlock::reverse_iterator B(BoundaryMI);<br>
+ // Check if B should actually be a bondary. If not set the previous<br>
+ // instruction as the boundary instead.<br>
+ if (!TII->isBasicBlockPrologue(*B))<br>
+ B++;<br>
+<br>
+ auto R = std::next(MI->getReverseIterator());<br>
+ const unsigned Threshold = 50;<br>
+ // Search until B or Threashold for a place to insert the initialization.<br>
+ for (unsigned I = 0; R != B && I < Threshold; ++R, ++I)<br>
+ if (R->readsRegister(Reg, TRI) || R->definesRegister(Reg, TRI) ||<br>
+ TII->isSchedulingBoundary(*R, MBB, *MBB->getParent()))<br>
+ break;<br>
+<br>
+ // Move to directly after R.<br>
+ if (&*--R != MI)<br>
+ MBB->splice(*R, MBB, MI);<br>
+ }<br>
+ }<br>
<br>
if (Changed)<br>
MRI.clearKillFlags(Reg);<br>
@@ -755,7 +789,7 @@ bool SIFixSGPRCopies::runOnMachineFuncti<br>
}<br>
<br>
if (MF.getTarget().getOptLevel() > CodeGenOpt::None && EnableM0Merge)<br>
- hoistAndMergeSGPRInits(AMDGPU::M0, MRI, *MDT, TII);<br>
+ hoistAndMergeSGPRInits(AMDGPU::M0, MRI, TRI, *MDT, TII);<br>
<br>
return true;<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=371671&r1=371670&r2=371671&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=371671&r1=371670&r2=371671&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll Wed Sep 11 14:28:41 2019<br>
@@ -26,12 +26,12 @@ define void @func_mov_fi_i32() #0 {<br>
<br>
; CI: s_sub_u32 [[SUB0:s[0-9]+|vcc_lo|vcc_hi]], s32, s33<br>
; CI-NEXT: s_sub_u32 [[SUB1:s[0-9]+|vcc_lo|vcc_hi]], s32, s33<br>
-; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[SUB1]], 6<br>
-; CI-NEXT: v_lshr_b32_e64 v0, [[SUB0]], 6<br>
-; CI-NEXT: v_add_i32_e64 v1, s{{\[[0-9]+:[0-9]+\]}}, 4, [[SCALED]]<br>
+; CI-DAG: v_lshr_b32_e64 v0, [[SUB0]], 6<br>
+; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[SUB1]], 6<br>
; CI-NOT: v_mov<br>
; CI: ds_write_b32 v0, v0<br>
-; CI-NEXT: ds_write_b32 v0, v1<br>
+; CI-NEXT: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, 4, [[SCALED]]<br>
+; CI-NEXT: ds_write_b32 v0, v0<br>
<br>
; GFX9: s_sub_u32 [[SUB0:s[0-9]+|vcc_lo|vcc_hi]], s32, s33<br>
; GFX9-NEXT: s_sub_u32 [[SUB1:s[0-9]+|vcc_lo|vcc_hi]], s32, s33<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir?rev=371671&r1=371670&r2=371671&view=diff" rel="noreferrer" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir?rev=371671&r1=371670&r2=371671&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir Wed Sep 11 14:28:41 2019<br>
@@ -1,7 +1,10 @@<br>
# RUN: llc -march=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s<br>
<br>
+# GCN-LABEL: name: merge-m0-many-init<br>
# GCN: bb.0.entry:<br>
# GCN: SI_INIT_M0 -1<br>
+# GCN-NEXT: IMPLICIT_DEF<br>
+# GCN-NEXT: IMPLICIT_DEF<br>
# GCN-NEXT: DS_WRITE_B32<br>
# GCN-NEXT: DS_WRITE_B32<br>
# GCN-NEXT: SI_INIT_M0 65536<br>
@@ -45,9 +48,8 @@<br>
# GCN-NEXT: DS_WRITE_B32<br>
# GCN-NEXT: SI_INIT_M0 -1<br>
# GCN-NEXT: DS_WRITE_B32<br>
-<br>
---<br>
-name: merge-m0-many-init<br>
+name: merge-m0-many-init<br>
registers:<br>
- { id: 0, class: vgpr_32 }<br>
- { id: 1, class: vgpr_32 }<br>
@@ -124,22 +126,24 @@ body: |<br>
<br>
...<br>
<br>
+# GCN-LABEL: name: merge-m0-dont-hoist-past-init-with-different-initializer<br>
# GCN: bb.0.entry:<br>
# GCN: SI_INIT_M0 65536<br>
+# GCN-NEXT: IMPLICIT_DEF<br>
+# GCN-NEXT: IMPLICIT_DEF<br>
# GCN-NEXT: DS_WRITE_B32<br>
<br>
-#GCN: bb.1:<br>
-#GCN-NOT: SI_INIT_M0 65536<br>
-#GCN-NOT: SI_INIT_M0 -1<br>
-<br>
-#GCN: bb.2:<br>
-#GCN: SI_INIT_M0 -1<br>
+# GCN: bb.1:<br>
+# GCN-NOT: SI_INIT_M0 65536<br>
+# GCN-NOT: SI_INIT_M0 -1<br>
<br>
-#GCN: bb.3:<br>
-#GCN: SI_INIT_M0 -1<br>
+# GCN: bb.2:<br>
+# GCN: SI_INIT_M0 -1<br>
<br>
+# GCN: bb.3:<br>
+# GCN: SI_INIT_M0 -1<br>
---<br>
-name: merge-m0-dont-hoist-past-init-with-different-initializer<br>
+name: merge-m0-dont-hoist-past-init-with-different-initializer<br>
registers:<br>
- { id: 0, class: vgpr_32 }<br>
- { id: 1, class: vgpr_32 }<br>
@@ -179,19 +183,19 @@ body: |<br>
S_ENDPGM 0<br>
...<br>
<br>
+# GCN-LABEL: name: merge-m0-after-prologue<br>
# GCN: bb.0.entry:<br>
# GCN-NOT: SI_INIT_M0<br>
# GCN: S_OR_B64<br>
# GCN-NEXT: SI_INIT_M0<br>
<br>
-#GCN: bb.1:<br>
-#GCN-NOT: SI_INIT_M0 -1<br>
-<br>
-#GCN: bb.2:<br>
-#GCN-NOT: SI_INIT_MO -1<br>
+# GCN: bb.1:<br>
+# GCN-NOT: SI_INIT_M0 -1<br>
<br>
+# GCN: bb.2:<br>
+# GCN-NOT: SI_INIT_MO -1<br>
---<br>
-name: merge-m0-after-prologue<br>
+name: merge-m0-after-prologue<br>
registers:<br>
- { id: 0, class: vgpr_32 }<br>
- { id: 1, class: vgpr_32 }<br>
@@ -223,3 +227,71 @@ body: |<br>
bb.3:<br>
S_ENDPGM 0<br>
...<br>
+<br>
+# GCN-LABEL: name: move-m0-avoid-hazard<br>
+# GCN: $m0 = S_MOV_B32 -1<br>
+# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec<br>
+# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec<br>
+---<br>
+name: move-m0-avoid-hazard<br>
+body: |<br>
+ bb.0:<br>
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec<br>
+ $m0 = S_MOV_B32 -1<br>
+ DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec<br>
+...<br>
+<br>
+# GCN-LABEL: name: move-m0-with-prologue<br>
+# GCN $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc<br>
+# GCN: $m0 = S_MOV_B32 -1<br>
+# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec<br>
+# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec<br>
+---<br>
+name: move-m0-with-prologue<br>
+body: |<br>
+ bb.0:<br>
+ liveins: $sgpr0_sgpr1<br>
+<br>
+ $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc<br>
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec<br>
+ $m0 = S_MOV_B32 -1<br>
+ DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec<br>
+...<br>
+<br>
+# GCN-LABEL: name: move-m0-different-initializer<br>
+# GCN: SI_INIT_M0 -1<br>
+# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF<br>
+# GCN: SI_INIT_M0 65536<br>
+# GCN-NEXT: S_NOP<br>
+---<br>
+name: move-m0-different-initializer<br>
+registers:<br>
+ - { id: 0, class: vgpr_32 }<br>
+ - { id: 1, class: vgpr_32 }<br>
+body: |<br>
+ bb.0:<br>
+ %0 = IMPLICIT_DEF<br>
+ %1 = IMPLICIT_DEF<br>
+ SI_INIT_M0 -1, implicit-def $m0<br>
+ DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec<br>
+ S_NOP 0<br>
+ SI_INIT_M0 65536, implicit-def $m0<br>
+ DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec<br>
+...<br>
+<br>
+# GCN-LABEL: name: move-m0-schedule-boundary<br>
+# GCN: S_SETREG<br>
+# GCN-NEXT: SI_INIT_M0 -1<br>
+---<br>
+name: move-m0-schedule-boundary<br>
+registers:<br>
+ - { id: 0, class: vgpr_32 }<br>
+ - { id: 1, class: vgpr_32 }<br>
+body: |<br>
+ bb.0:<br>
+ %0 = IMPLICIT_DEF<br>
+ %1 = IMPLICIT_DEF<br>
+ S_SETREG_IMM32_B32 0, 1<br>
+ SI_INIT_M0 -1, implicit-def $m0<br>
+ DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec<br>
+...<br>
<br>
<br>
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