<div dir="ltr">Hi Craig<div><br></div><div>I think this might have broken SelectionDag lowering for triple x86_64-unknown-linux-android for fp128 in some cases.</div><div><br></div><div>The reduced test case is:</div><div>```</div><div>target triple = "x86_64-unknown-linux-android"<br>define void @foo(fp128) {<br>BB0:<br> %a = fcmp oeq fp128 %0, 0xL00000000000000000000000000000000<br> %b = or i1 %a, %a<br> br i1 %b, label %BB1, label %BB2<br>BB1:<br> %c = uitofp i1 %a to fp128<br> br label %BB2<br>BB2:<br> %d = phi fp128 [ %0, %BB0 ], [ %c, %BB1 ]<br> ret void<br>}<br></div><div><br></div><div>```</div><div><br></div><div>Call stack is an assertion in llvm::TargetLowering::softenSetCCOperands</div><div><br></div><div>This is a reduced test case from compiling compiler-rt/lib/builtins/multc3.c with clang for android x86_64 (but x86_64-unknown-linux works too). </div><div><br></div><div>A bunch of our internal bots are blocked on this :-( </div><div><br></div><div>-Puyan</div><div><br></div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sun, Sep 8, 2019 at 6:33 PM Craig Topper via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: ctopper<br>
Date: Sun Sep 8 18:35:00 2019<br>
New Revision: 371357<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=371357&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=371357&view=rev</a><br>
Log:<br>
[X86] Use xorps to create fp128 +0.0 constants.<br>
<br>
This matches what we do for f32/f64. gcc also does this for fp128.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
llvm/trunk/test/CodeGen/X86/fp128-cast.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=371357&r1=371356&r2=371357&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=371357&r1=371356&r2=371357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Sep 8 18:35:00 2019<br>
@@ -628,6 +628,8 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FABS , MVT::f128, Custom);<br>
setOperationAction(ISD::FNEG , MVT::f128, Custom);<br>
setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);<br>
+<br>
+ addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps<br>
}<br>
<br>
addRegisterClass(MVT::f80, &X86::RFP80RegClass);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=371357&r1=371356&r2=371357&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=371357&r1=371356&r2=371357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Sep 8 18:35:00 2019<br>
@@ -464,7 +464,9 @@ let isReMaterializable = 1, isAsCheapAsA<br>
def AVX512_FsFLD0SS : I<0, Pseudo, (outs FR32X:$dst), (ins), "",<br>
[(set FR32X:$dst, fp32imm0)]>;<br>
def AVX512_FsFLD0SD : I<0, Pseudo, (outs FR64X:$dst), (ins), "",<br>
- [(set FR64X:$dst, fpimm0)]>;<br>
+ [(set FR64X:$dst, fp64imm0)]>;<br>
+ def AVX512_FsFLD0F128 : I<0, Pseudo, (outs VR128X:$dst), (ins), "",<br>
+ [(set VR128X:$dst, fp128imm0)]>;<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=371357&r1=371356&r2=371357&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=371357&r1=371356&r2=371357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sun Sep 8 18:35:00 2019<br>
@@ -963,6 +963,10 @@ def fp64imm0 : PatLeaf<(f64 fpimm), [{<br>
return N->isExactlyValue(+0.0);<br>
}]>;<br>
<br>
+def fp128imm0 : PatLeaf<(f128 fpimm), [{<br>
+ return N->isExactlyValue(+0.0);<br>
+}]>;<br>
+<br>
// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index<br>
// to VEXTRACTF128/VEXTRACTI128 imm.<br>
def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=371357&r1=371356&r2=371357&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=371357&r1=371356&r2=371357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Sep 8 18:35:00 2019<br>
@@ -497,9 +497,11 @@ bool X86InstrInfo::isReallyTriviallyReMa<br>
case X86::AVX512_512_SETALLONES:<br>
case X86::AVX512_FsFLD0SD:<br>
case X86::AVX512_FsFLD0SS:<br>
+ case X86::AVX512_FsFLD0F128:<br>
case X86::AVX_SET0:<br>
case X86::FsFLD0SD:<br>
case X86::FsFLD0SS:<br>
+ case X86::FsFLD0F128:<br>
case X86::KSET0D:<br>
case X86::KSET0Q:<br>
case X86::KSET0W:<br>
@@ -4026,6 +4028,7 @@ bool X86InstrInfo::expandPostRAPseudo(Ma<br>
case X86::V_SET0:<br>
case X86::FsFLD0SS:<br>
case X86::FsFLD0SD:<br>
+ case X86::FsFLD0F128:<br>
return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));<br>
case X86::AVX_SET0: {<br>
assert(HasAVX && "AVX not supported");<br>
@@ -4039,7 +4042,8 @@ bool X86InstrInfo::expandPostRAPseudo(Ma<br>
}<br>
case X86::AVX512_128_SET0:<br>
case X86::AVX512_FsFLD0SS:<br>
- case X86::AVX512_FsFLD0SD: {<br>
+ case X86::AVX512_FsFLD0SD:<br>
+ case X86::AVX512_FsFLD0F128: {<br>
bool HasVLX = Subtarget.hasVLX();<br>
Register SrcReg = MIB->getOperand(0).getReg();<br>
const TargetRegisterInfo *TRI = &getRegisterInfo();<br>
@@ -5152,6 +5156,8 @@ MachineInstr *X86InstrInfo::foldMemoryOp<br>
case X86::V_SET0:<br>
case X86::V_SETALLONES:<br>
case X86::AVX512_128_SET0:<br>
+ case X86::FsFLD0F128:<br>
+ case X86::AVX512_FsFLD0F128:<br>
Alignment = 16;<br>
break;<br>
case X86::MMX_SET0:<br>
@@ -5201,7 +5207,9 @@ MachineInstr *X86InstrInfo::foldMemoryOp<br>
case X86::FsFLD0SD:<br>
case X86::AVX512_FsFLD0SD:<br>
case X86::FsFLD0SS:<br>
- case X86::AVX512_FsFLD0SS: {<br>
+ case X86::AVX512_FsFLD0SS:<br>
+ case X86::FsFLD0F128:<br>
+ case X86::AVX512_FsFLD0F128: {<br>
// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.<br>
// Create a constant-pool entry and operands to load from it.<br>
<br>
@@ -5231,6 +5239,8 @@ MachineInstr *X86InstrInfo::foldMemoryOp<br>
Ty = Type::getFloatTy(MF.getFunction().getContext());<br>
else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)<br>
Ty = Type::getDoubleTy(MF.getFunction().getContext());<br>
+ else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)<br>
+ Ty = Type::getFP128Ty(MF.getFunction().getContext());<br>
else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)<br>
Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);<br>
else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=371357&r1=371356&r2=371357&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=371357&r1=371356&r2=371357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Sep 8 18:35:00 2019<br>
@@ -115,7 +115,9 @@ let isReMaterializable = 1, isAsCheapAsA<br>
def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",<br>
[(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1, NoAVX512]>;<br>
def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",<br>
- [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2, NoAVX512]>;<br>
+ [(set FR64:$dst, fp64imm0)]>, Requires<[HasSSE2, NoAVX512]>;<br>
+ def FsFLD0F128 : I<0, Pseudo, (outs VR128:$dst), (ins), "",<br>
+ [(set VR128:$dst, fp128imm0)]>, Requires<[HasSSE1, NoAVX512]>;<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/fp128-cast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-cast.ll?rev=371357&r1=371356&r2=371357&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp128-cast.ll?rev=371357&r1=371356&r2=371357&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/fp128-cast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/fp128-cast.ll Sun Sep 8 18:35:00 2019<br>
@@ -680,6 +680,57 @@ entry:<br>
ret i32 %conv<br>
}<br>
<br>
+<br>
+define i32 @TestConst128Zero(fp128 %v) nounwind {<br>
+; X64-SSE-LABEL: TestConst128Zero:<br>
+; X64-SSE: # %bb.0: # %entry<br>
+; X64-SSE-NEXT: pushq %rax<br>
+; X64-SSE-NEXT: xorps %xmm1, %xmm1<br>
+; X64-SSE-NEXT: callq __gttf2<br>
+; X64-SSE-NEXT: xorl %ecx, %ecx<br>
+; X64-SSE-NEXT: testl %eax, %eax<br>
+; X64-SSE-NEXT: setg %cl<br>
+; X64-SSE-NEXT: movl %ecx, %eax<br>
+; X64-SSE-NEXT: popq %rcx<br>
+; X64-SSE-NEXT: retq<br>
+;<br>
+; X32-LABEL: TestConst128Zero:<br>
+; X32: # %bb.0: # %entry<br>
+; X32-NEXT: subl $12, %esp<br>
+; X32-NEXT: pushl $0<br>
+; X32-NEXT: pushl $0<br>
+; X32-NEXT: pushl $0<br>
+; X32-NEXT: pushl $0<br>
+; X32-NEXT: pushl {{[0-9]+}}(%esp)<br>
+; X32-NEXT: pushl {{[0-9]+}}(%esp)<br>
+; X32-NEXT: pushl {{[0-9]+}}(%esp)<br>
+; X32-NEXT: pushl {{[0-9]+}}(%esp)<br>
+; X32-NEXT: calll __gttf2<br>
+; X32-NEXT: addl $32, %esp<br>
+; X32-NEXT: xorl %ecx, %ecx<br>
+; X32-NEXT: testl %eax, %eax<br>
+; X32-NEXT: setg %cl<br>
+; X32-NEXT: movl %ecx, %eax<br>
+; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: retl<br>
+;<br>
+; X64-AVX-LABEL: TestConst128Zero:<br>
+; X64-AVX: # %bb.0: # %entry<br>
+; X64-AVX-NEXT: pushq %rax<br>
+; X64-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1<br>
+; X64-AVX-NEXT: callq __gttf2<br>
+; X64-AVX-NEXT: xorl %ecx, %ecx<br>
+; X64-AVX-NEXT: testl %eax, %eax<br>
+; X64-AVX-NEXT: setg %cl<br>
+; X64-AVX-NEXT: movl %ecx, %eax<br>
+; X64-AVX-NEXT: popq %rcx<br>
+; X64-AVX-NEXT: retq<br>
+entry:<br>
+ %cmp = fcmp ogt fp128 %v, 0xL00000000000000000000000000000000<br>
+ %conv = zext i1 %cmp to i32<br>
+ ret i32 %conv<br>
+}<br>
+<br>
; C code:<br>
; struct TestBits_ieee_ext {<br>
; unsigned v1;<br>
@@ -833,7 +884,7 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X64-SSE-LABEL: TestTruncCopysign:<br>
; X64-SSE: # %bb.0: # %entry<br>
; X64-SSE-NEXT: cmpl $50001, %edi # imm = 0xC351<br>
-; X64-SSE-NEXT: jl .LBB17_2<br>
+; X64-SSE-NEXT: jl .LBB18_2<br>
; X64-SSE-NEXT: # %bb.1: # %if.then<br>
; X64-SSE-NEXT: pushq %rax<br>
; X64-SSE-NEXT: callq __trunctfdf2<br>
@@ -842,7 +893,7 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X64-SSE-NEXT: orps %xmm1, %xmm0<br>
; X64-SSE-NEXT: callq __extenddftf2<br>
; X64-SSE-NEXT: addq $8, %rsp<br>
-; X64-SSE-NEXT: .LBB17_2: # %cleanup<br>
+; X64-SSE-NEXT: .LBB18_2: # %cleanup<br>
; X64-SSE-NEXT: retq<br>
;<br>
; X32-LABEL: TestTruncCopysign:<br>
@@ -856,7 +907,7 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi<br>
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx<br>
; X32-NEXT: cmpl $50001, {{[0-9]+}}(%esp) # imm = 0xC351<br>
-; X32-NEXT: jl .LBB17_4<br>
+; X32-NEXT: jl .LBB18_4<br>
; X32-NEXT: # %bb.1: # %if.then<br>
; X32-NEXT: pushl %eax<br>
; X32-NEXT: pushl %ecx<br>
@@ -868,11 +919,11 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X32-NEXT: testb $-128, {{[0-9]+}}(%esp)<br>
; X32-NEXT: flds {{\.LCPI.*}}<br>
; X32-NEXT: flds {{\.LCPI.*}}<br>
-; X32-NEXT: jne .LBB17_3<br>
+; X32-NEXT: jne .LBB18_3<br>
; X32-NEXT: # %bb.2: # %if.then<br>
; X32-NEXT: fstp %st(1)<br>
; X32-NEXT: fldz<br>
-; X32-NEXT: .LBB17_3: # %if.then<br>
+; X32-NEXT: .LBB18_3: # %if.then<br>
; X32-NEXT: fstp %st(0)<br>
; X32-NEXT: subl $16, %esp<br>
; X32-NEXT: leal {{[0-9]+}}(%esp), %eax<br>
@@ -884,7 +935,7 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx<br>
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi<br>
-; X32-NEXT: .LBB17_4: # %cleanup<br>
+; X32-NEXT: .LBB18_4: # %cleanup<br>
; X32-NEXT: movl %edx, (%esi)<br>
; X32-NEXT: movl %edi, 4(%esi)<br>
; X32-NEXT: movl %ecx, 8(%esi)<br>
@@ -898,7 +949,7 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X64-AVX-LABEL: TestTruncCopysign:<br>
; X64-AVX: # %bb.0: # %entry<br>
; X64-AVX-NEXT: cmpl $50001, %edi # imm = 0xC351<br>
-; X64-AVX-NEXT: jl .LBB17_2<br>
+; X64-AVX-NEXT: jl .LBB18_2<br>
; X64-AVX-NEXT: # %bb.1: # %if.then<br>
; X64-AVX-NEXT: pushq %rax<br>
; X64-AVX-NEXT: callq __trunctfdf2<br>
@@ -908,7 +959,7 @@ define fp128 @TestTruncCopysign(fp128 %x<br>
; X64-AVX-NEXT: vorps %xmm0, %xmm1, %xmm0<br>
; X64-AVX-NEXT: callq __extenddftf2<br>
; X64-AVX-NEXT: addq $8, %rsp<br>
-; X64-AVX-NEXT: .LBB17_2: # %cleanup<br>
+; X64-AVX-NEXT: .LBB18_2: # %cleanup<br>
; X64-AVX-NEXT: retq<br>
entry:<br>
%cmp = icmp sgt i32 %n, 50000<br>
@@ -928,7 +979,7 @@ cleanup:<br>
define i1 @PR34866(i128 %x) nounwind {<br>
; X64-SSE-LABEL: PR34866:<br>
; X64-SSE: # %bb.0:<br>
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0<br>
+; X64-SSE-NEXT: xorps %xmm0, %xmm0<br>
; X64-SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; X64-SSE-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi<br>
; X64-SSE-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi<br>
@@ -948,7 +999,7 @@ define i1 @PR34866(i128 %x) nounwind {<br>
;<br>
; X64-AVX-LABEL: PR34866:<br>
; X64-AVX: # %bb.0:<br>
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0<br>
+; X64-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0<br>
; X64-AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; X64-AVX-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi<br>
; X64-AVX-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi<br>
@@ -963,7 +1014,7 @@ define i1 @PR34866(i128 %x) nounwind {<br>
define i1 @PR34866_commute(i128 %x) nounwind {<br>
; X64-SSE-LABEL: PR34866_commute:<br>
; X64-SSE: # %bb.0:<br>
-; X64-SSE-NEXT: movaps {{.*}}(%rip), %xmm0<br>
+; X64-SSE-NEXT: xorps %xmm0, %xmm0<br>
; X64-SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; X64-SSE-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi<br>
; X64-SSE-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi<br>
@@ -983,7 +1034,7 @@ define i1 @PR34866_commute(i128 %x) noun<br>
;<br>
; X64-AVX-LABEL: PR34866_commute:<br>
; X64-AVX: # %bb.0:<br>
-; X64-AVX-NEXT: vmovaps {{.*}}(%rip), %xmm0<br>
+; X64-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0<br>
; X64-AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; X64-AVX-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi<br>
; X64-AVX-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>