<div dir="ltr">Hello Jay,<br><br>This commit broke test to the builder next builder few days ago:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19470">lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19470</a><br><br>. . .<br>Failing Tests (1):<br> LLVM :: CodeGen/AMDGPU/no-initializer-constant-addrspace.ll<br><br>Please have a look ASAP?<br><br>Thanks<br><br>Galina</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Sep 2, 2019 at 7:39 AM Jay Foad via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: foad<br>
Date: Mon Sep 2 07:40:57 2019<br>
New Revision: 370667<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=370667&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=370667&view=rev</a><br>
Log:<br>
Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0"<br>
<br>
Summary:<br>
D61491 caused us to use relocs when they're not strictly necessary, to<br>
refer to symbols in the text section. This is a pessimization and it's a<br>
problem for some loaders that don't support relocs yet.<br>
<br>
Reviewers: nhaehnle, arsenm, tpr<br>
<br>
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, hiraditya, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D65813" rel="noreferrer" target="_blank">https://reviews.llvm.org/D65813</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp<br>
llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=370667&r1=370666&r2=370667&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=370667&r1=370666&r2=370667&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Mon Sep 2 07:40:57 2019<br>
@@ -5030,11 +5030,8 @@ buildPCRelGlobalAddress(SelectionDAG &DA<br>
// of the s_add_u32 instruction, we end up with an offset that is 4 bytes too<br>
// small. This requires us to add 4 to the global variable offset in order to<br>
// compute the correct address.<br>
- unsigned LoFlags = GAFlags;<br>
- if (LoFlags == SIInstrInfo::MO_NONE)<br>
- LoFlags = SIInstrInfo::MO_REL32;<br>
SDValue PtrLo =<br>
- DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, LoFlags);<br>
+ DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);<br>
SDValue PtrHi;<br>
if (GAFlags == SIInstrInfo::MO_NONE) {<br>
PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=370667&r1=370666&r2=370667&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=370667&r1=370666&r2=370667&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Mon Sep 2 07:40:57 2019<br>
@@ -514,7 +514,7 @@ bool isReadOnlySegment(const GlobalValue<br>
}<br>
<br>
bool shouldEmitConstantsToTextSection(const Triple &TT) {<br>
- return TT.getOS() != Triple::AMDHSA;<br>
+ return TT.getOS() == Triple::AMDPAL;<br>
}<br>
<br>
int getIntegerAttribute(const Function &F, StringRef Name, int Default) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll?rev=370667&r1=370666&r2=370667&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll?rev=370667&r1=370666&r2=370667&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll Mon Sep 2 07:40:57 2019<br>
@@ -1,5 +1,7 @@<br>
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s<br>
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s<br>
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=PAL %s<br>
+; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s<br>
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s<br>
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s<br>
<br>
@private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]<br>
@private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]<br>
@@ -8,23 +10,23 @@<br>
; GCN-LABEL: {{^}}private_test:<br>
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}<br>
<br>
-; Non-HSA OSes use fixup into .text section.<br>
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1<br>
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0<br>
-<br>
-; HSA OSes use relocations.<br>
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4<br>
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4<br>
+; PAL OSes use fixup into .text section.<br>
+; PAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1<br>
+; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0<br>
+<br>
+; Non-PAL OSes use relocations.<br>
+; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4<br>
+; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4<br>
<br>
; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}<br>
<br>
-; Non-HSA OSes use fixup into .text section.<br>
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2<br>
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0<br>
-<br>
-; HSA OSes use relocations.<br>
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4<br>
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4<br>
+; PAL OSes use fixup into .text section.<br>
+; PAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2<br>
+; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0<br>
+<br>
+; Non-PAL OSes use relocations.<br>
+; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4<br>
+; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4<br>
<br>
define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {<br>
%ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index<br>
@@ -36,10 +38,10 @@ define amdgpu_kernel void @private_test(<br>
ret void<br>
}<br>
<br>
-; HSA-LABEL: {{^}}available_externally_test:<br>
-; HSA: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}<br>
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4<br>
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4<br>
+; NOPAL-LABEL: {{^}}available_externally_test:<br>
+; NOPAL: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}<br>
+; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4<br>
+; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4<br>
define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) {<br>
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1<br>
%val = load i32, i32 addrspace(4)* %ptr<br>
@@ -47,8 +49,8 @@ define amdgpu_kernel void @available_ext<br>
ret void<br>
}<br>
<br>
-; NOHSA: .text<br>
-; HSA: .section .rodata<br>
+; PAL: .text<br>
+; NOPAL: .section .rodata<br>
<br>
; GCN: private1:<br>
; GCN: private2:<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll?rev=370667&r1=370666&r2=370667&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll?rev=370667&r1=370666&r2=370667&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll Mon Sep 2 07:40:57 2019<br>
@@ -2,7 +2,7 @@<br>
; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -r --symbols | FileCheck %s -check-prefix=GCN<br>
; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -r --symbols | FileCheck %s -check-prefix=EG<br>
<br>
-; GCN: R_AMDGPU_REL32_LO extern_const_addrspace<br>
+; GCN: R_AMDGPU_GOTPCREL32_LO extern_const_addrspace 0x0<br>
; EG: R_AMDGPU_ABS32 extern_const_addrspace<br>
<br>
; CHECK-DAG: Name: extern_const_addrspace<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll?rev=370667&r1=370666&r2=370667&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll?rev=370667&r1=370666&r2=370667&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll Mon Sep 2 07:40:57 2019<br>
@@ -4,13 +4,13 @@<br>
<br>
; CHECK: Relocations [<br>
; CHECK: Section (3) .rel.text {<br>
-; CHECK: 0x58 R_AMDGPU_ABS32 .text 0x0<br>
+; CHECK: 0x58 R_AMDGPU_ABS32 arr 0x0<br>
; CHECK: }<br>
; CHECK: ]<br>
<br>
; CHECK: Symbol {<br>
; CHECK: Name: arr (11)<br>
-; CHECK: Value: 0x70<br>
+; CHECK: Value: 0x0<br>
; CHECK: Size: 16<br>
; CHECK: Binding: Local (0x0)<br>
; CHECK: Type: Object (0x1)<br>
<br>
<br>
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</blockquote></div>