<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Aug 22, 2019, at 9:21 AM, Guozhi Wei via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Author: carrot<br class="">Date: Thu Aug 22 09:21:32 2019<br class="">New Revision: 369664<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=369664&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=369664&view=rev</a><br class="">Log:<br class="">[MBP] Disable aggressive loop rotate in plain mode<br class=""><br class="">Patch <a href="https://reviews.llvm.org/D43256" class="">https://reviews.llvm.org/D43256</a> introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.<br class=""><br class="">To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.<br class=""><br class="">Differential Revision: <a href="https://reviews.llvm.org/D65673" class="">https://reviews.llvm.org/D65673</a><br class=""><br class=""><br class="">Removed:<br class=""> llvm/trunk/test/CodeGen/X86/loop-rotate.ll<br class="">Modified:<br class=""> llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp<br class=""> llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll<br class=""> llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/global_smrd_cfg.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/loop_exit_with_xor.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/optimize-negated-cond.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/wave32.ll<br class=""> llvm/trunk/test/CodeGen/AMDGPU/wqm.ll<br class=""> llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll<br class=""> llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll<br class=""> llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll<br class=""> llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll<br class=""> llvm/trunk/test/CodeGen/ARM/code-placement.ll<br class=""> llvm/trunk/test/CodeGen/ARM/pr32578.ll<br class=""> llvm/trunk/test/CodeGen/Hexagon/bug6757-endloop.ll<br class=""> llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll<br class=""> llvm/trunk/test/CodeGen/Hexagon/prof-early-if.ll<br class=""> llvm/trunk/test/CodeGen/Hexagon/redundant-branching2.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/block-placement-1.mir<br class=""> llvm/trunk/test/CodeGen/PowerPC/cmp_elimination.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll<br class=""> llvm/trunk/test/CodeGen/PowerPC/machine-pre.ll<br class=""> llvm/trunk/test/CodeGen/RISCV/atomic-rmw.ll<br class=""> llvm/trunk/test/CodeGen/RISCV/remat.ll<br class=""> llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.ll<br class=""> llvm/trunk/test/CodeGen/Thumb/pr42760.ll<br class=""> llvm/trunk/test/CodeGen/X86/block-placement.ll<br class=""> llvm/trunk/test/CodeGen/X86/code_placement.ll<br class=""> llvm/trunk/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll<br class=""> llvm/trunk/test/CodeGen/X86/code_placement_no_header_change.ll<br class=""> llvm/trunk/test/CodeGen/X86/conditional-tailcall.ll<br class=""> llvm/trunk/test/CodeGen/X86/loop-blocks.ll<br class=""> llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll<br class=""> llvm/trunk/test/CodeGen/X86/move_latch_to_loop_top.ll<br class=""> llvm/trunk/test/CodeGen/X86/pr38185.ll<br class=""> llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll<br class=""> llvm/trunk/test/CodeGen/X86/reverse_branches.ll<br class=""> llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll<br class=""> llvm/trunk/test/CodeGen/X86/tail-dup-merge-loop-headers.ll<br class=""> llvm/trunk/test/CodeGen/X86/tail-dup-repeat.ll<br class=""> llvm/trunk/test/CodeGen/X86/vector-shift-by-select-loop.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_arith-1.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_arith-2.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_arith-3.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_arith-4.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_arith-5.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_arith-6.ll<br class=""> llvm/trunk/test/CodeGen/X86/widen_cast-4.ll<br class=""> llvm/trunk/test/DebugInfo/X86/PR37234.ll<br class=""> llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Thu Aug 22 09:21:32 2019<br class="">@@ -462,17 +462,20 @@ class MachineBlockPlacement : public Mac<br class=""> const MachineBasicBlock *ExitBB,<br class=""> const BlockFilterSet &LoopBlockSet);<br class=""> MachineBasicBlock *findBestLoopTopHelper(MachineBasicBlock *OldTop,<br class="">- const MachineLoop &L, const BlockFilterSet &LoopBlockSet);<br class="">+ const MachineLoop &L,<br class="">+ const BlockFilterSet &LoopBlockSet,<br class="">+ bool HasStaticProfileOnly = false);<br class=""> MachineBasicBlock *findBestLoopTop(<br class=""> const MachineLoop &L, const BlockFilterSet &LoopBlockSet);<br class="">+ MachineBasicBlock *findBestLoopTopNoProfile(<br class="">+ const MachineLoop &L, const BlockFilterSet &LoopBlockSet);<br class=""> MachineBasicBlock *findBestLoopExit(<br class="">- const MachineLoop &L, const BlockFilterSet &LoopBlockSet,<br class="">- BlockFrequency &ExitFreq);<br class="">+ const MachineLoop &L, const BlockFilterSet &LoopBlockSet);<br class=""> BlockFilterSet collectLoopBlockSet(const MachineLoop &L);<br class=""> void buildLoopChains(const MachineLoop &L);<br class=""> void rotateLoop(<br class=""> BlockChain &LoopChain, const MachineBasicBlock *ExitingBB,<br class="">- BlockFrequency ExitFreq, const BlockFilterSet &LoopBlockSet);<br class="">+ const BlockFilterSet &LoopBlockSet);<br class=""> void rotateLoopWithProfile(<br class=""> BlockChain &LoopChain, const MachineLoop &L,<br class=""> const BlockFilterSet &LoopBlockSet);<br class="">@@ -1947,11 +1950,14 @@ MachineBlockPlacement::FallThroughGains(<br class=""> /// At the same time, move it before old top increases the taken branch<br class=""> /// to loop exit block, so the reduced taken branch will be compared with<br class=""> /// the increased taken branch to the loop exit block.<br class="">+///<br class="">+/// This pattern is enabled only when HasStaticProfileOnly is false.<br class=""> MachineBasicBlock *<br class=""> MachineBlockPlacement::findBestLoopTopHelper(<br class=""> MachineBasicBlock *OldTop,<br class=""> const MachineLoop &L,<br class="">- const BlockFilterSet &LoopBlockSet) {<br class="">+ const BlockFilterSet &LoopBlockSet,<br class="">+ bool HasStaticProfileOnly) {<br class=""> // Check that the header hasn't been fused with a preheader block due to<br class=""> // crazy branches. If it has, we need to start with the header at the top to<br class=""> // prevent pulling the preheader into the loop body.<br class="">@@ -1975,22 +1981,38 @@ MachineBlockPlacement::findBestLoopTopHe<br class=""> if (Pred->succ_size() > 2)<br class=""> continue;<br class=""><br class="">- MachineBasicBlock *OtherBB = nullptr;<br class="">- if (Pred->succ_size() == 2) {<br class="">- OtherBB = *Pred->succ_begin();<br class="">- if (OtherBB == OldTop)<br class="">- OtherBB = *Pred->succ_rbegin();<br class="">- }<br class="">-<br class=""> if (!canMoveBottomBlockToTop(Pred, OldTop))<br class=""> continue;<br class=""><br class="">- BlockFrequency Gains = FallThroughGains(Pred, OldTop, OtherBB,<br class="">- LoopBlockSet);<br class="">- if ((Gains > 0) && (Gains > BestGains ||<br class="">- ((Gains == BestGains) && Pred->isLayoutSuccessor(OldTop)))) {<br class="">- BestPred = Pred;<br class="">- BestGains = Gains;<br class="">+ if (HasStaticProfileOnly) {<br class="">+ // In plain mode we consider pattern 1 only.<br class="">+ if (Pred->succ_size() > 1)<br class="">+ continue;<br class="">+<br class="">+ BlockFrequency PredFreq = MBFI->getBlockFreq(Pred);<br class="">+ if (!BestPred || PredFreq > BestGains ||<br class="">+ (!(PredFreq < BestGains) &&<br class="">+ Pred->isLayoutSuccessor(OldTop))) {<br class="">+ BestPred = Pred;<br class="">+ BestGains = PredFreq;<br class="">+ }<br class="">+ } else {<br class="">+ // With profile information we also consider pattern 2.<br class="">+ MachineBasicBlock *OtherBB = nullptr;<br class="">+ if (Pred->succ_size() == 2) {<br class="">+ OtherBB = *Pred->succ_begin();<br class="">+ if (OtherBB == OldTop)<br class="">+ OtherBB = *Pred->succ_rbegin();<br class="">+ }<br class="">+<br class="">+ // And more sophisticated cost model.<br class="">+ BlockFrequency Gains = FallThroughGains(Pred, OldTop, OtherBB,<br class="">+ LoopBlockSet);<br class="">+ if ((Gains > 0) && (Gains > BestGains ||<br class="">+ ((Gains == BestGains) && Pred->isLayoutSuccessor(OldTop)))) {<br class="">+ BestPred = Pred;<br class="">+ BestGains = Gains;<br class="">+ }<br class=""> }<br class=""> }<br class=""><br class="">@@ -2010,7 +2032,7 @@ MachineBlockPlacement::findBestLoopTopHe<br class=""> return BestPred;<br class=""> }<br class=""><br class="">-/// Find the best loop top block for layout.<br class="">+/// Find the best loop top block for layout in FDO mode.<br class=""> ///<br class=""> /// This function iteratively calls findBestLoopTopHelper, until no new better<br class=""> /// BB can be found.<br class="">@@ -2038,6 +2060,34 @@ MachineBlockPlacement::findBestLoopTop(c<br class=""> return NewTop;<br class=""> }<br class=""><br class="">+/// Find the best loop top block for layout in plain mode. It is less agressive<br class="">+/// than findBestLoopTop.<br class="">+///<br class="">+/// Look for a block which is strictly better than the loop header for laying<br class="">+/// out at the top of the loop. This looks for one and only one pattern:<br class="">+/// a latch block with no conditional exit. This block will cause a conditional<br class="">+/// jump around it or will be the bottom of the loop if we lay it out in place,<br class="">+/// but if it doesn't end up at the bottom of the loop for any reason,<br class="">+/// rotation alone won't fix it. Because such a block will always result in an<br class="">+/// unconditional jump (for the backedge) rotating it in front of the loop<br class="">+/// header is always profitable.<br class="">+MachineBasicBlock *<br class="">+MachineBlockPlacement::findBestLoopTopNoProfile(<br class="">+ const MachineLoop &L,<br class="">+ const BlockFilterSet &LoopBlockSet) {<br class="">+ // Placing the latch block before the header may introduce an extra branch<br class="">+ // that skips this block the first time the loop is executed, which we want<br class="">+ // to avoid when optimising for size.<br class="">+ // FIXME: in theory there is a case that does not introduce a new branch,<br class="">+ // i.e. when the layout predecessor does not fallthrough to the loop header.<br class="">+ // In practice this never happens though: there always seems to be a preheader<br class="">+ // that can fallthrough and that is also placed before the header.<br class="">+ if (F->getFunction().hasOptSize())<br class="">+ return L.getHeader();<br class="">+<br class="">+ return findBestLoopTopHelper(L.getHeader(), L, LoopBlockSet, true);<br class="">+}<br class="">+<br class=""> /// Find the best loop exiting block for layout.<br class=""> ///<br class=""> /// This routine implements the logic to analyze the loop looking for the best<br class="">@@ -2045,8 +2095,7 @@ MachineBlockPlacement::findBestLoopTop(c<br class=""> /// fallthrough opportunities.<br class=""> MachineBasicBlock *<br class=""> MachineBlockPlacement::findBestLoopExit(const MachineLoop &L,<br class="">- const BlockFilterSet &LoopBlockSet,<br class="">- BlockFrequency &ExitFreq) {<br class="">+ const BlockFilterSet &LoopBlockSet) {<br class=""> // We don't want to layout the loop linearly in all cases. If the loop header<br class=""> // is just a normal basic block in the loop, we want to look for what block<br class=""> // within the loop is the best one to layout at the top. However, if the loop<br class="">@@ -2157,7 +2206,6 @@ MachineBlockPlacement::findBestLoopExit(<br class=""><br class=""> LLVM_DEBUG(dbgs() << " Best exiting block: " << getBlockName(ExitingBB)<br class=""> << "\n");<br class="">- ExitFreq = BestExitEdgeFreq;<br class=""> return ExitingBB;<br class=""> }<br class=""><br class="">@@ -2202,7 +2250,6 @@ MachineBlockPlacement::hasViableTopFallt<br class=""> /// of its bottom already, don't rotate it.<br class=""> void MachineBlockPlacement::rotateLoop(BlockChain &LoopChain,<br class=""> const MachineBasicBlock *ExitingBB,<br class="">- BlockFrequency ExitFreq,<br class=""> const BlockFilterSet &LoopBlockSet) {<br class=""> if (!ExitingBB)<br class=""> return;<br class="">@@ -2226,12 +2273,6 @@ void MachineBlockPlacement::rotateLoop(B<br class=""> (!SuccChain || Succ == *SuccChain->begin()))<br class=""> return;<br class=""> }<br class="">-<br class="">- // Rotate will destroy the top fallthrough, we need to ensure the new exit<br class="">- // frequency is larger than top fallthrough.<br class="">- BlockFrequency FallThrough2Top = TopFallThroughFreq(Top, LoopBlockSet);<br class="">- if (FallThrough2Top >= ExitFreq)<br class="">- return;<br class=""> }<br class=""><br class=""> BlockChain::iterator ExitIt = llvm::find(LoopChain, ExitingBB);<br class="">@@ -2483,7 +2524,10 @@ void MachineBlockPlacement::buildLoopCha<br class=""> // loop. This will default to the header, but may end up as one of the<br class=""> // predecessors to the header if there is one which will result in strictly<br class=""> // fewer branches in the loop body.<br class="">- MachineBasicBlock *LoopTop = findBestLoopTop(L, LoopBlockSet);<br class="">+ MachineBasicBlock *LoopTop =<br class="">+ (RotateLoopWithProfile || F->getFunction().hasProfileData()) ?<br class="">+ findBestLoopTop(L, LoopBlockSet) :<br class="">+ findBestLoopTopNoProfile(L, LoopBlockSet);<br class=""><br class=""> // If we selected just the header for the loop top, look for a potentially<br class=""> // profitable exit block in the event that rotating the loop can eliminate<br class="">@@ -2492,9 +2536,8 @@ void MachineBlockPlacement::buildLoopCha<br class=""> // Loops are processed innermost to uttermost, make sure we clear<br class=""> // PreferredLoopExit before processing a new loop.<br class=""> PreferredLoopExit = nullptr;<br class="">- BlockFrequency ExitFreq;<br class=""> if (!RotateLoopWithProfile && LoopTop == L.getHeader())<br class="">- PreferredLoopExit = findBestLoopExit(L, LoopBlockSet, ExitFreq);<br class="">+ PreferredLoopExit = findBestLoopExit(L, LoopBlockSet);<br class=""><br class=""> BlockChain &LoopChain = *BlockToChain[LoopTop];<br class=""><br class="">@@ -2511,10 +2554,11 @@ void MachineBlockPlacement::buildLoopCha<br class=""><br class=""> buildChain(LoopTop, LoopChain, &LoopBlockSet);<br class=""><br class="">- if (RotateLoopWithProfile)<br class="">- rotateLoopWithProfile(LoopChain, L, LoopBlockSet);<br class="">- else<br class="">- rotateLoop(LoopChain, PreferredLoopExit, ExitFreq, LoopBlockSet);<br class="">+ if (RotateLoopWithProfile) {<br class="">+ if (LoopTop == L.getHeader())<br class="">+ rotateLoopWithProfile(LoopChain, L, LoopBlockSet);<br class="">+ } else<br class="">+ rotateLoop(LoopChain, PreferredLoopExit, LoopBlockSet);<br class=""><br class=""> LLVM_DEBUG({<br class=""> // Crash at the end so we get all of the debugging output first.<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AArch64/cmpxchg-idioms.ll Thu Aug 22 09:21:32 2019<br class="">@@ -111,7 +111,7 @@ define i1 @test_conditional2(i32 %a, i32<br class=""> ; CHECK: mov w22, #2<br class=""> ; CHECK-NOT: mov w22, #4<br class=""> ; CHECK-NOT: cmn w22, #4<br class="">-; CHECK: [[LOOP2:LBB[0-9]+_[0-9]+]]: ; %for.cond<br class="">+; CHECK: b [[LOOP2:LBB[0-9]+_[0-9]+]]<br class=""> ; CHECK-NOT: b.ne [[LOOP2]]<br class=""> ; CHECK-NOT: b {{LBB[0-9]+_[0-9]+}}<br class=""> ; CHECK: bl _foo<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll Thu Aug 22 09:21:32 2019<br class="">@@ -1,8 +1,9 @@<br class=""> ; RUN: llc <%s -mtriple=aarch64-eabi -verify-machine-dom-info | FileCheck %s<br class=""><br class=""> ; CHECK-LABEL: test:<br class="">-; CHECK-LABEL: %cond.false12.i<br class="">-; CHECK: b.gt<span class="Apple-tab-span" style="white-space:pre"> </span><br class="">+; CHECK: LBB0_7:<br class="">+; CHECK: b.hi<span class="Apple-tab-span" style="white-space:pre"> </span><br class="">+; CHECK-NEXT: b<span class="Apple-tab-span" style="white-space:pre"> </span><br class=""> ; CHECK-NEXT: LBB0_8:<br class=""> ; CHECK-NEXT: mov<span class="Apple-tab-span" style="white-space:pre"> </span> x8, x9<br class=""> ; CHECK-NEXT: LBB0_9:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.ll Thu Aug 22 09:21:32 2019<br class="">@@ -230,11 +230,6 @@ bb.end:<br class=""> ; Make sure scc liveness is updated if sor_b64 is removed<br class=""> ; ALL-LABEL: {{^}}scc_liveness:<br class=""><br class="">-; GCN: %bb10<br class="">-; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}<br class="">-; GCN: s_andn2_b64<br class="">-; GCN-NEXT: s_cbranch_execz<br class="">-<br class=""> ; GCN: [[BB1_LOOP:BB[0-9]+_[0-9]+]]:<br class=""> ; GCN: s_andn2_b64 exec, exec,<br class=""> ; GCN-NEXT: s_cbranch_execnz [[BB1_LOOP]]<br class="">@@ -245,6 +240,10 @@ bb.end:<br class=""> ; GCN-NOT: s_or_b64 exec, exec<br class=""><br class=""> ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}<br class="">+; GCN: s_andn2_b64<br class="">+; GCN-NEXT: s_cbranch_execnz<br class="">+<br class="">+; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}<br class=""> ; GCN: buffer_store_dword<br class=""> ; GCN: buffer_store_dword<br class=""> ; GCN: buffer_store_dword<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll Thu Aug 22 09:21:32 2019<br class="">@@ -20,41 +20,38 @@ define amdgpu_ps void @main(i32, float)<br class=""> ; CHECK-NEXT: ; implicit-def: $sgpr8_sgpr9<br class=""> ; CHECK-NEXT: ; implicit-def: $sgpr6_sgpr7<br class=""> ; CHECK-NEXT: ; implicit-def: $sgpr2_sgpr3<br class="">-; CHECK-NEXT: s_branch BB0_3<br class="">-; CHECK-NEXT: BB0_1: ; %Flow1<br class="">-; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1<br class="">-; CHECK-NEXT: s_or_b64 exec, exec, s[8:9]<br class="">-; CHECK-NEXT: s_mov_b64 s[8:9], 0<br class="">-; CHECK-NEXT: BB0_2: ; %Flow<br class="">-; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1<br class="">-; CHECK-NEXT: s_and_b64 s[10:11], exec, s[6:7]<br class="">-; CHECK-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]<br class="">-; CHECK-NEXT: s_andn2_b64 s[2:3], s[2:3], exec<br class="">-; CHECK-NEXT: s_and_b64 s[4:5], s[8:9], exec<br class="">-; CHECK-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]<br class="">-; CHECK-NEXT: s_mov_b64 s[4:5], s[10:11]<br class="">-; CHECK-NEXT: s_andn2_b64 exec, exec, s[10:11]<br class="">-; CHECK-NEXT: s_cbranch_execz BB0_6<br class="">-; CHECK-NEXT: BB0_3: ; %loop<br class="">+; CHECK-NEXT: BB0_1: ; %loop<br class=""> ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1<br class=""> ; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 32, v1<br class=""> ; CHECK-NEXT: s_and_b64 vcc, exec, vcc<br class=""> ; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], exec<br class=""> ; CHECK-NEXT: s_or_b64 s[8:9], s[8:9], exec<br class="">-; CHECK-NEXT: s_cbranch_vccz BB0_2<br class="">-; CHECK-NEXT: ; %bb.4: ; %endif1<br class="">-; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1<br class="">+; CHECK-NEXT: s_cbranch_vccz BB0_5<br class="">+; CHECK-NEXT: ; %bb.2: ; %endif1<br class="">+; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: s_mov_b64 s[6:7], -1<br class=""> ; CHECK-NEXT: s_and_saveexec_b64 s[8:9], s[0:1]<br class=""> ; CHECK-NEXT: s_xor_b64 s[8:9], exec, s[8:9]<br class="">-; CHECK-NEXT: ; mask branch BB0_1<br class="">-; CHECK-NEXT: s_cbranch_execz BB0_1<br class="">-; CHECK-NEXT: BB0_5: ; %endif2<br class="">-; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1<br class="">+; CHECK-NEXT: ; mask branch BB0_4<br class="">+; CHECK-NEXT: BB0_3: ; %endif2<br class="">+; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: v_add_u32_e32 v1, 1, v1<br class=""> ; CHECK-NEXT: s_xor_b64 s[6:7], exec, -1<br class="">-; CHECK-NEXT: s_branch BB0_1<br class="">-; CHECK-NEXT: BB0_6: ; %Flow2<br class="">+; CHECK-NEXT: BB0_4: ; %Flow1<br class="">+; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1<br class="">+; CHECK-NEXT: s_or_b64 exec, exec, s[8:9]<br class="">+; CHECK-NEXT: s_mov_b64 s[8:9], 0<br class="">+; CHECK-NEXT: BB0_5: ; %Flow<br class="">+; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1<br class="">+; CHECK-NEXT: s_and_b64 s[10:11], exec, s[6:7]<br class="">+; CHECK-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]<br class="">+; CHECK-NEXT: s_andn2_b64 s[2:3], s[2:3], exec<br class="">+; CHECK-NEXT: s_and_b64 s[4:5], s[8:9], exec<br class="">+; CHECK-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]<br class="">+; CHECK-NEXT: s_mov_b64 s[4:5], s[10:11]<br class="">+; CHECK-NEXT: s_andn2_b64 exec, exec, s[10:11]<br class="">+; CHECK-NEXT: s_cbranch_execnz BB0_1<br class="">+; CHECK-NEXT: ; %bb.6: ; %Flow2<br class=""> ; CHECK-NEXT: s_or_b64 exec, exec, s[10:11]<br class=""> ; CHECK-NEXT: v_mov_b32_e32 v1, 0<br class=""> ; CHECK-NEXT: s_and_saveexec_b64 s[0:1], s[2:3]<br class="">@@ -65,7 +62,6 @@ define amdgpu_ps void @main(i32, float)<br class=""> ; CHECK-NEXT: s_or_b64 exec, exec, s[0:1]<br class=""> ; CHECK-NEXT: exp mrt0 v1, v1, v1, v1 done vm<br class=""> ; CHECK-NEXT: s_endpgm<br class="">-; this is the divergent branch with the condition not marked as divergent<br class=""> start:<br class=""> %v0 = call float @llvm.amdgcn.interp.p1(float %1, i32 0, i32 0, i32 %0)<br class=""> br label %loop<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/global_smrd_cfg.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/global_smrd_cfg.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/global_smrd_cfg.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/global_smrd_cfg.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/global_smrd_cfg.ll Thu Aug 22 09:21:32 2019<br class="">@@ -1,28 +1,27 @@<br class=""> ; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s<br class=""><br class="">-; CHECK-LABEL: %bb22<br class="">+; CHECK-LABEL: %bb11<br class=""><br class="">-; Load from %arg has alias store in Loop<br class="">+; Load from %arg in a Loop body has alias store<br class=""><br class=""> ; CHECK: flat_load_dword<br class=""><br class="">-; #####################################################################<br class="">-<br class="">-; Load from %arg1 has no-alias store in Loop - arg1[i+1] never alias arg1[i]<br class="">-<br class="">-; CHECK: s_load_dword<br class="">+; CHECK-LABEL: %bb20<br class="">+; CHECK: flat_store_dword<br class=""><br class=""> ; #####################################################################<br class=""><br class="">-; CHECK-LABEL: %bb11<br class="">+; CHECK-LABEL: %bb22<br class=""><br class="">-; Load from %arg in a Loop body has alias store<br class="">+; Load from %arg has alias store in Loop<br class=""><br class=""> ; CHECK: flat_load_dword<br class=""><br class="">-; CHECK-LABEL: %bb20<br class="">+; #####################################################################<br class=""><br class="">-; CHECK: flat_store_dword<br class="">+; Load from %arg1 has no-alias store in Loop - arg1[i+1] never alias arg1[i]<br class="">+<br class="">+; CHECK: s_load_dword<br class=""><br class=""> define amdgpu_kernel void @cfg(i32 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) #0 {<br class=""> bb:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll Thu Aug 22 09:21:32 2019<br class="">@@ -3,20 +3,20 @@<br class=""><br class=""> ; SI-LABEL: {{^}}i1_copy_from_loop:<br class=""> ;<br class="">-; SI: ; %Flow<br class="">-; SI-DAG: s_andn2_b64 [[LCSSA_ACCUM:s\[[0-9]+:[0-9]+\]]], [[LCSSA_ACCUM]], exec<br class="">-; SI-DAG: s_and_b64 [[CC_MASK2:s\[[0-9]+:[0-9]+\]]], [[CC_ACCUM:s\[[0-9]+:[0-9]+\]]], exec<br class="">-; SI: s_or_b64 [[LCSSA_ACCUM]], [[LCSSA_ACCUM]], [[CC_MASK2]]<br class="">-<br class=""> ; SI: ; %for.body<br class=""> ; SI: v_cmp_gt_u32_e64 [[CC_SREG:s\[[0-9]+:[0-9]+\]]], 4,<br class="">-; SI-DAG: s_andn2_b64 [[CC_ACCUM]], [[CC_ACCUM]], exec<br class="">+; SI-DAG: s_andn2_b64 [[CC_ACCUM:s\[[0-9]+:[0-9]+\]]], [[CC_ACCUM]], exec<br class=""> ; SI-DAG: s_and_b64 [[CC_MASK:s\[[0-9]+:[0-9]+\]]], [[CC_SREG]], exec<br class=""> ; SI: s_or_b64 [[CC_ACCUM]], [[CC_ACCUM]], [[CC_MASK]]<br class=""><br class=""> ; SI: ; %Flow1<br class=""> ; SI: s_or_b64 [[CC_ACCUM]], [[CC_ACCUM]], exec<br class=""><br class="">+; SI: ; %Flow<br class="">+; SI-DAG: s_andn2_b64 [[LCSSA_ACCUM:s\[[0-9]+:[0-9]+\]]], [[LCSSA_ACCUM]], exec<br class="">+; SI-DAG: s_and_b64 [[CC_MASK2:s\[[0-9]+:[0-9]+\]]], [[CC_ACCUM]], exec<br class="">+; SI: s_or_b64 [[LCSSA_ACCUM]], [[LCSSA_ACCUM]], [[CC_MASK2]]<br class="">+<br class=""> ; SI: ; %for.end<br class=""> ; SI: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[LCSSA_ACCUM]]<br class=""><br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll Thu Aug 22 09:21:32 2019<br class="">@@ -630,7 +630,12 @@ define amdgpu_kernel void @insertelement<br class=""> ; GCN-LABEL: {{^}}broken_phi_bb:<br class=""> ; GCN: v_mov_b32_e32 [[PHIREG:v[0-9]+]], 8<br class=""><br class="">-; GCN: [[BB2:BB[0-9]+_[0-9]+]]:<br class="">+; GCN: s_branch [[BB2:BB[0-9]+_[0-9]+]]<br class="">+<br class="">+; GCN: {{^BB[0-9]+_[0-9]+}}:<br class="">+; GCN: s_mov_b64 exec,<br class="">+<br class="">+; GCN: [[BB2]]:<br class=""> ; GCN: v_cmp_le_i32_e32 vcc, s{{[0-9]+}}, [[PHIREG]]<br class=""> ; GCN: buffer_load_dword<br class=""><br class="">@@ -642,11 +647,6 @@ define amdgpu_kernel void @insertelement<br class=""> ; IDXMODE: s_set_gpr_idx_off<br class=""><br class=""> ; GCN: s_cbranch_execnz [[REGLOOP]]<br class="">-<br class="">-; GCN: {{^; %bb.[0-9]}}:<br class="">-; GCN: s_mov_b64 exec,<br class="">-; GCN: s_branch [[BB2]]<br class="">-<br class=""> define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) #0 {<br class=""> bb:<br class=""> br label %bb2<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/loop_exit_with_xor.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/loop_exit_with_xor.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/loop_exit_with_xor.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/loop_exit_with_xor.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/loop_exit_with_xor.ll Thu Aug 22 09:21:32 2019<br class="">@@ -61,9 +61,9 @@ loopexit:<br class=""><br class=""> ; GCN-LABEL: {{^}}break_cond_is_arg:<br class=""> ; GCN: s_xor_b64 [[REG1:[^ ,]*]], {{[^ ,]*, -1$}}<br class="">-; GCN: s_andn2_b64 exec, exec, [[REG3:[^ ,]*]]<br class=""> ; GCN: s_and_b64 [[REG2:[^ ,]*]], exec, [[REG1]]<br class="">-; GCN: s_or_b64 [[REG3]], [[REG2]],<br class="">+; GCN: s_or_b64 [[REG3:[^ ,]*]], [[REG2]],<br class="">+; GCN: s_andn2_b64 exec, exec, [[REG3]]<br class=""><br class=""> define void @break_cond_is_arg(i32 %arg, i1 %breakcond) {<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll Thu Aug 22 09:21:32 2019<br class="">@@ -24,29 +24,13 @@<br class=""> ; GCN: ; %main_body<br class=""> ; GCN: s_mov_b64 [[LEFT_OUTER:s\[[0-9]+:[0-9]+\]]], 0{{$}}<br class=""><br class="">-; GCN: [[FLOW2:BB[0-9]+_[0-9]+]]: ; %Flow2<br class="">-; GCN: s_or_b64 exec, exec, [[TMP0:s\[[0-9]+:[0-9]+\]]]<br class="">-; GCN: s_and_b64 [[TMP1:s\[[0-9]+:[0-9]+\]]], exec, [[BREAK_OUTER:s\[[0-9]+:[0-9]+\]]]<br class="">-; GCN: s_or_b64 [[TMP1]], [[TMP1]], [[LEFT_OUTER]]<br class="">-; GCN: s_mov_b64 [[LEFT_OUTER]], [[TMP1]]<br class="">-; GCN: s_andn2_b64 exec, exec, [[TMP1]]<br class="">-; GCN: s_cbranch_execz [[IF_BLOCK:BB[0-9]+_[0-9]+]]<br class="">-<br class=""> ; GCN: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP.outer{{$}}<br class=""> ; GCN: s_mov_b64 [[LEFT_INNER:s\[[0-9]+:[0-9]+\]]], 0{{$}}<br class=""><br class="">-; GCN: ; %Flow<br class="">-; GCN: s_or_b64 exec, exec, [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]]<br class="">-; GCN: s_and_b64 [[TMP0]], exec, [[BREAK_INNER:s\[[0-9]+:[0-9]+\]]]<br class="">-; GCN: s_or_b64 [[TMP0]], [[TMP0]], [[LEFT_INNER]]<br class="">-; GCN: s_mov_b64 [[LEFT_INNER]], [[TMP0]]<br class="">-; GCN: s_andn2_b64 exec, exec, [[TMP0]]<br class="">-; GCN: s_cbranch_execz [[FLOW2]]<br class="">-<br class=""> ; GCN: [[INNER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP{{$}}<br class="">-; GCN: s_or_b64 [[BREAK_OUTER]], [[BREAK_OUTER]], exec<br class="">-; GCN: s_or_b64 [[BREAK_INNER]], [[BREAK_INNER]], exec<br class="">-; GCN: s_and_saveexec_b64 [[SAVE_EXEC]], vcc<br class="">+; GCN: s_or_b64 [[BREAK_OUTER:s\[[0-9]+:[0-9]+\]]], [[BREAK_OUTER]], exec<br class="">+; GCN: s_or_b64 [[BREAK_INNER:s\[[0-9]+:[0-9]+\]]], [[BREAK_INNER]], exec<br class="">+; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc<br class=""><br class=""> ; FIXME: duplicate comparison<br class=""> ; GCN: ; %ENDIF<br class="">@@ -59,7 +43,23 @@<br class=""> ; GCN-DAG: s_or_b64 [[BREAK_OUTER]], [[BREAK_OUTER]], [[TMP_EQ]]<br class=""> ; GCN-DAG: s_or_b64 [[BREAK_INNER]], [[BREAK_INNER]], [[TMP_NE]]<br class=""><br class="">-; GCN: [[IF_BLOCK]]: ; %IF<br class="">+; GCN: ; %Flow<br class="">+; GCN: s_or_b64 exec, exec, [[SAVE_EXEC]]<br class="">+; GCN: s_and_b64 [[TMP0:s\[[0-9]+:[0-9]+\]]], exec, [[BREAK_INNER]]<br class="">+; GCN: s_or_b64 [[TMP0]], [[TMP0]], [[LEFT_INNER]]<br class="">+; GCN: s_mov_b64 [[LEFT_INNER]], [[TMP0]]<br class="">+; GCN: s_andn2_b64 exec, exec, [[TMP0]]<br class="">+; GCN: s_cbranch_execnz [[INNER_LOOP]]<br class="">+<br class="">+; GCN: ; %Flow2<br class="">+; GCN: s_or_b64 exec, exec, [[TMP0]]<br class="">+; GCN: s_and_b64 [[TMP1:s\[[0-9]+:[0-9]+\]]], exec, [[BREAK_OUTER]]<br class="">+; GCN: s_or_b64 [[TMP1]], [[TMP1]], [[LEFT_OUTER]]<br class="">+; GCN: s_mov_b64 [[LEFT_OUTER]], [[TMP1]]<br class="">+; GCN: s_andn2_b64 exec, exec, [[TMP1]]<br class="">+; GCN: s_cbranch_execnz [[OUTER_LOOP]]<br class="">+<br class="">+; GCN: ; %IF<br class=""> ; GCN-NEXT: s_endpgm<br class=""> define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {<br class=""> main_body:<br class="">@@ -92,18 +92,12 @@ ENDIF:<br class=""> ; GCN-LABEL: {{^}}multi_if_break_loop:<br class=""> ; GCN: s_mov_b64 [[LEFT:s\[[0-9]+:[0-9]+\]]], 0{{$}}<br class=""><br class="">-; GCN: ; %Flow4<br class="">-; GCN: s_and_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[BREAK]]<br class="">-; GCN: s_or_b64 [[LEFT]], [[BREAK]], [[OLD_LEFT:s\[[0-9]+:[0-9]+\]]]<br class="">-; GCN: s_andn2_b64 exec, exec, [[LEFT]]<br class="">-; GCN-NEXT: s_cbranch_execz<br class="">-<br class=""> ; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; %bb1{{$}}<br class="">-; GCN: s_mov_b64 [[OLD_LEFT]], [[LEFT]]<br class="">+; GCN: s_mov_b64 [[OLD_LEFT:s\[[0-9]+:[0-9]+\]]], [[LEFT]]<br class=""><br class=""> ; GCN: ; %LeafBlock1<br class=""> ; GCN: s_mov_b64<br class="">-; GCN: s_mov_b64 [[BREAK]], -1{{$}}<br class="">+; GCN: s_mov_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], -1{{$}}<br class=""><br class=""> ; GCN: ; %case1<br class=""> ; GCN: buffer_load_dword [[LOAD2:v[0-9]+]],<br class="">@@ -124,6 +118,12 @@ ENDIF:<br class=""> ; GCN-DAG: s_and_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], vcc, exec<br class=""> ; GCN: s_or_b64 [[BREAK]], [[BREAK]], [[TMP]]<br class=""><br class="">+; GCN: ; %Flow4<br class="">+; GCN: s_and_b64 [[BREAK]], exec, [[BREAK]]<br class="">+; GCN: s_or_b64 [[LEFT]], [[BREAK]], [[OLD_LEFT]]<br class="">+; GCN: s_andn2_b64 exec, exec, [[LEFT]]<br class="">+; GCN-NEXT: s_cbranch_execnz<br class="">+<br class=""> define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {<br class=""> bb:<br class=""> %id = call i32 @llvm.amdgcn.workitem.id.x()<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/optimize-negated-cond.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/optimize-negated-cond.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/optimize-negated-cond.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/optimize-negated-cond.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/optimize-negated-cond.ll Thu Aug 22 09:21:32 2019<br class="">@@ -3,11 +3,11 @@<br class=""> ; GCN-LABEL: {{^}}negated_cond:<br class=""> ; GCN: BB0_1:<br class=""> ; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]],<br class="">-; GCN: BB0_3:<br class="">+; GCN: BB0_2:<br class=""> ; GCN-NOT: v_cndmask_b32<br class=""> ; GCN-NOT: v_cmp<br class=""> ; GCN: s_andn2_b64 vcc, exec, [[CC]]<br class="">-; GCN: s_cbranch_vccnz BB0_2<br class="">+; GCN: s_cbranch_vccnz BB0_4<br class=""> define amdgpu_kernel void @negated_cond(i32 addrspace(1)* %arg1) {<br class=""> bb:<br class=""> br label %bb1<br class="">@@ -36,11 +36,11 @@ bb4:<br class=""><br class=""> ; GCN-LABEL: {{^}}negated_cond_dominated_blocks:<br class=""> ; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]],<br class="">-; GCN: %bb4<br class="">+; GCN: BB1_1:<br class=""> ; GCN-NOT: v_cndmask_b32<br class=""> ; GCN-NOT: v_cmp<br class=""> ; GCN: s_andn2_b64 vcc, exec, [[CC]]<br class="">-; GCN: s_cbranch_vccnz BB1_1<br class="">+; GCN: s_cbranch_vccz BB1_3<br class=""> define amdgpu_kernel void @negated_cond_dominated_blocks(i32 addrspace(1)* %arg1) {<br class=""> bb:<br class=""> br label %bb2<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/si-annotate-cf.ll Thu Aug 22 09:21:32 2019<br class="">@@ -96,20 +96,20 @@ declare float @llvm.fabs.f32(float) noun<br class=""> ; FUNC-LABEL: {{^}}loop_land_info_assert:<br class=""> ; SI: v_cmp_lt_i32_e64 [[CMP4:s\[[0-9:]+\]]], s{{[0-9]+}}, 4{{$}}<br class=""> ; SI: s_and_b64 [[CMP4M:s\[[0-9]+:[0-9]+\]]], exec, [[CMP4]]<br class="">-<br class="">-; SI: [[WHILELOOP:BB[0-9]+_[0-9]+]]: ; %while.cond<br class="">-; SI: s_cbranch_vccz [[FOR_COND_PH:BB[0-9]+_[0-9]+]]<br class="">+; SI: s_branch [[INFLOOP:BB[0-9]+_[0-9]+]]<br class=""><br class=""> ; SI: [[CONVEX_EXIT:BB[0-9_]+]]<br class=""> ; SI: s_mov_b64 vcc,<br class=""> ; SI-NEXT: s_cbranch_vccnz [[ENDPGM:BB[0-9]+_[0-9]+]]<br class="">-<br class="">-; SI: s_cbranch_vccnz [[WHILELOOP]]<br class="">+; SI: s_cbranch_vccnz [[INFLOOP]]<br class=""><br class=""> ; SI: ; %if.else<br class=""> ; SI: buffer_store_dword<br class=""><br class="">-; SI: [[FOR_COND_PH]]: ; %for.cond.preheader<br class="">+; SI: [[INFLOOP]]:<br class="">+; SI: s_cbranch_vccnz [[CONVEX_EXIT]]<br class="">+<br class="">+; SI: ; %for.cond.preheader<br class=""> ; SI: s_cbranch_vccz [[ENDPGM]]<br class=""><br class=""> ; SI: [[ENDPGM]]:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/wave32.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wave32.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wave32.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/wave32.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/wave32.ll Thu Aug 22 09:21:32 2019<br class="">@@ -166,29 +166,30 @@ endif:<br class=""> }<br class=""><br class=""> ; GCN-LABEL: {{^}}test_loop_with_if:<br class="">-; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}}<br class="">-; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}}<br class="">-; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}]<br class="">-; GFX1064: s_andn2_b64 exec, exec, s[{{[0-9:]+}}]<br class="">-; GCN: s_cbranch_execz<br class="">-; GCN: BB{{.*}}:<br class="">+; GCN: BB{{.*}}: ; %bb2<br class=""> ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo<br class=""> ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}<br class=""> ; GCN: s_cbranch_execz<br class="">-; GCN: BB{{.*}}:<br class="">-; GCN: BB{{.*}}:<br class="">+; GCN: BB{{.*}}: ; %bb5<br class="">+; GCN: BB{{.*}}: ; %Flow<br class=""> ; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}}<br class=""> ; GFX1064: s_xor_b64 s[{{[0-9:]+}}], exec, s[{{[0-9:]+}}]<br class=""> ; GCN: ; mask branch BB<br class="">-; GCN: BB{{.*}}:<br class="">-; GCN: BB{{.*}}:<br class="">+; GCN: BB{{.*}}: ; %bb11<br class="">+; GCN: BB{{.*}}: ; %Flow1<br class=""> ; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}}<br class=""> ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}}<br class=""> ; GFX1064: s_or_b64 exec, exec, s[{{[0-9:]+}}]<br class=""> ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}<br class=""> ; GCN: ; mask branch BB<br class="">-; GCN: BB{{.*}}:<br class="">-; GCN: BB{{.*}}:<br class="">+; GCN: BB{{.*}}: ; %bb10<br class="">+; GCN: BB{{.*}}: ; %bb13<br class="">+; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}}<br class="">+; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}}<br class="">+; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}]<br class="">+; GFX1064: s_andn2_b64 exec, exec, s[{{[0-9:]+}}]<br class="">+; GCN: s_cbranch_execnz<br class="">+; GCN: ; %bb1<br class=""> ; GCN: s_endpgm<br class=""> define amdgpu_kernel void @test_loop_with_if(i32 addrspace(1)* %arg) #0 {<br class=""> bb:<br class="">@@ -230,16 +231,17 @@ bb13:<br class=""> ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}<br class=""> ; GCN: ; mask branch<br class=""> ; GCN: s_cbranch_execz<br class="">-; GCN: BB{{.*}}:<br class="">-; GCN: BB{{.*}}:<br class="">+; GCN: BB{{.*}}: ; %.preheader<br class="">+; GCN: ; %bb8<br class=""> ; GFX1032: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, exec_lo<br class=""> ; GFX1064: s_andn2_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], exec<br class=""> ; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}}<br class=""> ; GFX1032: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}<br class=""> ; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}]<br class=""> ; GFX1064: s_or_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}]<br class="">-; GCN: s_cbranch_execz<br class="">-; GCN: BB{{.*}}:<br class="">+; GCN: BB{{.*}}: ; %Flow<br class="">+; GCN: s_cbranch_execnz<br class="">+; GCN: BB{{.*}}: ; %.loopexit<br class=""> define amdgpu_kernel void @test_loop_with_if_else_break(i32 addrspace(1)* %arg) #0 {<br class=""> bb:<br class=""> %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()<br class="">@@ -655,7 +657,7 @@ define amdgpu_gs void @test_kill_i1_term<br class=""> ; GCN-LABEL: {{^}}test_loop_vcc:<br class=""> ; GFX1032: v_cmp_lt_f32_e32 vcc_lo,<br class=""> ; GFX1064: v_cmp_lt_f32_e32 vcc,<br class="">-; GCN: s_cbranch_vccnz<br class="">+; GCN: s_cbranch_vccz<br class=""> define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) #0 {<br class=""> entry:<br class=""> br label %loop<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/wqm.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wqm.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wqm.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/wqm.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/wqm.ll Thu Aug 22 09:21:32 2019<br class="">@@ -650,15 +650,12 @@ main_body:<br class=""> ; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0<br class=""> ; CHECK-DAG: s_mov_b32 [[SEVEN:s[0-9]+]], 0x40e00000<br class=""><br class="">-; CHECK: [[LOOPHDR:BB[0-9]+_[0-9]+]]: ; %loop<br class="">-; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]]<br class="">-; CHECK: s_cbranch_vccnz<br class="">-<br class="">-; CHECK: ; %body<br class="">+; CHECK: [[LOOPHDR:BB[0-9]+_[0-9]+]]: ; %body<br class=""> ; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]]<br class="">-; CHECK: s_branch [[LOOPHDR]]<br class="">-<br class="">+; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]]<br class="">+; CHECK: s_cbranch_vccz [[LOOPHDR]]<br class=""> ; CHECK: ; %break<br class="">+<br class=""> ; CHECK: ; return<br class=""> define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind {<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll Thu Aug 22 09:21:32 2019<br class="">@@ -26,7 +26,7 @@ bb1:<br class=""><br class=""> bb2: ; preds = %bb1, %entry<br class=""> ; CHECK: cmp [[REG]], #0<br class="">-; CHECK: bgt<br class="">+; CHECK: ble<br class=""> %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]<br class=""> %tries.0 = sub i32 2147483647, %indvar<br class=""> %tmp1 = icmp sgt i32 %tries.0, 0<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Thu Aug 22 09:21:32 2019<br class="">@@ -47,8 +47,9 @@ tailrecurse.switch:<br class=""> ; V8-NEXT: beq<br class=""> ; V8-NEXT: %tailrecurse.switch<br class=""> ; V8: cmp<br class="">-; V8-NEXT: bne<br class="">-; V8-NEXT: %sw.bb<br class="">+; V8-NEXT: beq<br class="">+; V8-NEXT: %sw.epilog<br class="">+; V8-NEXT: bx lr<br class=""> switch i32 %and, label %sw.epilog [<br class=""> i32 1, label %sw.bb<br class=""> i32 3, label %sw.bb6<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll Thu Aug 22 09:21:32 2019<br class="">@@ -9,8 +9,8 @@ define i8 @t(i8* %a, i8 %b, i8 %c) nounw<br class=""> ; ARM: clrex<br class=""><br class=""> ; T2-LABEL: t:<br class="">-; T2: ldrexb<br class=""> ; T2: strexb<br class="">+; T2: ldrexb<br class=""> ; T2: clrex<br class=""> %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic monotonic<br class=""> %tmp1 = extractvalue { i8, i1 } %tmp0, 0<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll Thu Aug 22 09:21:32 2019<br class="">@@ -52,16 +52,16 @@ entry:<br class=""> ; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8:<br class=""> ; CHECK-ARMV7-NEXT: .fnstart<br class=""> ; CHECK-ARMV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1<br class="">-; CHECK-ARMV7-NEXT: [[TRY:.LBB[0-9_]+]]:<br class="">-; CHECK-ARMV7-NEXT: ldrexb [[SUCCESS:r[0-9]+]], [r0]<br class="">-; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], r1<br class="">-; CHECK-ARMV7-NEXT: bne [[EXIT:.LBB[0-9_]+]]<br class="">-; CHECK-ARMV7-NEXT: strexb [[SUCCESS]], r2, [r0]<br class="">+; CHECK-ARMV7-NEXT: b [[TRY:.LBB[0-9_]+]]<br class="">+; CHECK-ARMV7-NEXT: [[HEAD:.LBB[0-9_]+]]:<br class="">+; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]<br class=""> ; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], #0<br class=""> ; CHECK-ARMV7-NEXT: moveq r0, #1<br class=""> ; CHECK-ARMV7-NEXT: bxeq lr<br class="">-; CHECK-ARMV7-NEXT: b [[TRY]]<br class="">-; CHECK-ARMV7-NEXT: [[EXIT]]:<br class="">+; CHECK-ARMV7-NEXT: [[TRY]]:<br class="">+; CHECK-ARMV7-NEXT: ldrexb [[SUCCESS]], [r0]<br class="">+; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], r1<br class="">+; CHECK-ARMV7-NEXT: beq [[HEAD]]<br class=""> ; CHECK-ARMV7-NEXT: mov r0, #0<br class=""> ; CHECK-ARMV7-NEXT: clrex<br class=""> ; CHECK-ARMV7-NEXT: bx lr<br class="">@@ -69,17 +69,17 @@ entry:<br class=""> ; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8:<br class=""> ; CHECK-THUMBV7-NEXT: .fnstart<br class=""> ; CHECK-THUMBV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1<br class="">-; CHECK-THUMBV7-NEXT: [[TRYLD:.LBB[0-9_]+]]<br class="">-; CHECK-THUMBV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0]<br class="">-; CHECK-THUMBV7-NEXT: cmp [[LD]], [[DESIRED]]<br class="">-; CHECK-THUMBV7-NEXT: bne [[EXIT:.LBB[0-9_]+]]<br class="">+; CHECK-THUMBV7-NEXT: b [[TRYLD:.LBB[0-9_]+]]<br class="">+; CHECK-THUMBV7-NEXT: [[TRYST:.LBB[0-9_]+]]:<br class=""> ; CHECK-THUMBV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]<br class=""> ; CHECK-THUMBV7-NEXT: cmp [[SUCCESS]], #0<br class=""> ; CHECK-THUMBV7-NEXT: itt eq<br class=""> ; CHECK-THUMBV7-NEXT: moveq r0, #1<br class=""> ; CHECK-THUMBV7-NEXT: bxeq lr<br class="">-; CHECK-THUMBV7-NEXT: b [[TRYLD]]<br class="">-; CHECK-THUMBV7-NEXT: [[EXIT]]:<br class="">+; CHECK-THUMBV7-NEXT: [[TRYLD]]:<br class="">+; CHECK-THUMBV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0]<br class="">+; CHECK-THUMBV7-NEXT: cmp [[LD]], [[DESIRED]]<br class="">+; CHECK-THUMBV7-NEXT: beq [[TRYST:.LBB[0-9_]+]]<br class=""> ; CHECK-THUMBV7-NEXT: movs r0, #0<br class=""> ; CHECK-THUMBV7-NEXT: clrex<br class=""> ; CHECK-THUMBV7-NEXT: bx lr<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/ARM/code-placement.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/code-placement.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/code-placement.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/ARM/code-placement.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/ARM/code-placement.ll Thu Aug 22 09:21:32 2019<br class="">@@ -38,9 +38,8 @@ entry:<br class=""> br i1 %0, label %bb5, label %bb.nph15<br class=""><br class=""> bb1: ; preds = %bb2.preheader, %bb1<br class="">-; CHECK: LBB1_[[BB3:.]]: @ %bb3<br class=""> ; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader<br class="">-; CHECK: bmi LBB1_[[BB3]]<br class="">+; CHECK: bmi LBB1_[[BB3:.]]<br class=""> %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]<br class=""> %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]<br class=""> %tmp17 = sub i32 %i.07, %indvar ; <i32> [#uses=1]<br class="">@@ -54,6 +53,7 @@ bb1:<br class=""> bb3: ; preds = %bb1, %bb2.preheader<br class=""> ; CHECK: LBB1_[[BB1:.]]: @ %bb1<br class=""> ; CHECK: bne LBB1_[[BB1]]<br class="">+; CHECK: LBB1_[[BB3]]: @ %bb3<br class=""> %sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; <i32> [#uses=2]<br class=""> %3 = add i32 %pass.011, 1 ; <i32> [#uses=2]<br class=""> %exitcond18 = icmp eq i32 %3, %passes ; <i1> [#uses=1]<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/ARM/pr32578.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr32578.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr32578.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/ARM/pr32578.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/ARM/pr32578.ll Thu Aug 22 09:21:32 2019<br class="">@@ -4,7 +4,7 @@ target triple = "armv7"<br class=""> ; CHECK-LABEL: func:<br class=""> ; CHECK: push {r11, lr}<br class=""> ; CHECK: vpush {d8}<br class="">-; CHECK: .LBB0_1: @ %tailrecurse<br class="">+; CHECK: b .LBB0_2<br class=""> define arm_aapcscc double @func() {<br class=""> br label %tailrecurse<br class=""><br class=""><br class="">Modified: llvm/trunk/test/CodeGen/Hexagon/bug6757-endloop.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bug6757-endloop.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bug6757-endloop.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/Hexagon/bug6757-endloop.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/Hexagon/bug6757-endloop.ll Thu Aug 22 09:21:32 2019<br class="">@@ -4,10 +4,10 @@<br class=""> ; This situation can arise due to tail duplication.<br class=""><br class=""> ; CHECK: loop1([[LP:.LBB0_[0-9]+]]<br class="">-; CHECK: endloop1<br class=""> ; CHECK: [[LP]]:<br class=""> ; CHECK-NOT: loop1(<br class=""> ; CHECK: endloop1<br class="">+; CHECK: endloop1<br class=""><br class=""> %s.0 = type { i32, i8* }<br class=""> %s.1 = type { i32, i32, i32, i32 }<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/Hexagon/early-if-merge-loop.ll Thu Aug 22 09:21:32 2019<br class="">@@ -2,11 +2,9 @@<br class=""> ; Make sure that the loop in the end has only one basic block.<br class=""><br class=""> ; CHECK-LABEL: fred<br class="">-; CHECK: %b2<br class=""> ; Rely on the comments, make sure the one for the loop header is present.<br class=""> ; CHECK: %loop<br class="">-; CHECK: %should_merge<br class="">-; CHECK: %exit<br class="">+; CHECK-NOT: %should_merge<br class=""><br class=""> target triple = "hexagon"<br class=""><br class=""><br class="">Modified: llvm/trunk/test/CodeGen/Hexagon/prof-early-if.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/prof-early-if.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/prof-early-if.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/Hexagon/prof-early-if.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/Hexagon/prof-early-if.ll Thu Aug 22 09:21:32 2019<br class="">@@ -1,8 +1,8 @@<br class=""> ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s<br class=""> ; Rely on the comments generated by llc. Check that "if.then" was not predicated.<br class="">-; CHECK: b5<br class=""> ; CHECK: b2<br class=""> ; CHECK-NOT: if{{.*}}memd<br class="">+; CHECK: b5<br class=""><br class=""> %s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] }<br class=""> %s.1 = type { i32, i32 }<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/Hexagon/redundant-branching2.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/redundant-branching2.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/redundant-branching2.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/Hexagon/redundant-branching2.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/Hexagon/redundant-branching2.ll Thu Aug 22 09:21:32 2019<br class="">@@ -3,9 +3,9 @@<br class=""><br class=""> ; CHECK: memub<br class=""> ; CHECK: memub<br class="">-; CHECK: cmp.eq<br class=""> ; CHECK: memub<br class=""> ; CHECK-NOT: if{{.*}}jump .LBB<br class="">+; CHECK: cmp.eq<br class=""><br class=""> target triple = "hexagon-unknown--elf"<br class=""><br class=""><br class="">Modified: llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll Thu Aug 22 09:21:32 2019<br class="">@@ -401,15 +401,16 @@ define void @test40(i8* %ptr, i8 %cmp, i<br class=""> ; PPC64LE-LABEL: test40:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31<br class="">+; PPC64LE-NEXT: b .LBB40_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB40_1:<br class="">-; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB40_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stbcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB40_1<br class="">-; PPC64LE-NEXT: .LBB40_3:<br class="">+; PPC64LE-NEXT: .LBB40_2:<br class="">+; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB40_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stbcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic<br class="">@@ -465,15 +466,16 @@ define void @test43(i8* %ptr, i8 %cmp, i<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB43_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB43_1:<br class="">-; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB43_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stbcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB43_1<br class="">-; PPC64LE-NEXT: .LBB43_3:<br class="">+; PPC64LE-NEXT: .LBB43_2:<br class="">+; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB43_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stbcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic<br class="">@@ -485,15 +487,16 @@ define void @test44(i8* %ptr, i8 %cmp, i<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB44_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB44_1:<br class="">-; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB44_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stbcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB44_1<br class="">-; PPC64LE-NEXT: .LBB44_3:<br class="">+; PPC64LE-NEXT: .LBB44_2:<br class="">+; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB44_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stbcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire<br class="">@@ -619,15 +622,16 @@ define void @test50(i16* %ptr, i16 %cmp,<br class=""> ; PPC64LE-LABEL: test50:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31<br class="">+; PPC64LE-NEXT: b .LBB50_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB50_1:<br class="">-; PPC64LE-NEXT: lharx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB50_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: sthcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB50_1<br class="">-; PPC64LE-NEXT: .LBB50_3:<br class="">+; PPC64LE-NEXT: .LBB50_2:<br class="">+; PPC64LE-NEXT: lharx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB50_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: sthcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic<br class="">@@ -683,15 +687,16 @@ define void @test53(i16* %ptr, i16 %cmp,<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB53_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB53_1:<br class="">-; PPC64LE-NEXT: lharx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB53_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: sthcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB53_1<br class="">-; PPC64LE-NEXT: .LBB53_3:<br class="">+; PPC64LE-NEXT: .LBB53_2:<br class="">+; PPC64LE-NEXT: lharx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB53_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: sthcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic<br class="">@@ -703,15 +708,16 @@ define void @test54(i16* %ptr, i16 %cmp,<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB54_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB54_1:<br class="">-; PPC64LE-NEXT: lharx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB54_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: sthcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB54_1<br class="">-; PPC64LE-NEXT: .LBB54_3:<br class="">+; PPC64LE-NEXT: .LBB54_2:<br class="">+; PPC64LE-NEXT: lharx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB54_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: sthcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire<br class="">@@ -836,15 +842,16 @@ define void @test59(i16* %ptr, i16 %cmp,<br class=""> define void @test60(i32* %ptr, i32 %cmp, i32 %val) {<br class=""> ; PPC64LE-LABEL: test60:<br class=""> ; PPC64LE: # %bb.0:<br class="">+; PPC64LE-NEXT: b .LBB60_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB60_1:<br class="">-; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB60_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stwcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB60_1<br class="">-; PPC64LE-NEXT: .LBB60_3:<br class="">+; PPC64LE-NEXT: .LBB60_2:<br class="">+; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB60_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stwcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic<br class="">@@ -897,15 +904,16 @@ define void @test63(i32* %ptr, i32 %cmp,<br class=""> ; PPC64LE-LABEL: test63:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB63_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB63_1:<br class="">-; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB63_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stwcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB63_1<br class="">-; PPC64LE-NEXT: .LBB63_3:<br class="">+; PPC64LE-NEXT: .LBB63_2:<br class="">+; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB63_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stwcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic<br class="">@@ -916,15 +924,16 @@ define void @test64(i32* %ptr, i32 %cmp,<br class=""> ; PPC64LE-LABEL: test64:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB64_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB64_1:<br class="">-; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB64_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stwcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB64_1<br class="">-; PPC64LE-NEXT: .LBB64_3:<br class="">+; PPC64LE-NEXT: .LBB64_2:<br class="">+; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB64_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stwcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire<br class="">@@ -1044,15 +1053,16 @@ define void @test69(i32* %ptr, i32 %cmp,<br class=""> define void @test70(i64* %ptr, i64 %cmp, i64 %val) {<br class=""> ; PPC64LE-LABEL: test70:<br class=""> ; PPC64LE: # %bb.0:<br class="">+; PPC64LE-NEXT: b .LBB70_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB70_1:<br class="">-; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpd 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB70_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stdcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB70_1<br class="">-; PPC64LE-NEXT: .LBB70_3:<br class="">+; PPC64LE-NEXT: .LBB70_2:<br class="">+; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpd 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB70_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stdcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic<br class="">@@ -1105,15 +1115,16 @@ define void @test73(i64* %ptr, i64 %cmp,<br class=""> ; PPC64LE-LABEL: test73:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB73_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB73_1:<br class="">-; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpd 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB73_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stdcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB73_1<br class="">-; PPC64LE-NEXT: .LBB73_3:<br class="">+; PPC64LE-NEXT: .LBB73_2:<br class="">+; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpd 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB73_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stdcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic<br class="">@@ -1124,15 +1135,16 @@ define void @test74(i64* %ptr, i64 %cmp,<br class=""> ; PPC64LE-LABEL: test74:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB74_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB74_1:<br class="">-; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpd 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB74_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stdcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB74_1<br class="">-; PPC64LE-NEXT: .LBB74_3:<br class="">+; PPC64LE-NEXT: .LBB74_2:<br class="">+; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpd 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB74_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stdcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire<br class="">@@ -1253,15 +1265,16 @@ define void @test80(i8* %ptr, i8 %cmp, i<br class=""> ; PPC64LE-LABEL: test80:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31<br class="">+; PPC64LE-NEXT: b .LBB80_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB80_1:<br class="">-; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB80_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stbcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB80_1<br class="">-; PPC64LE-NEXT: .LBB80_3:<br class="">+; PPC64LE-NEXT: .LBB80_2:<br class="">+; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB80_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stbcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic<br class="">@@ -1317,15 +1330,16 @@ define void @test83(i8* %ptr, i8 %cmp, i<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB83_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB83_1:<br class="">-; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB83_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stbcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB83_1<br class="">-; PPC64LE-NEXT: .LBB83_3:<br class="">+; PPC64LE-NEXT: .LBB83_2:<br class="">+; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB83_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stbcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic<br class="">@@ -1337,15 +1351,16 @@ define void @test84(i8* %ptr, i8 %cmp, i<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB84_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB84_1:<br class="">-; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB84_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stbcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB84_1<br class="">-; PPC64LE-NEXT: .LBB84_3:<br class="">+; PPC64LE-NEXT: .LBB84_2:<br class="">+; PPC64LE-NEXT: lbarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB84_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stbcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire<br class="">@@ -1471,15 +1486,16 @@ define void @test90(i16* %ptr, i16 %cmp,<br class=""> ; PPC64LE-LABEL: test90:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31<br class="">+; PPC64LE-NEXT: b .LBB90_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB90_1:<br class="">-; PPC64LE-NEXT: lharx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB90_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: sthcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b <br class="">-; PPC64LE-NEXT: .LBB90_3:<br class="">+; PPC64LE-NEXT: .LBB90_2:<br class="">+; PPC64LE-NEXT: lharx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB90_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: sthcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic<br class="">@@ -1535,15 +1551,16 @@ define void @test93(i16* %ptr, i16 %cmp,<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB93_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB93_1:<br class="">-; PPC64LE-NEXT: lharx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB93_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: sthcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB93_1<br class="">-; PPC64LE-NEXT: .LBB93_3:<br class="">+; PPC64LE-NEXT: .LBB93_2:<br class="">+; PPC64LE-NEXT: lharx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB93_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: sthcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic<br class="">@@ -1555,15 +1572,16 @@ define void @test94(i16* %ptr, i16 %cmp,<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB94_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB94_1:<br class="">-; PPC64LE-NEXT: lharx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB94_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: sthcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB94_1<br class="">-; PPC64LE-NEXT: .LBB94_3:<br class="">+; PPC64LE-NEXT: .LBB94_2:<br class="">+; PPC64LE-NEXT: lharx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB94_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: sthcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire<br class="">@@ -1688,15 +1706,16 @@ define void @test99(i16* %ptr, i16 %cmp,<br class=""> define void @test100(i32* %ptr, i32 %cmp, i32 %val) {<br class=""> ; PPC64LE-LABEL: test100:<br class=""> ; PPC64LE: # %bb.0:<br class="">+; PPC64LE-NEXT: b .LBB100_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB100_1:<br class="">-; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB100_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stwcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB100_1<br class="">-; PPC64LE-NEXT: .LBB100_3:<br class="">+; PPC64LE-NEXT: .LBB100_2:<br class="">+; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB100_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stwcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic<br class="">@@ -1749,15 +1768,16 @@ define void @test103(i32* %ptr, i32 %cmp<br class=""> ; PPC64LE-LABEL: test103:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB103_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB103_1:<br class="">-; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB103_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stwcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB103_1<br class="">-; PPC64LE-NEXT: .LBB103_3:<br class="">+; PPC64LE-NEXT: .LBB103_2:<br class="">+; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB103_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stwcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic<br class="">@@ -1768,15 +1788,16 @@ define void @test104(i32* %ptr, i32 %cmp<br class=""> ; PPC64LE-LABEL: test104:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB104_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB104_1:<br class="">-; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpw 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB104_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stwcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB104_1<br class="">-; PPC64LE-NEXT: .LBB104_3:<br class="">+; PPC64LE-NEXT: .LBB104_2:<br class="">+; PPC64LE-NEXT: lwarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpw 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB104_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stwcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire<br class="">@@ -1896,15 +1917,16 @@ define void @test109(i32* %ptr, i32 %cmp<br class=""> define void @test110(i64* %ptr, i64 %cmp, i64 %val) {<br class=""> ; PPC64LE-LABEL: test110:<br class=""> ; PPC64LE: # %bb.0:<br class="">+; PPC64LE-NEXT: b .LBB110_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB110_1:<br class="">-; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpd 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB110_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stdcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB110_1<br class="">-; PPC64LE-NEXT: .LBB110_3:<br class="">+; PPC64LE-NEXT: .LBB110_2:<br class="">+; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpd 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB110_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stdcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic<br class="">@@ -1957,15 +1979,16 @@ define void @test113(i64* %ptr, i64 %cmp<br class=""> ; PPC64LE-LABEL: test113:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB113_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB113_1:<br class="">-; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpd 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB113_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stdcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB113_1<br class="">-; PPC64LE-NEXT: .LBB113_3:<br class="">+; PPC64LE-NEXT: .LBB113_2:<br class="">+; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpd 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB113_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stdcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic<br class="">@@ -1976,15 +1999,16 @@ define void @test114(i64* %ptr, i64 %cmp<br class=""> ; PPC64LE-LABEL: test114:<br class=""> ; PPC64LE: # %bb.0:<br class=""> ; PPC64LE-NEXT: lwsync<br class="">+; PPC64LE-NEXT: b .LBB114_2<br class="">+; PPC64LE-NEXT: .p2align 5<br class=""> ; PPC64LE-NEXT: .LBB114_1:<br class="">-; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">-; PPC64LE-NEXT: cmpd 4, 6<br class="">-; PPC64LE-NEXT: bne 0, .LBB114_3<br class="">-; PPC64LE-NEXT: # %bb.2:<br class=""> ; PPC64LE-NEXT: stdcx. 5, 0, 3<br class=""> ; PPC64LE-NEXT: beqlr 0<br class="">-; PPC64LE-NEXT: b .LBB114_1<br class="">-; PPC64LE-NEXT: .LBB114_3:<br class="">+; PPC64LE-NEXT: .LBB114_2:<br class="">+; PPC64LE-NEXT: ldarx 6, 0, 3<br class="">+; PPC64LE-NEXT: cmpd 4, 6<br class="">+; PPC64LE-NEXT: beq 0, .LBB114_1<br class="">+; PPC64LE-NEXT: # %bb.3:<br class=""> ; PPC64LE-NEXT: stdcx. 6, 0, 3<br class=""> ; PPC64LE-NEXT: blr<br class=""> %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/PowerPC/block-placement-1.mir<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/block-placement-1.mir?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/block-placement-1.mir?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/PowerPC/block-placement-1.mir (original)<br class="">+++ llvm/trunk/test/CodeGen/PowerPC/block-placement-1.mir Thu Aug 22 09:21:32 2019<br class="">@@ -298,14 +298,14 @@ body: |<br class=""><br class=""> bb.11.unreachable:<br class=""><br class="">- ; CHECK: bb.1.for.body:<br class="">- ; CHECK: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)<br class="">- ; CHECK: B %bb.2<br class="">-<br class=""> ; CHECK: bb.4.catch4:<br class=""> ; CHECK: successors: %bb.11(0x7ffff800), %bb.6(0x00000800)<br class=""> ; CHECK: B %bb.11<br class=""><br class="">+ ; CHECK: bb.1.for.body (align 4):<br class="">+ ; CHECK: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)<br class="">+ ; CHECK: B %bb.2<br class="">+<br class=""> ; CHECK: bb.2..noexc:<br class=""><br class=""> ; CHECK: bb.11.unreachable: <br class=""><br class="">Modified: llvm/trunk/test/CodeGen/PowerPC/cmp_elimination.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cmp_elimination.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cmp_elimination.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/PowerPC/cmp_elimination.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/PowerPC/cmp_elimination.ll Thu Aug 22 09:21:32 2019<br class="">@@ -718,14 +718,13 @@ if.end:<br class=""> define void @func28(i32 signext %a) {<br class=""> ; CHECK-LABEL: @func28<br class=""> ; CHECK: cmplwi<span class="Apple-tab-span" style="white-space:pre"> </span> [[REG1:[0-9]+]], [[REG2:[0-9]+]]<br class="">-; CHECK: .[[LABEL2:[A-Z0-9_]+]]:<br class="">-; CHECK: cmpwi [[REG1]], [[REG2]]<br class="">-; CHECK: ble 0, .[[LABEL1:[A-Z0-9_]+]]<br class="">+; CHECK: .[[LABEL1:[A-Z0-9_]+]]:<br class=""> ; CHECK-NOT: cmp<br class="">-; CHECK: bne 0, .[[LABEL2]]<br class="">+; CHECK: bne<span class="Apple-tab-span" style="white-space:pre"> </span> 0, .[[LABEL2:[A-Z0-9_]+]]<br class=""> ; CHECK: bl dummy1<br class="">-; CHECK: b .[[LABEL2]]<br class="">-; CHECK: .[[LABEL1]]:<br class="">+; CHECK: .[[LABEL2]]:<br class="">+; CHECK: cmpwi<span class="Apple-tab-span" style="white-space:pre"> </span> [[REG1]], [[REG2]]<br class="">+; CHECK: bgt<span class="Apple-tab-span" style="white-space:pre"> </span> 0, .[[LABEL1]]<br class=""> ; CHECK: blr<br class=""> entry:<br class=""> br label %do.body<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll Thu Aug 22 09:21:32 2019<br class="">@@ -24,7 +24,8 @@ define linkonce_odr void @ZN6snappyDecom<br class=""> ; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l<br class=""> ; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha<br class=""> ; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l<br class="">-; CHECK: .LBB0_2: # %for.cond<br class="">+; CHECK: b .[[LABEL1:[A-Z0-9_]+]]<br class="">+; CHECK: .[[LABEL1]]: # %for.cond<br class=""> ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha<br class=""> ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL10char_tableE@toc@ha<br class=""> ; CHECK: bctrl<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/PowerPC/machine-pre.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/machine-pre.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/machine-pre.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/PowerPC/machine-pre.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/PowerPC/machine-pre.ll Thu Aug 22 09:21:32 2019<br class="">@@ -75,19 +75,8 @@ define dso_local signext i32 @foo(i32 si<br class=""> ; CHECK-P9-NEXT: lis r3, 21845<br class=""> ; CHECK-P9-NEXT: add r28, r30, r29<br class=""> ; CHECK-P9-NEXT: ori r27, r3, 21846<br class="">-; CHECK-P9-NEXT: b .LBB1_4<br class=""> ; CHECK-P9-NEXT: .p2align 4<br class="">-; CHECK-P9-NEXT: .LBB1_1: # %sw.bb3<br class="">-; CHECK-P9-NEXT: #<br class="">-; CHECK-P9-NEXT: mulli r3, r30, 23<br class="">-; CHECK-P9-NEXT: .LBB1_2: # %sw.epilog<br class="">-; CHECK-P9-NEXT: #<br class="">-; CHECK-P9-NEXT: add r28, r3, r28<br class="">-; CHECK-P9-NEXT: .LBB1_3: # %sw.epilog<br class="">-; CHECK-P9-NEXT: #<br class="">-; CHECK-P9-NEXT: cmpwi r28, 1025<br class="">-; CHECK-P9-NEXT: bge cr0, .LBB1_7<br class="">-; CHECK-P9-NEXT: .LBB1_4: # %while.cond<br class="">+; CHECK-P9-NEXT: .LBB1_1: # %while.cond<br class=""> ; CHECK-P9-NEXT: #<br class=""> ; CHECK-P9-NEXT: extsw r3, r29<br class=""> ; CHECK-P9-NEXT: bl bar<br class="">@@ -106,16 +95,27 @@ define dso_local signext i32 @foo(i32 si<br class=""> ; CHECK-P9-NEXT: add r4, r4, r5<br class=""> ; CHECK-P9-NEXT: subf r3, r4, r3<br class=""> ; CHECK-P9-NEXT: cmplwi r3, 1<br class="">-; CHECK-P9-NEXT: beq cr0, .LBB1_1<br class="">-; CHECK-P9-NEXT: # %bb.5: # %while.cond<br class="">+; CHECK-P9-NEXT: beq cr0, .LBB1_4<br class="">+; CHECK-P9-NEXT: # %bb.2: # %while.cond<br class=""> ; CHECK-P9-NEXT: #<br class=""> ; CHECK-P9-NEXT: cmplwi r3, 0<br class="">-; CHECK-P9-NEXT: bne cr0, .LBB1_3<br class="">-; CHECK-P9-NEXT: # %bb.6: # %sw.bb<br class="">+; CHECK-P9-NEXT: bne cr0, .LBB1_6<br class="">+; CHECK-P9-NEXT: # %bb.3: # %sw.bb<br class=""> ; CHECK-P9-NEXT: #<br class=""> ; CHECK-P9-NEXT: mulli r3, r29, 13<br class="">-; CHECK-P9-NEXT: b .LBB1_2<br class="">-; CHECK-P9-NEXT: .LBB1_7: # %while.end<br class="">+; CHECK-P9-NEXT: b .LBB1_5<br class="">+; CHECK-P9-NEXT: .p2align 4<br class="">+; CHECK-P9-NEXT: .LBB1_4: # %sw.bb3<br class="">+; CHECK-P9-NEXT: # <br class="">+; CHECK-P9-NEXT: mulli r3, r30, 23<br class="">+; CHECK-P9-NEXT: .LBB1_5: # %sw.epilog<br class="">+; CHECK-P9-NEXT: # <br class="">+; CHECK-P9-NEXT: add r28, r3, r28 <br class="">+; CHECK-P9-NEXT: .LBB1_6: # %sw.epilog<br class="">+; CHECK-P9-NEXT: # <br class="">+; CHECK-P9-NEXT: cmpwi r28, 1025<br class="">+; CHECK-P9-NEXT: blt cr0, .LBB1_1<br class="">+; CHECK-P9-NEXT: # %bb.7: # %while.end<br class=""> ; CHECK-P9-NEXT: lis r3, -13108<br class=""> ; CHECK-P9-NEXT: ori r3, r3, 52429<br class=""> ; CHECK-P9-NEXT: mullw r3, r28, r3<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/RISCV/atomic-rmw.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/atomic-rmw.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/atomic-rmw.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/RISCV/atomic-rmw.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/RISCV/atomic-rmw.ll Thu Aug 22 09:21:32 2019<br class="">@@ -2083,9 +2083,17 @@ define i8 @atomicrmw_max_i8_monotonic(i8<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB35_2<br class=""> ; RV32I-NEXT: .LBB35_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB35_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB35_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB35_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB35_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -2094,18 +2102,8 @@ define i8 @atomicrmw_max_i8_monotonic(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB35_4<br class="">-; RV32I-NEXT: .LBB35_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB35_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB35_1<br class="">-; RV32I-NEXT: .LBB35_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB35_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -2158,9 +2156,17 @@ define i8 @atomicrmw_max_i8_monotonic(i8<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB35_2<br class=""> ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB35_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB35_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB35_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB35_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -2169,18 +2175,8 @@ define i8 @atomicrmw_max_i8_monotonic(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB35_4<br class="">-; RV64I-NEXT: .LBB35_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB35_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB35_1<br class="">-; RV64I-NEXT: .LBB35_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB35_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -2237,9 +2233,17 @@ define i8 @atomicrmw_max_i8_acquire(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB36_2<br class=""> ; RV32I-NEXT: .LBB36_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB36_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB36_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB36_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB36_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -2248,18 +2252,8 @@ define i8 @atomicrmw_max_i8_acquire(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB36_4<br class="">-; RV32I-NEXT: .LBB36_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB36_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB36_1<br class="">-; RV32I-NEXT: .LBB36_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB36_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -2312,9 +2306,17 @@ define i8 @atomicrmw_max_i8_acquire(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB36_2<br class=""> ; RV64I-NEXT: .LBB36_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB36_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB36_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB36_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB36_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -2323,18 +2325,8 @@ define i8 @atomicrmw_max_i8_acquire(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB36_4<br class="">-; RV64I-NEXT: .LBB36_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB36_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB36_1<br class="">-; RV64I-NEXT: .LBB36_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB36_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -2391,9 +2383,17 @@ define i8 @atomicrmw_max_i8_release(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB37_2<br class=""> ; RV32I-NEXT: .LBB37_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB37_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB37_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB37_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB37_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -2402,18 +2402,8 @@ define i8 @atomicrmw_max_i8_release(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB37_4<br class="">-; RV32I-NEXT: .LBB37_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB37_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB37_1<br class="">-; RV32I-NEXT: .LBB37_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB37_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -2466,9 +2456,17 @@ define i8 @atomicrmw_max_i8_release(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB37_2<br class=""> ; RV64I-NEXT: .LBB37_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB37_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB37_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB37_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB37_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -2477,18 +2475,8 @@ define i8 @atomicrmw_max_i8_release(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB37_4<br class="">-; RV64I-NEXT: .LBB37_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB37_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB37_1<br class="">-; RV64I-NEXT: .LBB37_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB37_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -2545,9 +2533,17 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB38_2<br class=""> ; RV32I-NEXT: .LBB38_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB38_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB38_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB38_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB38_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -2556,18 +2552,8 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB38_4<br class="">-; RV32I-NEXT: .LBB38_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB38_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB38_1<br class="">-; RV32I-NEXT: .LBB38_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB38_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -2620,9 +2606,17 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB38_2<br class=""> ; RV64I-NEXT: .LBB38_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB38_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB38_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB38_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB38_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -2631,18 +2625,8 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB38_4<br class="">-; RV64I-NEXT: .LBB38_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB38_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB38_1<br class="">-; RV64I-NEXT: .LBB38_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB38_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -2699,9 +2683,17 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB39_2<br class=""> ; RV32I-NEXT: .LBB39_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB39_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB39_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB39_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB39_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -2710,18 +2702,8 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB39_4<br class="">-; RV32I-NEXT: .LBB39_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB39_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB39_1<br class="">-; RV32I-NEXT: .LBB39_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB39_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -2774,9 +2756,17 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB39_2<br class=""> ; RV64I-NEXT: .LBB39_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB39_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB39_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB39_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB39_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -2785,18 +2775,8 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB39_4<br class="">-; RV64I-NEXT: .LBB39_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB39_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB39_1<br class="">-; RV64I-NEXT: .LBB39_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB39_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -2853,9 +2833,17 @@ define i8 @atomicrmw_min_i8_monotonic(i8<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB40_2<br class=""> ; RV32I-NEXT: .LBB40_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB40_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB40_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB40_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB40_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -2864,18 +2852,8 @@ define i8 @atomicrmw_min_i8_monotonic(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB40_4<br class="">-; RV32I-NEXT: .LBB40_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB40_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB40_1<br class="">-; RV32I-NEXT: .LBB40_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB40_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -2928,9 +2906,17 @@ define i8 @atomicrmw_min_i8_monotonic(i8<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB40_2<br class=""> ; RV64I-NEXT: .LBB40_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB40_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB40_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB40_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB40_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -2939,18 +2925,8 @@ define i8 @atomicrmw_min_i8_monotonic(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB40_4<br class="">-; RV64I-NEXT: .LBB40_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB40_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB40_1<br class="">-; RV64I-NEXT: .LBB40_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB40_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3007,9 +2983,17 @@ define i8 @atomicrmw_min_i8_acquire(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB41_2<br class=""> ; RV32I-NEXT: .LBB41_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB41_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB41_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB41_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB41_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3018,18 +3002,8 @@ define i8 @atomicrmw_min_i8_acquire(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB41_4<br class="">-; RV32I-NEXT: .LBB41_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB41_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB41_1<br class="">-; RV32I-NEXT: .LBB41_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB41_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3082,9 +3056,17 @@ define i8 @atomicrmw_min_i8_acquire(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB41_2<br class=""> ; RV64I-NEXT: .LBB41_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB41_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB41_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB41_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB41_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3093,18 +3075,8 @@ define i8 @atomicrmw_min_i8_acquire(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB41_4<br class="">-; RV64I-NEXT: .LBB41_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB41_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB41_1<br class="">-; RV64I-NEXT: .LBB41_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB41_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3161,9 +3133,17 @@ define i8 @atomicrmw_min_i8_release(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB42_2<br class=""> ; RV32I-NEXT: .LBB42_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB42_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB42_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB42_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB42_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3172,18 +3152,8 @@ define i8 @atomicrmw_min_i8_release(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB42_4<br class="">-; RV32I-NEXT: .LBB42_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB42_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB42_1<br class="">-; RV32I-NEXT: .LBB42_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB42_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3236,9 +3206,17 @@ define i8 @atomicrmw_min_i8_release(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB42_2<br class=""> ; RV64I-NEXT: .LBB42_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB42_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB42_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB42_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB42_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3247,18 +3225,8 @@ define i8 @atomicrmw_min_i8_release(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB42_4<br class="">-; RV64I-NEXT: .LBB42_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB42_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB42_1<br class="">-; RV64I-NEXT: .LBB42_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB42_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3315,9 +3283,17 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB43_2<br class=""> ; RV32I-NEXT: .LBB43_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB43_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB43_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB43_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB43_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3326,18 +3302,8 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB43_4<br class="">-; RV32I-NEXT: .LBB43_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB43_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB43_1<br class="">-; RV32I-NEXT: .LBB43_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB43_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3390,9 +3356,17 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB43_2<br class=""> ; RV64I-NEXT: .LBB43_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB43_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB43_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB43_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB43_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3401,18 +3375,8 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB43_4<br class="">-; RV64I-NEXT: .LBB43_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB43_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB43_1<br class="">-; RV64I-NEXT: .LBB43_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB43_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3469,9 +3433,17 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *<br class=""> ; RV32I-NEXT: slli a1, a1, 24<br class=""> ; RV32I-NEXT: srai s0, a1, 24<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB44_2<br class=""> ; RV32I-NEXT: .LBB44_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 24<br class="">+; RV32I-NEXT: srai a1, a1, 24<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB44_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB44_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB44_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB44_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3480,18 +3452,8 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB44_4<br class="">-; RV32I-NEXT: .LBB44_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 24<br class="">-; RV32I-NEXT: srai a1, a1, 24<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB44_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB44_1<br class="">-; RV32I-NEXT: .LBB44_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB44_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3544,9 +3506,17 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *<br class=""> ; RV64I-NEXT: slli a1, a1, 56<br class=""> ; RV64I-NEXT: srai s0, a1, 56<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB44_2<br class=""> ; RV64I-NEXT: .LBB44_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 56<br class="">+; RV64I-NEXT: srai a1, a1, 56<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB44_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB44_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB44_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB44_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3555,18 +3525,8 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB44_4<br class="">-; RV64I-NEXT: .LBB44_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 56<br class="">-; RV64I-NEXT: srai a1, a1, 56<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB44_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB44_1<br class="">-; RV64I-NEXT: .LBB44_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB44_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3622,9 +3582,16 @@ define i8 @atomicrmw_umax_i8_monotonic(i<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB45_2<br class=""> ; RV32I-NEXT: .LBB45_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s0, a1, .LBB45_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB45_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB45_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB45_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3633,17 +3600,8 @@ define i8 @atomicrmw_umax_i8_monotonic(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB45_4<br class="">-; RV32I-NEXT: .LBB45_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s0, a1, .LBB45_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB45_1<br class="">-; RV32I-NEXT: .LBB45_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB45_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3690,9 +3648,16 @@ define i8 @atomicrmw_umax_i8_monotonic(i<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB45_2<br class=""> ; RV64I-NEXT: .LBB45_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB45_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB45_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB45_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB45_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3701,17 +3666,8 @@ define i8 @atomicrmw_umax_i8_monotonic(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB45_4<br class="">-; RV64I-NEXT: .LBB45_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB45_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB45_1<br class="">-; RV64I-NEXT: .LBB45_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB45_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3762,9 +3718,16 @@ define i8 @atomicrmw_umax_i8_acquire(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB46_2<br class=""> ; RV32I-NEXT: .LBB46_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s0, a1, .LBB46_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB46_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB46_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB46_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3773,17 +3736,8 @@ define i8 @atomicrmw_umax_i8_acquire(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB46_4<br class="">-; RV32I-NEXT: .LBB46_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s0, a1, .LBB46_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB46_1<br class="">-; RV32I-NEXT: .LBB46_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB46_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3830,9 +3784,16 @@ define i8 @atomicrmw_umax_i8_acquire(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB46_2<br class=""> ; RV64I-NEXT: .LBB46_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB46_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB46_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB46_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB46_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3841,17 +3802,8 @@ define i8 @atomicrmw_umax_i8_acquire(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB46_4<br class="">-; RV64I-NEXT: .LBB46_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB46_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB46_1<br class="">-; RV64I-NEXT: .LBB46_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB46_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -3902,9 +3854,16 @@ define i8 @atomicrmw_umax_i8_release(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB47_2<br class=""> ; RV32I-NEXT: .LBB47_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s0, a1, .LBB47_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB47_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB47_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB47_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -3913,17 +3872,8 @@ define i8 @atomicrmw_umax_i8_release(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB47_4<br class="">-; RV32I-NEXT: .LBB47_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s0, a1, .LBB47_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB47_1<br class="">-; RV32I-NEXT: .LBB47_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB47_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -3970,9 +3920,16 @@ define i8 @atomicrmw_umax_i8_release(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB47_2<br class=""> ; RV64I-NEXT: .LBB47_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB47_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB47_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB47_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB47_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -3981,17 +3938,8 @@ define i8 @atomicrmw_umax_i8_release(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB47_4<br class="">-; RV64I-NEXT: .LBB47_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB47_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB47_1<br class="">-; RV64I-NEXT: .LBB47_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB47_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4042,9 +3990,16 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB48_2<br class=""> ; RV32I-NEXT: .LBB48_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s0, a1, .LBB48_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB48_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB48_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB48_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4053,17 +4008,8 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB48_4<br class="">-; RV32I-NEXT: .LBB48_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s0, a1, .LBB48_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB48_1<br class="">-; RV32I-NEXT: .LBB48_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB48_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4110,9 +4056,16 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB48_2<br class=""> ; RV64I-NEXT: .LBB48_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB48_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB48_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB48_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB48_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4121,17 +4074,8 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB48_4<br class="">-; RV64I-NEXT: .LBB48_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB48_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB48_1<br class="">-; RV64I-NEXT: .LBB48_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB48_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4182,9 +4126,16 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB49_2<br class=""> ; RV32I-NEXT: .LBB49_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s0, a1, .LBB49_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB49_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB49_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB49_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4193,17 +4144,8 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB49_4<br class="">-; RV32I-NEXT: .LBB49_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s0, a1, .LBB49_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB49_1<br class="">-; RV32I-NEXT: .LBB49_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB49_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4250,9 +4192,16 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB49_2<br class=""> ; RV64I-NEXT: .LBB49_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB49_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB49_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB49_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB49_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4261,17 +4210,8 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB49_4<br class="">-; RV64I-NEXT: .LBB49_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB49_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB49_1<br class="">-; RV64I-NEXT: .LBB49_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB49_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4322,9 +4262,16 @@ define i8 @atomicrmw_umin_i8_monotonic(i<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB50_2<br class=""> ; RV32I-NEXT: .LBB50_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s0, a1, .LBB50_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB50_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB50_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB50_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4333,17 +4280,8 @@ define i8 @atomicrmw_umin_i8_monotonic(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB50_4<br class="">-; RV32I-NEXT: .LBB50_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s0, a1, .LBB50_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB50_1<br class="">-; RV32I-NEXT: .LBB50_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB50_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4390,9 +4328,16 @@ define i8 @atomicrmw_umin_i8_monotonic(i<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB50_2<br class=""> ; RV64I-NEXT: .LBB50_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB50_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB50_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB50_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB50_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4401,17 +4346,8 @@ define i8 @atomicrmw_umin_i8_monotonic(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB50_4<br class="">-; RV64I-NEXT: .LBB50_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB50_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB50_1<br class="">-; RV64I-NEXT: .LBB50_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB50_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4462,9 +4398,16 @@ define i8 @atomicrmw_umin_i8_acquire(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB51_2<br class=""> ; RV32I-NEXT: .LBB51_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s0, a1, .LBB51_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB51_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB51_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB51_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4473,17 +4416,8 @@ define i8 @atomicrmw_umin_i8_acquire(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB51_4<br class="">-; RV32I-NEXT: .LBB51_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s0, a1, .LBB51_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB51_1<br class="">-; RV32I-NEXT: .LBB51_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB51_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4530,9 +4464,16 @@ define i8 @atomicrmw_umin_i8_acquire(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB51_2<br class=""> ; RV64I-NEXT: .LBB51_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB51_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB51_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB51_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB51_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4541,17 +4482,8 @@ define i8 @atomicrmw_umin_i8_acquire(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB51_4<br class="">-; RV64I-NEXT: .LBB51_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB51_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB51_1<br class="">-; RV64I-NEXT: .LBB51_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB51_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4602,9 +4534,16 @@ define i8 @atomicrmw_umin_i8_release(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB52_2<br class=""> ; RV32I-NEXT: .LBB52_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s0, a1, .LBB52_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB52_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB52_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB52_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4613,17 +4552,8 @@ define i8 @atomicrmw_umin_i8_release(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB52_4<br class="">-; RV32I-NEXT: .LBB52_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s0, a1, .LBB52_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB52_1<br class="">-; RV32I-NEXT: .LBB52_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB52_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4670,9 +4600,16 @@ define i8 @atomicrmw_umin_i8_release(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB52_2<br class=""> ; RV64I-NEXT: .LBB52_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB52_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB52_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB52_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB52_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4681,17 +4618,8 @@ define i8 @atomicrmw_umin_i8_release(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB52_4<br class="">-; RV64I-NEXT: .LBB52_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB52_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB52_1<br class="">-; RV64I-NEXT: .LBB52_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB52_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4742,9 +4670,16 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB53_2<br class=""> ; RV32I-NEXT: .LBB53_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s0, a1, .LBB53_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB53_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB53_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB53_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4753,17 +4688,8 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB53_4<br class="">-; RV32I-NEXT: .LBB53_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s0, a1, .LBB53_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB53_1<br class="">-; RV32I-NEXT: .LBB53_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB53_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4810,9 +4736,16 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB53_2<br class=""> ; RV64I-NEXT: .LBB53_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB53_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB53_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB53_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB53_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4821,17 +4754,8 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB53_4<br class="">-; RV64I-NEXT: .LBB53_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB53_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB53_1<br class="">-; RV64I-NEXT: .LBB53_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB53_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -4882,9 +4806,16 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8<br class=""> ; RV32I-NEXT: lbu a0, 0(a0)<br class=""> ; RV32I-NEXT: andi s0, a1, 255<br class=""> ; RV32I-NEXT: addi s3, sp, 11<br class="">-; RV32I-NEXT: j .LBB54_2<br class=""> ; RV32I-NEXT: .LBB54_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: andi a1, a0, 255<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s0, a1, .LBB54_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB54_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB54_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB54_1 Depth=1<br class=""> ; RV32I-NEXT: sb a0, 11(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -4893,17 +4824,8 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lb a0, 11(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB54_4<br class="">-; RV32I-NEXT: .LBB54_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: andi a1, a0, 255<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s0, a1, .LBB54_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB54_1<br class="">-; RV32I-NEXT: .LBB54_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB54_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -4950,9 +4872,16 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8<br class=""> ; RV64I-NEXT: lbu a0, 0(a0)<br class=""> ; RV64I-NEXT: andi s0, a1, 255<br class=""> ; RV64I-NEXT: addi s3, sp, 7<br class="">-; RV64I-NEXT: j .LBB54_2<br class=""> ; RV64I-NEXT: .LBB54_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: andi a1, a0, 255<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB54_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB54_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB54_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB54_1 Depth=1<br class=""> ; RV64I-NEXT: sb a0, 7(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -4961,17 +4890,8 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_1<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lb a0, 7(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB54_4<br class="">-; RV64I-NEXT: .LBB54_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: andi a1, a0, 255<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB54_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB54_1<br class="">-; RV64I-NEXT: .LBB54_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB54_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -7173,9 +7093,17 @@ define i16 @atomicrmw_max_i16_monotonic(<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB90_2<br class=""> ; RV32I-NEXT: .LBB90_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB90_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB90_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB90_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB90_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -7184,18 +7112,8 @@ define i16 @atomicrmw_max_i16_monotonic(<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB90_4<br class="">-; RV32I-NEXT: .LBB90_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB90_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB90_1<br class="">-; RV32I-NEXT: .LBB90_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB90_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -7249,9 +7167,17 @@ define i16 @atomicrmw_max_i16_monotonic(<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB90_2<br class=""> ; RV64I-NEXT: .LBB90_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB90_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB90_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB90_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB90_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -7260,18 +7186,8 @@ define i16 @atomicrmw_max_i16_monotonic(<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB90_4<br class="">-; RV64I-NEXT: .LBB90_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB90_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB90_1<br class="">-; RV64I-NEXT: .LBB90_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB90_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -7329,9 +7245,17 @@ define i16 @atomicrmw_max_i16_acquire(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB91_2<br class=""> ; RV32I-NEXT: .LBB91_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB91_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB91_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB91_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB91_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -7340,18 +7264,8 @@ define i16 @atomicrmw_max_i16_acquire(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB91_4<br class="">-; RV32I-NEXT: .LBB91_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB91_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB91_1<br class="">-; RV32I-NEXT: .LBB91_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB91_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -7405,9 +7319,17 @@ define i16 @atomicrmw_max_i16_acquire(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB91_2<br class=""> ; RV64I-NEXT: .LBB91_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB91_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB91_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB91_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB91_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -7416,18 +7338,8 @@ define i16 @atomicrmw_max_i16_acquire(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB91_4<br class="">-; RV64I-NEXT: .LBB91_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB91_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB91_1<br class="">-; RV64I-NEXT: .LBB91_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB91_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -7485,9 +7397,17 @@ define i16 @atomicrmw_max_i16_release(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB92_2<br class=""> ; RV32I-NEXT: .LBB92_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB92_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB92_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB92_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB92_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -7496,18 +7416,8 @@ define i16 @atomicrmw_max_i16_release(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB92_4<br class="">-; RV32I-NEXT: .LBB92_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB92_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB92_1<br class="">-; RV32I-NEXT: .LBB92_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB92_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -7561,9 +7471,17 @@ define i16 @atomicrmw_max_i16_release(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB92_2<br class=""> ; RV64I-NEXT: .LBB92_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB92_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB92_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB92_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB92_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -7572,18 +7490,8 @@ define i16 @atomicrmw_max_i16_release(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB92_4<br class="">-; RV64I-NEXT: .LBB92_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB92_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB92_1<br class="">-; RV64I-NEXT: .LBB92_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB92_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -7641,9 +7549,17 @@ define i16 @atomicrmw_max_i16_acq_rel(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB93_2<br class=""> ; RV32I-NEXT: .LBB93_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB93_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB93_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB93_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB93_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -7652,18 +7568,8 @@ define i16 @atomicrmw_max_i16_acq_rel(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB93_4<br class="">-; RV32I-NEXT: .LBB93_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB93_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB93_1<br class="">-; RV32I-NEXT: .LBB93_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB93_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -7717,9 +7623,17 @@ define i16 @atomicrmw_max_i16_acq_rel(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB93_2<br class=""> ; RV64I-NEXT: .LBB93_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB93_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB93_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB93_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB93_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -7728,18 +7642,8 @@ define i16 @atomicrmw_max_i16_acq_rel(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB93_4<br class="">-; RV64I-NEXT: .LBB93_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB93_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB93_1<br class="">-; RV64I-NEXT: .LBB93_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB93_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -7797,9 +7701,17 @@ define i16 @atomicrmw_max_i16_seq_cst(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB94_2<br class=""> ; RV32I-NEXT: .LBB94_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: blt s0, a1, .LBB94_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB94_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB94_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB94_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -7808,18 +7720,8 @@ define i16 @atomicrmw_max_i16_seq_cst(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB94_4<br class="">-; RV32I-NEXT: .LBB94_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: blt s0, a1, .LBB94_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB94_1<br class="">-; RV32I-NEXT: .LBB94_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB94_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -7873,9 +7775,17 @@ define i16 @atomicrmw_max_i16_seq_cst(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB94_2<br class=""> ; RV64I-NEXT: .LBB94_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB94_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB94_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB94_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB94_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -7884,18 +7794,8 @@ define i16 @atomicrmw_max_i16_seq_cst(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB94_4<br class="">-; RV64I-NEXT: .LBB94_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB94_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB94_1<br class="">-; RV64I-NEXT: .LBB94_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB94_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -7953,29 +7853,27 @@ define i16 @atomicrmw_min_i16_monotonic(<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB95_2<br class=""> ; RV32I-NEXT: .LBB95_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1<br class="">-; RV32I-NEXT: sh a0, 10(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB95_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB95_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB95_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB95_1 Depth=1<br class="">+; RV32I-NEXT: sh a0, 10(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class=""> ; RV32I-NEXT: mv a3, zero<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB95_4<br class="">-; RV32I-NEXT: .LBB95_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB95_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB95_1<br class="">-; RV32I-NEXT: .LBB95_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB95_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -8029,9 +7927,17 @@ define i16 @atomicrmw_min_i16_monotonic(<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB95_2<br class=""> ; RV64I-NEXT: .LBB95_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB95_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB95_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB95_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB95_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8040,18 +7946,8 @@ define i16 @atomicrmw_min_i16_monotonic(<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB95_4<br class="">-; RV64I-NEXT: .LBB95_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB95_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB95_1<br class="">-; RV64I-NEXT: .LBB95_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB95_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -8109,9 +8005,17 @@ define i16 @atomicrmw_min_i16_acquire(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB96_2<br class=""> ; RV32I-NEXT: .LBB96_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB96_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB96_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB96_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB96_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -8120,18 +8024,8 @@ define i16 @atomicrmw_min_i16_acquire(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB96_4<br class="">-; RV32I-NEXT: .LBB96_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB96_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB96_1<br class="">-; RV32I-NEXT: .LBB96_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB96_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -8185,9 +8079,17 @@ define i16 @atomicrmw_min_i16_acquire(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB96_2<br class=""> ; RV64I-NEXT: .LBB96_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB96_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB96_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB96_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB96_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8196,18 +8098,8 @@ define i16 @atomicrmw_min_i16_acquire(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB96_4<br class="">-; RV64I-NEXT: .LBB96_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB96_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB96_1<br class="">-; RV64I-NEXT: .LBB96_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB96_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -8265,9 +8157,17 @@ define i16 @atomicrmw_min_i16_release(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB97_2<br class=""> ; RV32I-NEXT: .LBB97_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB97_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB97_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB97_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB97_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -8276,18 +8176,8 @@ define i16 @atomicrmw_min_i16_release(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB97_4<br class="">-; RV32I-NEXT: .LBB97_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB97_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB97_1<br class="">-; RV32I-NEXT: .LBB97_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB97_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -8341,9 +8231,17 @@ define i16 @atomicrmw_min_i16_release(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB97_2<br class=""> ; RV64I-NEXT: .LBB97_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB97_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB97_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB97_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB97_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8352,18 +8250,8 @@ define i16 @atomicrmw_min_i16_release(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB97_4<br class="">-; RV64I-NEXT: .LBB97_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB97_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB97_1<br class="">-; RV64I-NEXT: .LBB97_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB97_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -8421,9 +8309,17 @@ define i16 @atomicrmw_min_i16_acq_rel(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB98_2<br class=""> ; RV32I-NEXT: .LBB98_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB98_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB98_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB98_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB98_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -8432,18 +8328,8 @@ define i16 @atomicrmw_min_i16_acq_rel(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB98_4<br class="">-; RV32I-NEXT: .LBB98_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB98_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB98_1<br class="">-; RV32I-NEXT: .LBB98_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB98_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -8497,9 +8383,17 @@ define i16 @atomicrmw_min_i16_acq_rel(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB98_2<br class=""> ; RV64I-NEXT: .LBB98_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB98_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB98_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB98_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB98_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8508,18 +8402,8 @@ define i16 @atomicrmw_min_i16_acq_rel(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB98_4<br class="">-; RV64I-NEXT: .LBB98_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB98_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB98_1<br class="">-; RV64I-NEXT: .LBB98_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB98_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -8577,9 +8461,17 @@ define i16 @atomicrmw_min_i16_seq_cst(i1<br class=""> ; RV32I-NEXT: slli a1, a1, 16<br class=""> ; RV32I-NEXT: srai s0, a1, 16<br class=""> ; RV32I-NEXT: addi s3, sp, 10<br class="">-; RV32I-NEXT: j .LBB99_2<br class=""> ; RV32I-NEXT: .LBB99_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: slli a1, a0, 16<br class="">+; RV32I-NEXT: srai a1, a1, 16<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bge s0, a1, .LBB99_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB99_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB99_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB99_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 10(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -8588,18 +8480,8 @@ define i16 @atomicrmw_min_i16_seq_cst(i1<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 10(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB99_4<br class="">-; RV32I-NEXT: .LBB99_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: slli a1, a0, 16<br class="">-; RV32I-NEXT: srai a1, a1, 16<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bge s0, a1, .LBB99_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB99_1<br class="">-; RV32I-NEXT: .LBB99_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB99_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -8653,9 +8535,17 @@ define i16 @atomicrmw_min_i16_seq_cst(i1<br class=""> ; RV64I-NEXT: slli a1, a1, 48<br class=""> ; RV64I-NEXT: srai s0, a1, 48<br class=""> ; RV64I-NEXT: addi s3, sp, 6<br class="">-; RV64I-NEXT: j .LBB99_2<br class=""> ; RV64I-NEXT: .LBB99_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: slli a1, a0, 48<br class="">+; RV64I-NEXT: srai a1, a1, 48<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB99_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB99_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB99_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB99_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 6(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8664,18 +8554,8 @@ define i16 @atomicrmw_min_i16_seq_cst(i1<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 6(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB99_4<br class="">-; RV64I-NEXT: .LBB99_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: slli a1, a0, 48<br class="">-; RV64I-NEXT: srai a1, a1, 48<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB99_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB99_1<br class="">-; RV64I-NEXT: .LBB99_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB99_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -8735,9 +8615,16 @@ define i16 @atomicrmw_umax_i16_monotonic<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB100_2<br class=""> ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s1, a1, .LBB100_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB100_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB100_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB100_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -8746,17 +8633,8 @@ define i16 @atomicrmw_umax_i16_monotonic<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB100_4<br class="">-; RV32I-NEXT: .LBB100_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s1, a1, .LBB100_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB100_1<br class="">-; RV32I-NEXT: .LBB100_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB100_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -8808,9 +8686,16 @@ define i16 @atomicrmw_umax_i16_monotonic<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB100_2<br class=""> ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s1, a1, .LBB100_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB100_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB100_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB100_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8819,17 +8704,8 @@ define i16 @atomicrmw_umax_i16_monotonic<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB100_4<br class="">-; RV64I-NEXT: .LBB100_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s1, a1, .LBB100_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB100_1<br class="">-; RV64I-NEXT: .LBB100_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB100_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -8885,9 +8761,16 @@ define i16 @atomicrmw_umax_i16_acquire(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB101_2<br class=""> ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s1, a1, .LBB101_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB101_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB101_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB101_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -8896,17 +8779,8 @@ define i16 @atomicrmw_umax_i16_acquire(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB101_4<br class="">-; RV32I-NEXT: .LBB101_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s1, a1, .LBB101_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB101_1<br class="">-; RV32I-NEXT: .LBB101_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB101_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -8958,9 +8832,16 @@ define i16 @atomicrmw_umax_i16_acquire(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB101_2<br class=""> ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s1, a1, .LBB101_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB101_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB101_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB101_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -8969,17 +8850,8 @@ define i16 @atomicrmw_umax_i16_acquire(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB101_4<br class="">-; RV64I-NEXT: .LBB101_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s1, a1, .LBB101_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB101_1<br class="">-; RV64I-NEXT: .LBB101_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB101_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9035,9 +8907,16 @@ define i16 @atomicrmw_umax_i16_release(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB102_2<br class=""> ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s1, a1, .LBB102_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB102_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB102_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB102_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9046,17 +8925,8 @@ define i16 @atomicrmw_umax_i16_release(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB102_4<br class="">-; RV32I-NEXT: .LBB102_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s1, a1, .LBB102_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB102_1<br class="">-; RV32I-NEXT: .LBB102_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB102_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -9108,9 +8978,16 @@ define i16 @atomicrmw_umax_i16_release(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB102_2<br class=""> ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s1, a1, .LBB102_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB102_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB102_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB102_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -9119,17 +8996,8 @@ define i16 @atomicrmw_umax_i16_release(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB102_4<br class="">-; RV64I-NEXT: .LBB102_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s1, a1, .LBB102_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB102_1<br class="">-; RV64I-NEXT: .LBB102_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB102_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9185,9 +9053,16 @@ define i16 @atomicrmw_umax_i16_acq_rel(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB103_2<br class=""> ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s1, a1, .LBB103_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB103_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB103_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB103_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9196,17 +9071,8 @@ define i16 @atomicrmw_umax_i16_acq_rel(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB103_4<br class="">-; RV32I-NEXT: .LBB103_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s1, a1, .LBB103_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB103_1<br class="">-; RV32I-NEXT: .LBB103_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB103_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -9258,9 +9124,16 @@ define i16 @atomicrmw_umax_i16_acq_rel(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB103_2<br class=""> ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s1, a1, .LBB103_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB103_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB103_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB103_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -9269,17 +9142,8 @@ define i16 @atomicrmw_umax_i16_acq_rel(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB103_4<br class="">-; RV64I-NEXT: .LBB103_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s1, a1, .LBB103_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB103_1<br class="">-; RV64I-NEXT: .LBB103_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB103_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9335,9 +9199,16 @@ define i16 @atomicrmw_umax_i16_seq_cst(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB104_2<br class=""> ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bltu s1, a1, .LBB104_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB104_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB104_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB104_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9346,17 +9217,8 @@ define i16 @atomicrmw_umax_i16_seq_cst(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB104_4<br class="">-; RV32I-NEXT: .LBB104_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bltu s1, a1, .LBB104_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB104_1<br class="">-; RV32I-NEXT: .LBB104_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB104_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -9408,9 +9270,16 @@ define i16 @atomicrmw_umax_i16_seq_cst(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB104_2<br class=""> ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s1, a1, .LBB104_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB104_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB104_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB104_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -9419,17 +9288,8 @@ define i16 @atomicrmw_umax_i16_seq_cst(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB104_4<br class="">-; RV64I-NEXT: .LBB104_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s1, a1, .LBB104_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB104_1<br class="">-; RV64I-NEXT: .LBB104_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB104_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9485,9 +9345,16 @@ define i16 @atomicrmw_umin_i16_monotonic<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB105_2<br class=""> ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s1, a1, .LBB105_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB105_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB105_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB105_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9496,17 +9363,8 @@ define i16 @atomicrmw_umin_i16_monotonic<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB105_4<br class="">-; RV32I-NEXT: .LBB105_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s1, a1, .LBB105_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB105_1<br class="">-; RV32I-NEXT: .LBB105_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB105_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -9558,9 +9416,16 @@ define i16 @atomicrmw_umin_i16_monotonic<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB105_2<br class=""> ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s1, a1, .LBB105_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB105_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB105_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB105_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -9569,17 +9434,8 @@ define i16 @atomicrmw_umin_i16_monotonic<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB105_4<br class="">-; RV64I-NEXT: .LBB105_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s1, a1, .LBB105_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB105_1<br class="">-; RV64I-NEXT: .LBB105_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB105_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9635,9 +9491,16 @@ define i16 @atomicrmw_umin_i16_acquire(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB106_2<br class=""> ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s1, a1, .LBB106_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB106_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB106_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB106_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9646,17 +9509,8 @@ define i16 @atomicrmw_umin_i16_acquire(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB106_4<br class="">-; RV32I-NEXT: .LBB106_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s1, a1, .LBB106_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB106_1<br class="">-; RV32I-NEXT: .LBB106_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB106_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -9708,9 +9562,16 @@ define i16 @atomicrmw_umin_i16_acquire(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB106_2<br class=""> ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s1, a1, .LBB106_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB106_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB106_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB106_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -9719,17 +9580,8 @@ define i16 @atomicrmw_umin_i16_acquire(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB106_4<br class="">-; RV64I-NEXT: .LBB106_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s1, a1, .LBB106_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB106_1<br class="">-; RV64I-NEXT: .LBB106_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB106_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9785,9 +9637,16 @@ define i16 @atomicrmw_umin_i16_release(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB107_2<br class=""> ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s1, a1, .LBB107_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB107_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB107_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB107_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9796,17 +9655,8 @@ define i16 @atomicrmw_umin_i16_release(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB107_4<br class="">-; RV32I-NEXT: .LBB107_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s1, a1, .LBB107_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB107_1<br class="">-; RV32I-NEXT: .LBB107_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB107_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -9858,9 +9708,16 @@ define i16 @atomicrmw_umin_i16_release(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB107_2<br class=""> ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s1, a1, .LBB107_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB107_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB107_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB107_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -9869,17 +9726,8 @@ define i16 @atomicrmw_umin_i16_release(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB107_4<br class="">-; RV64I-NEXT: .LBB107_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s1, a1, .LBB107_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB107_1<br class="">-; RV64I-NEXT: .LBB107_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB107_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -9935,9 +9783,16 @@ define i16 @atomicrmw_umin_i16_acq_rel(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB108_2<br class=""> ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s1, a1, .LBB108_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB108_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB108_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB108_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -9946,17 +9801,8 @@ define i16 @atomicrmw_umin_i16_acq_rel(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB108_4<br class="">-; RV32I-NEXT: .LBB108_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s1, a1, .LBB108_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB108_1<br class="">-; RV32I-NEXT: .LBB108_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB108_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -10008,9 +9854,16 @@ define i16 @atomicrmw_umin_i16_acq_rel(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB108_2<br class=""> ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s1, a1, .LBB108_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB108_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB108_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB108_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -10019,17 +9872,8 @@ define i16 @atomicrmw_umin_i16_acq_rel(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB108_4<br class="">-; RV64I-NEXT: .LBB108_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s1, a1, .LBB108_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB108_1<br class="">-; RV64I-NEXT: .LBB108_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB108_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -10085,9 +9929,16 @@ define i16 @atomicrmw_umin_i16_seq_cst(i<br class=""> ; RV32I-NEXT: addi s0, a1, -1<br class=""> ; RV32I-NEXT: and s1, s2, s0<br class=""> ; RV32I-NEXT: addi s3, sp, 6<br class="">-; RV32I-NEXT: j .LBB109_2<br class=""> ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: and a1, a0, s0<br class="">+; RV32I-NEXT: mv a2, a0<br class="">+; RV32I-NEXT: bgeu s1, a1, .LBB109_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB109_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: .LBB109_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB109_1 Depth=1<br class=""> ; RV32I-NEXT: sh a0, 6(sp)<br class=""> ; RV32I-NEXT: mv a0, s4<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -10096,17 +9947,8 @@ define i16 @atomicrmw_umin_i16_seq_cst(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV32I-NEXT: mv a1, a0<br class=""> ; RV32I-NEXT: lh a0, 6(sp)<br class="">-; RV32I-NEXT: bnez a1, .LBB109_4<br class="">-; RV32I-NEXT: .LBB109_2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV32I-NEXT: and a1, a0, s0<br class="">-; RV32I-NEXT: mv a2, a0<br class="">-; RV32I-NEXT: bgeu s1, a1, .LBB109_1<br class="">-; RV32I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: j .LBB109_1<br class="">-; RV32I-NEXT: .LBB109_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a1, .LBB109_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: lw s4, 8(sp)<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -10158,9 +10000,16 @@ define i16 @atomicrmw_umin_i16_seq_cst(i<br class=""> ; RV64I-NEXT: addiw s0, a1, -1<br class=""> ; RV64I-NEXT: and s1, s2, s0<br class=""> ; RV64I-NEXT: addi s3, sp, 14<br class="">-; RV64I-NEXT: j .LBB109_2<br class=""> ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: and a1, a0, s0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s1, a1, .LBB109_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB109_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB109_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB109_1 Depth=1<br class=""> ; RV64I-NEXT: sh a0, 14(sp)<br class=""> ; RV64I-NEXT: mv a0, s4<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -10169,17 +10018,8 @@ define i16 @atomicrmw_umin_i16_seq_cst(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_2<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lh a0, 14(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB109_4<br class="">-; RV64I-NEXT: .LBB109_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: and a1, a0, s0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s1, a1, .LBB109_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB109_1<br class="">-; RV64I-NEXT: .LBB109_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB109_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s4, 16(sp)<br class=""> ; RV64I-NEXT: ld s3, 24(sp)<br class=""> ; RV64I-NEXT: ld s2, 32(sp)<br class="">@@ -11500,25 +11340,23 @@ define i32 @atomicrmw_max_i32_monotonic(<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB145_3<br class=""> ; RV32I-NEXT: .LBB145_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: blt s0, a2, .LBB145_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB145_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB145_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB145_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: mv a3, zero<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB145_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB145_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB145_1<br class="">-; RV32I-NEXT: .LBB145_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB145_1<br class="">-; RV32I-NEXT: .LBB145_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB145_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -11545,9 +11383,16 @@ define i32 @atomicrmw_max_i32_monotonic(<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB145_2<br class=""> ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB145_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB145_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB145_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB145_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -11556,17 +11401,8 @@ define i32 @atomicrmw_max_i32_monotonic(<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB145_4<br class="">-; RV64I-NEXT: .LBB145_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB145_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB145_1<br class="">-; RV64I-NEXT: .LBB145_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB145_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -11595,25 +11431,23 @@ define i32 @atomicrmw_max_i32_acquire(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB146_3<br class=""> ; RV32I-NEXT: .LBB146_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: blt s0, a2, .LBB146_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB146_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB146_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB146_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 2<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB146_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB146_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB146_1<br class="">-; RV32I-NEXT: .LBB146_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB146_1<br class="">-; RV32I-NEXT: .LBB146_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB146_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -11640,9 +11474,16 @@ define i32 @atomicrmw_max_i32_acquire(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB146_2<br class=""> ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB146_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB146_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB146_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB146_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -11651,17 +11492,8 @@ define i32 @atomicrmw_max_i32_acquire(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB146_4<br class="">-; RV64I-NEXT: .LBB146_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB146_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB146_1<br class="">-; RV64I-NEXT: .LBB146_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB146_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -11690,25 +11522,23 @@ define i32 @atomicrmw_max_i32_release(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB147_3<br class=""> ; RV32I-NEXT: .LBB147_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: blt s0, a2, .LBB147_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB147_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB147_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB147_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 3<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB147_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB147_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB147_1<br class="">-; RV32I-NEXT: .LBB147_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB147_1<br class="">-; RV32I-NEXT: .LBB147_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB147_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -11735,9 +11565,16 @@ define i32 @atomicrmw_max_i32_release(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB147_2<br class=""> ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB147_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB147_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB147_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB147_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -11746,17 +11583,8 @@ define i32 @atomicrmw_max_i32_release(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB147_4<br class="">-; RV64I-NEXT: .LBB147_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB147_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB147_1<br class="">-; RV64I-NEXT: .LBB147_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB147_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -11785,25 +11613,23 @@ define i32 @atomicrmw_max_i32_acq_rel(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB148_3<br class=""> ; RV32I-NEXT: .LBB148_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: blt s0, a2, .LBB148_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB148_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB148_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB148_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 4<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB148_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB148_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB148_1<br class="">-; RV32I-NEXT: .LBB148_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB148_1<br class="">-; RV32I-NEXT: .LBB148_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB148_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -11830,9 +11656,16 @@ define i32 @atomicrmw_max_i32_acq_rel(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB148_2<br class=""> ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB148_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB148_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB148_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB148_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -11841,17 +11674,8 @@ define i32 @atomicrmw_max_i32_acq_rel(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB148_4<br class="">-; RV64I-NEXT: .LBB148_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB148_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB148_1<br class="">-; RV64I-NEXT: .LBB148_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB148_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -11880,25 +11704,23 @@ define i32 @atomicrmw_max_i32_seq_cst(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB149_3<br class=""> ; RV32I-NEXT: .LBB149_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: blt s0, a2, .LBB149_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB149_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB149_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB149_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 5<br class=""> ; RV32I-NEXT: addi a4, zero, 5<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB149_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB149_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB149_1<br class="">-; RV32I-NEXT: .LBB149_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB149_1<br class="">-; RV32I-NEXT: .LBB149_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB149_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -11925,9 +11747,16 @@ define i32 @atomicrmw_max_i32_seq_cst(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB149_2<br class=""> ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: blt s0, a1, .LBB149_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB149_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB149_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB149_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -11936,17 +11765,8 @@ define i32 @atomicrmw_max_i32_seq_cst(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB149_4<br class="">-; RV64I-NEXT: .LBB149_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: blt s0, a1, .LBB149_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB149_1<br class="">-; RV64I-NEXT: .LBB149_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB149_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -11975,25 +11795,23 @@ define i32 @atomicrmw_min_i32_monotonic(<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB150_3<br class=""> ; RV32I-NEXT: .LBB150_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bge s0, a2, .LBB150_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB150_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB150_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB150_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: mv a3, zero<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB150_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB150_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB150_1<br class="">-; RV32I-NEXT: .LBB150_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB150_1<br class="">-; RV32I-NEXT: .LBB150_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB150_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12020,9 +11838,16 @@ define i32 @atomicrmw_min_i32_monotonic(<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB150_2<br class=""> ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB150_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB150_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB150_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB150_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12031,17 +11856,8 @@ define i32 @atomicrmw_min_i32_monotonic(<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB150_4<br class="">-; RV64I-NEXT: .LBB150_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB150_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB150_1<br class="">-; RV64I-NEXT: .LBB150_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB150_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12070,25 +11886,23 @@ define i32 @atomicrmw_min_i32_acquire(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB151_3<br class=""> ; RV32I-NEXT: .LBB151_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bge s0, a2, .LBB151_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB151_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB151_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB151_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 2<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB151_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB151_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB151_1<br class="">-; RV32I-NEXT: .LBB151_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB151_1<br class="">-; RV32I-NEXT: .LBB151_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB151_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12115,9 +11929,16 @@ define i32 @atomicrmw_min_i32_acquire(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB151_2<br class=""> ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB151_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB151_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB151_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB151_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12126,17 +11947,8 @@ define i32 @atomicrmw_min_i32_acquire(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB151_4<br class="">-; RV64I-NEXT: .LBB151_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB151_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB151_1<br class="">-; RV64I-NEXT: .LBB151_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB151_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12165,25 +11977,23 @@ define i32 @atomicrmw_min_i32_release(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB152_3<br class=""> ; RV32I-NEXT: .LBB152_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bge s0, a2, .LBB152_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB152_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB152_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB152_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 3<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB152_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB152_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB152_1<br class="">-; RV32I-NEXT: .LBB152_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB152_1<br class="">-; RV32I-NEXT: .LBB152_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB152_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12210,9 +12020,16 @@ define i32 @atomicrmw_min_i32_release(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB152_2<br class=""> ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB152_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB152_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB152_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB152_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12221,17 +12038,8 @@ define i32 @atomicrmw_min_i32_release(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB152_4<br class="">-; RV64I-NEXT: .LBB152_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB152_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB152_1<br class="">-; RV64I-NEXT: .LBB152_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB152_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12260,25 +12068,23 @@ define i32 @atomicrmw_min_i32_acq_rel(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB153_3<br class=""> ; RV32I-NEXT: .LBB153_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bge s0, a2, .LBB153_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB153_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB153_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB153_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 4<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB153_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB153_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB153_1<br class="">-; RV32I-NEXT: .LBB153_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB153_1<br class="">-; RV32I-NEXT: .LBB153_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB153_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12305,9 +12111,16 @@ define i32 @atomicrmw_min_i32_acq_rel(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB153_2<br class=""> ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB153_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB153_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB153_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB153_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12316,17 +12129,8 @@ define i32 @atomicrmw_min_i32_acq_rel(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB153_4<br class="">-; RV64I-NEXT: .LBB153_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB153_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB153_1<br class="">-; RV64I-NEXT: .LBB153_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB153_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12355,25 +12159,23 @@ define i32 @atomicrmw_min_i32_seq_cst(i3<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: blt s0, a2, .LBB154_3<br class=""> ; RV32I-NEXT: .LBB154_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bge s0, a2, .LBB154_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB154_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB154_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB154_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 5<br class=""> ; RV32I-NEXT: addi a4, zero, 5<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB154_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB154_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bge s0, a2, .LBB154_1<br class="">-; RV32I-NEXT: .LBB154_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB154_1<br class="">-; RV32I-NEXT: .LBB154_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB154_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12400,9 +12202,16 @@ define i32 @atomicrmw_min_i32_seq_cst(i3<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB154_2<br class=""> ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bge s0, a1, .LBB154_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB154_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB154_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB154_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12411,17 +12220,8 @@ define i32 @atomicrmw_min_i32_seq_cst(i3<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB154_4<br class="">-; RV64I-NEXT: .LBB154_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bge s0, a1, .LBB154_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB154_1<br class="">-; RV64I-NEXT: .LBB154_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB154_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12450,25 +12250,23 @@ define i32 @atomicrmw_umax_i32_monotonic<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB155_3<br class=""> ; RV32I-NEXT: .LBB155_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bltu s0, a2, .LBB155_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB155_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB155_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB155_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: mv a3, zero<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB155_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB155_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB155_1<br class="">-; RV32I-NEXT: .LBB155_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB155_1<br class="">-; RV32I-NEXT: .LBB155_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB155_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12495,9 +12293,16 @@ define i32 @atomicrmw_umax_i32_monotonic<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB155_2<br class=""> ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB155_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB155_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB155_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB155_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12506,17 +12311,8 @@ define i32 @atomicrmw_umax_i32_monotonic<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB155_4<br class="">-; RV64I-NEXT: .LBB155_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB155_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB155_1<br class="">-; RV64I-NEXT: .LBB155_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB155_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12545,25 +12341,23 @@ define i32 @atomicrmw_umax_i32_acquire(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB156_3<br class=""> ; RV32I-NEXT: .LBB156_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bltu s0, a2, .LBB156_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB156_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB156_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB156_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 2<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB156_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB156_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB156_1<br class="">-; RV32I-NEXT: .LBB156_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB156_1<br class="">-; RV32I-NEXT: .LBB156_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB156_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12590,9 +12384,16 @@ define i32 @atomicrmw_umax_i32_acquire(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB156_2<br class=""> ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB156_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB156_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB156_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB156_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12601,17 +12402,8 @@ define i32 @atomicrmw_umax_i32_acquire(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB156_4<br class="">-; RV64I-NEXT: .LBB156_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB156_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB156_1<br class="">-; RV64I-NEXT: .LBB156_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB156_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12640,25 +12432,23 @@ define i32 @atomicrmw_umax_i32_release(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB157_3<br class=""> ; RV32I-NEXT: .LBB157_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bltu s0, a2, .LBB157_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB157_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB157_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB157_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 3<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB157_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB157_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB157_1<br class="">-; RV32I-NEXT: .LBB157_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB157_1<br class="">-; RV32I-NEXT: .LBB157_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB157_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12685,9 +12475,16 @@ define i32 @atomicrmw_umax_i32_release(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB157_2<br class=""> ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB157_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB157_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB157_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB157_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12696,17 +12493,8 @@ define i32 @atomicrmw_umax_i32_release(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB157_4<br class="">-; RV64I-NEXT: .LBB157_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB157_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB157_1<br class="">-; RV64I-NEXT: .LBB157_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB157_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12735,25 +12523,23 @@ define i32 @atomicrmw_umax_i32_acq_rel(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB158_3<br class=""> ; RV32I-NEXT: .LBB158_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bltu s0, a2, .LBB158_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB158_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB158_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB158_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 4<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB158_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB158_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB158_1<br class="">-; RV32I-NEXT: .LBB158_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB158_1<br class="">-; RV32I-NEXT: .LBB158_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB158_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12780,9 +12566,16 @@ define i32 @atomicrmw_umax_i32_acq_rel(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB158_2<br class=""> ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB158_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB158_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB158_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB158_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12791,17 +12584,8 @@ define i32 @atomicrmw_umax_i32_acq_rel(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB158_4<br class="">-; RV64I-NEXT: .LBB158_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB158_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB158_1<br class="">-; RV64I-NEXT: .LBB158_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB158_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12830,25 +12614,23 @@ define i32 @atomicrmw_umax_i32_seq_cst(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB159_3<br class=""> ; RV32I-NEXT: .LBB159_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bltu s0, a2, .LBB159_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB159_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB159_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB159_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 5<br class=""> ; RV32I-NEXT: addi a4, zero, 5<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB159_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB159_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB159_1<br class="">-; RV32I-NEXT: .LBB159_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB159_1<br class="">-; RV32I-NEXT: .LBB159_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB159_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12875,9 +12657,16 @@ define i32 @atomicrmw_umax_i32_seq_cst(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB159_2<br class=""> ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bltu s0, a1, .LBB159_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB159_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB159_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB159_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12886,17 +12675,8 @@ define i32 @atomicrmw_umax_i32_seq_cst(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB159_4<br class="">-; RV64I-NEXT: .LBB159_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bltu s0, a1, .LBB159_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB159_1<br class="">-; RV64I-NEXT: .LBB159_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB159_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -12925,25 +12705,23 @@ define i32 @atomicrmw_umin_i32_monotonic<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB160_3<br class=""> ; RV32I-NEXT: .LBB160_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bgeu s0, a2, .LBB160_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB160_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB160_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB160_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: mv a3, zero<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB160_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB160_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB160_1<br class="">-; RV32I-NEXT: .LBB160_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB160_1<br class="">-; RV32I-NEXT: .LBB160_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB160_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -12970,9 +12748,16 @@ define i32 @atomicrmw_umin_i32_monotonic<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB160_2<br class=""> ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB160_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB160_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB160_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB160_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -12981,17 +12766,8 @@ define i32 @atomicrmw_umin_i32_monotonic<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB160_4<br class="">-; RV64I-NEXT: .LBB160_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB160_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB160_1<br class="">-; RV64I-NEXT: .LBB160_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB160_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -13020,25 +12796,23 @@ define i32 @atomicrmw_umin_i32_acquire(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB161_3<br class=""> ; RV32I-NEXT: .LBB161_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bgeu s0, a2, .LBB161_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB161_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB161_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB161_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 2<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB161_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB161_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB161_1<br class="">-; RV32I-NEXT: .LBB161_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB161_1<br class="">-; RV32I-NEXT: .LBB161_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB161_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -13065,9 +12839,16 @@ define i32 @atomicrmw_umin_i32_acquire(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB161_2<br class=""> ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB161_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB161_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB161_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB161_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -13076,17 +12857,8 @@ define i32 @atomicrmw_umin_i32_acquire(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB161_4<br class="">-; RV64I-NEXT: .LBB161_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB161_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB161_1<br class="">-; RV64I-NEXT: .LBB161_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB161_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -13115,25 +12887,23 @@ define i32 @atomicrmw_umin_i32_release(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB162_3<br class=""> ; RV32I-NEXT: .LBB162_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bgeu s0, a2, .LBB162_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB162_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB162_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB162_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 3<br class=""> ; RV32I-NEXT: mv a4, zero<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB162_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB162_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB162_1<br class="">-; RV32I-NEXT: .LBB162_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB162_1<br class="">-; RV32I-NEXT: .LBB162_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB162_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -13160,9 +12930,16 @@ define i32 @atomicrmw_umin_i32_release(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB162_2<br class=""> ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB162_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB162_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB162_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB162_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -13171,17 +12948,8 @@ define i32 @atomicrmw_umin_i32_release(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB162_4<br class="">-; RV64I-NEXT: .LBB162_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB162_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB162_1<br class="">-; RV64I-NEXT: .LBB162_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB162_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -13210,25 +12978,23 @@ define i32 @atomicrmw_umin_i32_acq_rel(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB163_3<br class=""> ; RV32I-NEXT: .LBB163_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bgeu s0, a2, .LBB163_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB163_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB163_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB163_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 4<br class=""> ; RV32I-NEXT: addi a4, zero, 2<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB163_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB163_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB163_1<br class="">-; RV32I-NEXT: .LBB163_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB163_1<br class="">-; RV32I-NEXT: .LBB163_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB163_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -13255,9 +13021,16 @@ define i32 @atomicrmw_umin_i32_acq_rel(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB163_2<br class=""> ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB163_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB163_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB163_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB163_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -13266,17 +13039,8 @@ define i32 @atomicrmw_umin_i32_acq_rel(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB163_4<br class="">-; RV64I-NEXT: .LBB163_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB163_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB163_1<br class="">-; RV64I-NEXT: .LBB163_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB163_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -13305,25 +13069,23 @@ define i32 @atomicrmw_umin_i32_seq_cst(i<br class=""> ; RV32I-NEXT: mv s1, a0<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: addi s2, sp, 12<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bltu s0, a2, .LBB164_3<br class=""> ; RV32I-NEXT: .LBB164_1: # %atomicrmw.start<br class=""> ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: sw a2, 12(sp)<br class="">+; RV32I-NEXT: bgeu s0, a2, .LBB164_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB164_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s0<br class="">+; RV32I-NEXT: .LBB164_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB164_1 Depth=1<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s2<br class=""> ; RV32I-NEXT: addi a3, zero, 5<br class=""> ; RV32I-NEXT: addi a4, zero, 5<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV32I-NEXT: lw a2, 12(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB164_4<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: # in Loop: Header=BB164_1 Depth=1<br class="">-; RV32I-NEXT: sw a2, 12(sp)<br class="">-; RV32I-NEXT: bgeu s0, a2, .LBB164_1<br class="">-; RV32I-NEXT: .LBB164_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s0<br class="">-; RV32I-NEXT: j .LBB164_1<br class="">-; RV32I-NEXT: .LBB164_4: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB164_1<br class="">+; RV32I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class=""> ; RV32I-NEXT: lw s1, 20(sp)<br class="">@@ -13350,9 +13112,16 @@ define i32 @atomicrmw_umin_i32_seq_cst(i<br class=""> ; RV64I-NEXT: lwu a0, 0(a0)<br class=""> ; RV64I-NEXT: sext.w s0, a1<br class=""> ; RV64I-NEXT: addi s3, sp, 4<br class="">-; RV64I-NEXT: j .LBB164_2<br class=""> ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1<br class="">+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sext.w a1, a0<br class="">+; RV64I-NEXT: mv a2, a0<br class="">+; RV64I-NEXT: bgeu s0, a1, .LBB164_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB164_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s2<br class="">+; RV64I-NEXT: .LBB164_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB164_1 Depth=1<br class=""> ; RV64I-NEXT: sw a0, 4(sp)<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s3<br class="">@@ -13361,17 +13130,8 @@ define i32 @atomicrmw_umin_i32_seq_cst(i<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_4<br class=""> ; RV64I-NEXT: mv a1, a0<br class=""> ; RV64I-NEXT: lw a0, 4(sp)<br class="">-; RV64I-NEXT: bnez a1, .LBB164_4<br class="">-; RV64I-NEXT: .LBB164_2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; RV64I-NEXT: sext.w a1, a0<br class="">-; RV64I-NEXT: mv a2, a0<br class="">-; RV64I-NEXT: bgeu s0, a1, .LBB164_1<br class="">-; RV64I-NEXT: # %bb.3: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1<br class="">-; RV64I-NEXT: mv a2, s2<br class="">-; RV64I-NEXT: j .LBB164_1<br class="">-; RV64I-NEXT: .LBB164_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a1, .LBB164_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: ld s3, 8(sp)<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -14808,9 +14568,26 @@ define i64 @atomicrmw_max_i64_monotonic(<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB200_3<br class="">-; RV32I-NEXT: j .LBB200_4<br class=""> ; RV32I-NEXT: .LBB200_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB200_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32I-NEXT: slt a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB200_4<br class="">+; RV32I-NEXT: .LBB200_3: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB200_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB200_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB200_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -14819,23 +14596,8 @@ define i64 @atomicrmw_max_i64_monotonic(<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB200_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB200_4<br class="">-; RV32I-NEXT: .LBB200_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB200_5<br class="">-; RV32I-NEXT: .LBB200_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB200_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB200_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB200_1<br class="">-; RV32I-NEXT: .LBB200_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB200_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -14859,9 +14621,26 @@ define i64 @atomicrmw_max_i64_monotonic(<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB200_3<br class="">-; RV32IA-NEXT: j .LBB200_4<br class=""> ; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB200_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32IA-NEXT: slt a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB200_4<br class="">+; RV32IA-NEXT: .LBB200_3: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB200_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB200_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB200_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -14870,23 +14649,8 @@ define i64 @atomicrmw_max_i64_monotonic(<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB200_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB200_4<br class="">-; RV32IA-NEXT: .LBB200_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB200_5<br class="">-; RV32IA-NEXT: .LBB200_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB200_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB200_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB200_1<br class="">-; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB200_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -14907,25 +14671,23 @@ define i64 @atomicrmw_max_i64_monotonic(<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB200_3<br class=""> ; RV64I-NEXT: .LBB200_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: blt s0, a2, .LBB200_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB200_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: mv a3, zero<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB200_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB200_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB200_1<br class="">-; RV64I-NEXT: .LBB200_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB200_1<br class="">-; RV64I-NEXT: .LBB200_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB200_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -14957,9 +14719,26 @@ define i64 @atomicrmw_max_i64_acquire(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB201_3<br class="">-; RV32I-NEXT: j .LBB201_4<br class=""> ; RV32I-NEXT: .LBB201_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB201_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32I-NEXT: slt a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB201_4<br class="">+; RV32I-NEXT: .LBB201_3: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB201_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB201_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB201_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -14968,23 +14747,8 @@ define i64 @atomicrmw_max_i64_acquire(i6<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB201_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB201_4<br class="">-; RV32I-NEXT: .LBB201_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB201_5<br class="">-; RV32I-NEXT: .LBB201_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB201_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB201_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB201_1<br class="">-; RV32I-NEXT: .LBB201_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB201_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15008,9 +14772,26 @@ define i64 @atomicrmw_max_i64_acquire(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB201_3<br class="">-; RV32IA-NEXT: j .LBB201_4<br class=""> ; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB201_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32IA-NEXT: slt a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB201_4<br class="">+; RV32IA-NEXT: .LBB201_3: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB201_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB201_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB201_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -15019,23 +14800,8 @@ define i64 @atomicrmw_max_i64_acquire(i6<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB201_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB201_4<br class="">-; RV32IA-NEXT: .LBB201_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB201_5<br class="">-; RV32IA-NEXT: .LBB201_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB201_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB201_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB201_1<br class="">-; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB201_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15056,25 +14822,23 @@ define i64 @atomicrmw_max_i64_acquire(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB201_3<br class=""> ; RV64I-NEXT: .LBB201_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: blt s0, a2, .LBB201_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB201_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 2<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB201_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB201_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB201_1<br class="">-; RV64I-NEXT: .LBB201_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB201_1<br class="">-; RV64I-NEXT: .LBB201_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB201_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -15106,9 +14870,26 @@ define i64 @atomicrmw_max_i64_release(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB202_3<br class="">-; RV32I-NEXT: j .LBB202_4<br class=""> ; RV32I-NEXT: .LBB202_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB202_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32I-NEXT: slt a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB202_4<br class="">+; RV32I-NEXT: .LBB202_3: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB202_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB202_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB202_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -15117,23 +14898,8 @@ define i64 @atomicrmw_max_i64_release(i6<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB202_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB202_4<br class="">-; RV32I-NEXT: .LBB202_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB202_5<br class="">-; RV32I-NEXT: .LBB202_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB202_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB202_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB202_1<br class="">-; RV32I-NEXT: .LBB202_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB202_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15157,9 +14923,26 @@ define i64 @atomicrmw_max_i64_release(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB202_3<br class="">-; RV32IA-NEXT: j .LBB202_4<br class=""> ; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB202_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32IA-NEXT: slt a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB202_4<br class="">+; RV32IA-NEXT: .LBB202_3: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB202_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB202_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB202_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -15168,23 +14951,8 @@ define i64 @atomicrmw_max_i64_release(i6<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB202_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB202_4<br class="">-; RV32IA-NEXT: .LBB202_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB202_5<br class="">-; RV32IA-NEXT: .LBB202_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB202_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB202_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB202_1<br class="">-; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB202_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15205,25 +14973,23 @@ define i64 @atomicrmw_max_i64_release(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB202_3<br class=""> ; RV64I-NEXT: .LBB202_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: blt s0, a2, .LBB202_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB202_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 3<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB202_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB202_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB202_1<br class="">-; RV64I-NEXT: .LBB202_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB202_1<br class="">-; RV64I-NEXT: .LBB202_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB202_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -15255,9 +15021,26 @@ define i64 @atomicrmw_max_i64_acq_rel(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB203_3<br class="">-; RV32I-NEXT: j .LBB203_4<br class=""> ; RV32I-NEXT: .LBB203_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB203_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32I-NEXT: slt a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB203_4<br class="">+; RV32I-NEXT: .LBB203_3: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB203_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB203_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB203_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -15266,23 +15049,8 @@ define i64 @atomicrmw_max_i64_acq_rel(i6<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB203_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB203_4<br class="">-; RV32I-NEXT: .LBB203_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB203_5<br class="">-; RV32I-NEXT: .LBB203_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB203_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB203_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB203_1<br class="">-; RV32I-NEXT: .LBB203_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB203_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15306,9 +15074,26 @@ define i64 @atomicrmw_max_i64_acq_rel(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB203_3<br class="">-; RV32IA-NEXT: j .LBB203_4<br class=""> ; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB203_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32IA-NEXT: slt a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB203_4<br class="">+; RV32IA-NEXT: .LBB203_3: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB203_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB203_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB203_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -15317,23 +15102,8 @@ define i64 @atomicrmw_max_i64_acq_rel(i6<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB203_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB203_4<br class="">-; RV32IA-NEXT: .LBB203_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB203_5<br class="">-; RV32IA-NEXT: .LBB203_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB203_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB203_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB203_1<br class="">-; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB203_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15354,25 +15124,23 @@ define i64 @atomicrmw_max_i64_acq_rel(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB203_3<br class=""> ; RV64I-NEXT: .LBB203_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: blt s0, a2, .LBB203_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB203_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 4<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB203_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB203_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB203_1<br class="">-; RV64I-NEXT: .LBB203_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB203_1<br class="">-; RV64I-NEXT: .LBB203_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB203_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -15404,9 +15172,26 @@ define i64 @atomicrmw_max_i64_seq_cst(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB204_3<br class="">-; RV32I-NEXT: j .LBB204_4<br class=""> ; RV32I-NEXT: .LBB204_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB204_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32I-NEXT: slt a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB204_4<br class="">+; RV32I-NEXT: .LBB204_3: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB204_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB204_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB204_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -15415,23 +15200,8 @@ define i64 @atomicrmw_max_i64_seq_cst(i6<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB204_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB204_4<br class="">-; RV32I-NEXT: .LBB204_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB204_5<br class="">-; RV32I-NEXT: .LBB204_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB204_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB204_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB204_1<br class="">-; RV32I-NEXT: .LBB204_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB204_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15455,9 +15225,26 @@ define i64 @atomicrmw_max_i64_seq_cst(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB204_3<br class="">-; RV32IA-NEXT: j .LBB204_4<br class=""> ; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB204_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32IA-NEXT: slt a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB204_4<br class="">+; RV32IA-NEXT: .LBB204_3: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB204_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB204_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB204_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -15466,23 +15253,8 @@ define i64 @atomicrmw_max_i64_seq_cst(i6<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB204_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB204_4<br class="">-; RV32IA-NEXT: .LBB204_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB204_5<br class="">-; RV32IA-NEXT: .LBB204_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB204_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB204_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB204_1<br class="">-; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB204_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15503,25 +15275,23 @@ define i64 @atomicrmw_max_i64_seq_cst(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB204_3<br class=""> ; RV64I-NEXT: .LBB204_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: blt s0, a2, .LBB204_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB204_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 5<br class=""> ; RV64I-NEXT: addi a4, zero, 5<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB204_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB204_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB204_1<br class="">-; RV64I-NEXT: .LBB204_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB204_1<br class="">-; RV64I-NEXT: .LBB204_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB204_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -15553,35 +15323,37 @@ define i64 @atomicrmw_min_i64_monotonic(<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB205_3<br class="">-; RV32I-NEXT: j .LBB205_4<br class=""> ; RV32I-NEXT: .LBB205_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: mv a4, zero<br class="">-; RV32I-NEXT: mv a5, zero<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB205_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB205_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB205_4<br class="">-; RV32I-NEXT: .LBB205_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB205_5<br class="">-; RV32I-NEXT: .LBB205_4:<br class="">+; RV32I-NEXT: j .LBB205_4<br class="">+; RV32I-NEXT: .LBB205_3: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB205_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB205_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB205_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB205_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB205_1<br class="">-; RV32I-NEXT: .LBB205_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB205_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: mv a4, zero<br class="">+; RV32I-NEXT: mv a5, zero<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB205_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15605,35 +15377,37 @@ define i64 @atomicrmw_min_i64_monotonic(<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB205_3<br class="">-; RV32IA-NEXT: j .LBB205_4<br class=""> ; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: mv a4, zero<br class="">-; RV32IA-NEXT: mv a5, zero<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB205_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB205_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB205_4<br class="">-; RV32IA-NEXT: .LBB205_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB205_5<br class="">-; RV32IA-NEXT: .LBB205_4:<br class="">+; RV32IA-NEXT: j .LBB205_4<br class="">+; RV32IA-NEXT: .LBB205_3: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB205_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB205_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB205_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB205_1<br class="">-; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB205_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: mv a4, zero<br class="">+; RV32IA-NEXT: mv a5, zero<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB205_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15654,25 +15428,23 @@ define i64 @atomicrmw_min_i64_monotonic(<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB205_3<br class=""> ; RV64I-NEXT: .LBB205_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bge s0, a2, .LBB205_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB205_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: mv a3, zero<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB205_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB205_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB205_1<br class="">-; RV64I-NEXT: .LBB205_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB205_1<br class="">-; RV64I-NEXT: .LBB205_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB205_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -15704,35 +15476,37 @@ define i64 @atomicrmw_min_i64_acquire(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB206_3<br class="">-; RV32I-NEXT: j .LBB206_4<br class=""> ; RV32I-NEXT: .LBB206_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 2<br class="">-; RV32I-NEXT: addi a5, zero, 2<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB206_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB206_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB206_4<br class="">-; RV32I-NEXT: .LBB206_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB206_5<br class="">-; RV32I-NEXT: .LBB206_4:<br class="">+; RV32I-NEXT: j .LBB206_4<br class="">+; RV32I-NEXT: .LBB206_3: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB206_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB206_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB206_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB206_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB206_1<br class="">-; RV32I-NEXT: .LBB206_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB206_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 2<br class="">+; RV32I-NEXT: addi a5, zero, 2<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB206_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15756,35 +15530,37 @@ define i64 @atomicrmw_min_i64_acquire(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB206_3<br class="">-; RV32IA-NEXT: j .LBB206_4<br class=""> ; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 2<br class="">-; RV32IA-NEXT: addi a5, zero, 2<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB206_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB206_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB206_4<br class="">-; RV32IA-NEXT: .LBB206_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB206_5<br class="">-; RV32IA-NEXT: .LBB206_4:<br class="">+; RV32IA-NEXT: j .LBB206_4<br class="">+; RV32IA-NEXT: .LBB206_3: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB206_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB206_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB206_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB206_1<br class="">-; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB206_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 2<br class="">+; RV32IA-NEXT: addi a5, zero, 2<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB206_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15805,25 +15581,23 @@ define i64 @atomicrmw_min_i64_acquire(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB206_3<br class=""> ; RV64I-NEXT: .LBB206_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bge s0, a2, .LBB206_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB206_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 2<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB206_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB206_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB206_1<br class="">-; RV64I-NEXT: .LBB206_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB206_1<br class="">-; RV64I-NEXT: .LBB206_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB206_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -15855,35 +15629,37 @@ define i64 @atomicrmw_min_i64_release(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB207_3<br class="">-; RV32I-NEXT: j .LBB207_4<br class=""> ; RV32I-NEXT: .LBB207_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 3<br class="">-; RV32I-NEXT: mv a5, zero<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB207_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB207_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB207_4<br class="">-; RV32I-NEXT: .LBB207_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB207_5<br class="">-; RV32I-NEXT: .LBB207_4:<br class="">+; RV32I-NEXT: j .LBB207_4<br class="">+; RV32I-NEXT: .LBB207_3: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB207_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB207_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB207_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB207_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB207_1<br class="">-; RV32I-NEXT: .LBB207_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB207_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 3<br class="">+; RV32I-NEXT: mv a5, zero<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB207_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -15907,35 +15683,37 @@ define i64 @atomicrmw_min_i64_release(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB207_3<br class="">-; RV32IA-NEXT: j .LBB207_4<br class=""> ; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 3<br class="">-; RV32IA-NEXT: mv a5, zero<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB207_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB207_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB207_4<br class="">-; RV32IA-NEXT: .LBB207_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB207_5<br class="">-; RV32IA-NEXT: .LBB207_4:<br class="">+; RV32IA-NEXT: j .LBB207_4<br class="">+; RV32IA-NEXT: .LBB207_3: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB207_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB207_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB207_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB207_1<br class="">-; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB207_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 3<br class="">+; RV32IA-NEXT: mv a5, zero<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB207_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -15956,25 +15734,23 @@ define i64 @atomicrmw_min_i64_release(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB207_3<br class=""> ; RV64I-NEXT: .LBB207_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bge s0, a2, .LBB207_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB207_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 3<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB207_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB207_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB207_1<br class="">-; RV64I-NEXT: .LBB207_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB207_1<br class="">-; RV64I-NEXT: .LBB207_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB207_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16006,35 +15782,37 @@ define i64 @atomicrmw_min_i64_acq_rel(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB208_3<br class="">-; RV32I-NEXT: j .LBB208_4<br class=""> ; RV32I-NEXT: .LBB208_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 4<br class="">-; RV32I-NEXT: addi a5, zero, 2<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB208_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB208_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB208_4<br class="">-; RV32I-NEXT: .LBB208_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB208_5<br class="">-; RV32I-NEXT: .LBB208_4:<br class="">+; RV32I-NEXT: j .LBB208_4<br class="">+; RV32I-NEXT: .LBB208_3: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB208_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB208_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB208_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB208_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB208_1<br class="">-; RV32I-NEXT: .LBB208_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB208_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 4<br class="">+; RV32I-NEXT: addi a5, zero, 2<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB208_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16058,35 +15836,37 @@ define i64 @atomicrmw_min_i64_acq_rel(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB208_3<br class="">-; RV32IA-NEXT: j .LBB208_4<br class=""> ; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 4<br class="">-; RV32IA-NEXT: addi a5, zero, 2<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB208_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB208_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB208_4<br class="">-; RV32IA-NEXT: .LBB208_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB208_5<br class="">-; RV32IA-NEXT: .LBB208_4:<br class="">+; RV32IA-NEXT: j .LBB208_4<br class="">+; RV32IA-NEXT: .LBB208_3: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB208_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB208_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB208_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB208_1<br class="">-; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB208_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 4<br class="">+; RV32IA-NEXT: addi a5, zero, 2<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB208_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -16107,25 +15887,23 @@ define i64 @atomicrmw_min_i64_acq_rel(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB208_3<br class=""> ; RV64I-NEXT: .LBB208_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bge s0, a2, .LBB208_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB208_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 4<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB208_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB208_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB208_1<br class="">-; RV64I-NEXT: .LBB208_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB208_1<br class="">-; RV64I-NEXT: .LBB208_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB208_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16157,35 +15935,37 @@ define i64 @atomicrmw_min_i64_seq_cst(i6<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB209_3<br class="">-; RV32I-NEXT: j .LBB209_4<br class=""> ; RV32I-NEXT: .LBB209_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 5<br class="">-; RV32I-NEXT: addi a5, zero, 5<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB209_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB209_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB209_4<br class="">-; RV32I-NEXT: .LBB209_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32I-NEXT: slt a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB209_5<br class="">-; RV32I-NEXT: .LBB209_4:<br class="">+; RV32I-NEXT: j .LBB209_4<br class="">+; RV32I-NEXT: .LBB209_3: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB209_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB209_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB209_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB209_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB209_1<br class="">-; RV32I-NEXT: .LBB209_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB209_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 5<br class="">+; RV32I-NEXT: addi a5, zero, 5<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB209_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16209,35 +15989,37 @@ define i64 @atomicrmw_min_i64_seq_cst(i6<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB209_3<br class="">-; RV32IA-NEXT: j .LBB209_4<br class=""> ; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 5<br class="">-; RV32IA-NEXT: addi a5, zero, 5<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB209_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB209_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB209_4<br class="">-; RV32IA-NEXT: .LBB209_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32IA-NEXT: slt a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB209_5<br class="">-; RV32IA-NEXT: .LBB209_4:<br class="">+; RV32IA-NEXT: j .LBB209_4<br class="">+; RV32IA-NEXT: .LBB209_3: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB209_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB209_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB209_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB209_1<br class="">-; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB209_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 5<br class="">+; RV32IA-NEXT: addi a5, zero, 5<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB209_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -16258,25 +16040,23 @@ define i64 @atomicrmw_min_i64_seq_cst(i6<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: blt s0, a2, .LBB209_3<br class=""> ; RV64I-NEXT: .LBB209_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bge s0, a2, .LBB209_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB209_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 5<br class=""> ; RV64I-NEXT: addi a4, zero, 5<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB209_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB209_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bge s0, a2, .LBB209_1<br class="">-; RV64I-NEXT: .LBB209_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB209_1<br class="">-; RV64I-NEXT: .LBB209_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB209_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16308,9 +16088,26 @@ define i64 @atomicrmw_umax_i64_monotonic<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB210_3<br class="">-; RV32I-NEXT: j .LBB210_4<br class=""> ; RV32I-NEXT: .LBB210_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB210_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB210_4<br class="">+; RV32I-NEXT: .LBB210_3: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB210_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB210_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB210_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -16319,23 +16116,8 @@ define i64 @atomicrmw_umax_i64_monotonic<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB210_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB210_4<br class="">-; RV32I-NEXT: .LBB210_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB210_5<br class="">-; RV32I-NEXT: .LBB210_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB210_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB210_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB210_1<br class="">-; RV32I-NEXT: .LBB210_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB210_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16359,9 +16141,26 @@ define i64 @atomicrmw_umax_i64_monotonic<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB210_3<br class="">-; RV32IA-NEXT: j .LBB210_4<br class=""> ; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB210_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB210_4<br class="">+; RV32IA-NEXT: .LBB210_3: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB210_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB210_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB210_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -16370,23 +16169,8 @@ define i64 @atomicrmw_umax_i64_monotonic<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB210_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB210_4<br class="">-; RV32IA-NEXT: .LBB210_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB210_5<br class="">-; RV32IA-NEXT: .LBB210_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB210_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB210_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB210_1<br class="">-; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB210_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -16407,25 +16191,23 @@ define i64 @atomicrmw_umax_i64_monotonic<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB210_3<br class=""> ; RV64I-NEXT: .LBB210_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bltu s0, a2, .LBB210_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB210_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: mv a3, zero<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB210_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB210_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB210_1<br class="">-; RV64I-NEXT: .LBB210_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB210_1<br class="">-; RV64I-NEXT: .LBB210_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB210_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16457,9 +16239,26 @@ define i64 @atomicrmw_umax_i64_acquire(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB211_3<br class="">-; RV32I-NEXT: j .LBB211_4<br class=""> ; RV32I-NEXT: .LBB211_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB211_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB211_4<br class="">+; RV32I-NEXT: .LBB211_3: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB211_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB211_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB211_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -16468,23 +16267,8 @@ define i64 @atomicrmw_umax_i64_acquire(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB211_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB211_4<br class="">-; RV32I-NEXT: .LBB211_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB211_5<br class="">-; RV32I-NEXT: .LBB211_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB211_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB211_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB211_1<br class="">-; RV32I-NEXT: .LBB211_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB211_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16508,9 +16292,26 @@ define i64 @atomicrmw_umax_i64_acquire(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB211_3<br class="">-; RV32IA-NEXT: j .LBB211_4<br class=""> ; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB211_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB211_4<br class="">+; RV32IA-NEXT: .LBB211_3: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB211_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB211_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB211_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -16519,23 +16320,8 @@ define i64 @atomicrmw_umax_i64_acquire(i<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB211_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB211_4<br class="">-; RV32IA-NEXT: .LBB211_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB211_5<br class="">-; RV32IA-NEXT: .LBB211_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB211_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB211_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB211_1<br class="">-; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB211_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -16556,25 +16342,23 @@ define i64 @atomicrmw_umax_i64_acquire(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB211_3<br class=""> ; RV64I-NEXT: .LBB211_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bltu s0, a2, .LBB211_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB211_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 2<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB211_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB211_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB211_1<br class="">-; RV64I-NEXT: .LBB211_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB211_1<br class="">-; RV64I-NEXT: .LBB211_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB211_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16606,34 +16390,36 @@ define i64 @atomicrmw_umax_i64_release(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB212_3<br class="">-; RV32I-NEXT: j .LBB212_4<br class=""> ; RV32I-NEXT: .LBB212_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 3<br class="">-; RV32I-NEXT: mv a5, zero<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB212_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB212_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB212_4<br class="">-; RV32I-NEXT: .LBB212_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB212_5<br class="">-; RV32I-NEXT: .LBB212_4:<br class="">+; RV32I-NEXT: j .LBB212_4<br class="">+; RV32I-NEXT: .LBB212_3: # in Loop: Header=BB212_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB212_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB212_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB212_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB212_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB212_1<br class="">-; RV32I-NEXT: .LBB212_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB212_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 3<br class="">+; RV32I-NEXT: mv a5, zero<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB212_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16657,9 +16443,26 @@ define i64 @atomicrmw_umax_i64_release(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB212_3<br class="">-; RV32IA-NEXT: j .LBB212_4<br class=""> ; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB212_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB212_4<br class="">+; RV32IA-NEXT: .LBB212_3: # in Loop: Header=BB212_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB212_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB212_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB212_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -16668,23 +16471,8 @@ define i64 @atomicrmw_umax_i64_release(i<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB212_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB212_4<br class="">-; RV32IA-NEXT: .LBB212_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB212_5<br class="">-; RV32IA-NEXT: .LBB212_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB212_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB212_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB212_1<br class="">-; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB212_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -16705,25 +16493,23 @@ define i64 @atomicrmw_umax_i64_release(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB212_3<br class=""> ; RV64I-NEXT: .LBB212_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bltu s0, a2, .LBB212_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB212_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 3<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB212_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB212_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB212_1<br class="">-; RV64I-NEXT: .LBB212_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB212_1<br class="">-; RV64I-NEXT: .LBB212_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB212_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16755,9 +16541,26 @@ define i64 @atomicrmw_umax_i64_acq_rel(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB213_3<br class="">-; RV32I-NEXT: j .LBB213_4<br class=""> ; RV32I-NEXT: .LBB213_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB213_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB213_4<br class="">+; RV32I-NEXT: .LBB213_3: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB213_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB213_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB213_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -16766,23 +16569,8 @@ define i64 @atomicrmw_umax_i64_acq_rel(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB213_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB213_4<br class="">-; RV32I-NEXT: .LBB213_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB213_5<br class="">-; RV32I-NEXT: .LBB213_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB213_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB213_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB213_1<br class="">-; RV32I-NEXT: .LBB213_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB213_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16806,9 +16594,26 @@ define i64 @atomicrmw_umax_i64_acq_rel(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB213_3<br class="">-; RV32IA-NEXT: j .LBB213_4<br class=""> ; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB213_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB213_4<br class="">+; RV32IA-NEXT: .LBB213_3: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB213_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB213_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB213_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -16817,23 +16622,8 @@ define i64 @atomicrmw_umax_i64_acq_rel(i<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB213_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB213_4<br class="">-; RV32IA-NEXT: .LBB213_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB213_5<br class="">-; RV32IA-NEXT: .LBB213_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB213_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB213_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB213_1<br class="">-; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB213_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -16854,25 +16644,23 @@ define i64 @atomicrmw_umax_i64_acq_rel(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB213_3<br class=""> ; RV64I-NEXT: .LBB213_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bltu s0, a2, .LBB213_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB213_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 4<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB213_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB213_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB213_1<br class="">-; RV64I-NEXT: .LBB213_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB213_1<br class="">-; RV64I-NEXT: .LBB213_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB213_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -16904,9 +16692,26 @@ define i64 @atomicrmw_umax_i64_seq_cst(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB214_3<br class="">-; RV32I-NEXT: j .LBB214_4<br class=""> ; RV32I-NEXT: .LBB214_1: # %atomicrmw.start<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB214_3<br class="">+; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s0, a1<br class="">+; RV32I-NEXT: j .LBB214_4<br class="">+; RV32I-NEXT: .LBB214_3: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32I-NEXT: sltu a0, s2, a2<br class="">+; RV32I-NEXT: .LBB214_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32I-NEXT: sw a2, 0(sp)<br class="">+; RV32I-NEXT: mv a3, a1<br class="">+; RV32I-NEXT: bnez a0, .LBB214_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32I-NEXT: mv a2, s2<br class="">+; RV32I-NEXT: mv a3, s0<br class="">+; RV32I-NEXT: .LBB214_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class=""> ; RV32I-NEXT: sw a1, 4(sp)<br class=""> ; RV32I-NEXT: mv a0, s1<br class=""> ; RV32I-NEXT: mv a1, s3<br class="">@@ -16915,23 +16720,8 @@ define i64 @atomicrmw_umax_i64_seq_cst(i<br class=""> ; RV32I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32I-NEXT: lw a1, 4(sp)<br class=""> ; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB214_7<br class="">-; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB214_4<br class="">-; RV32I-NEXT: .LBB214_3: # %atomicrmw.start<br class="">-; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB214_5<br class="">-; RV32I-NEXT: .LBB214_4:<br class="">-; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB214_5: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a2, 0(sp)<br class="">-; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB214_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32I-NEXT: mv a2, s2<br class="">-; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB214_1<br class="">-; RV32I-NEXT: .LBB214_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: beqz a0, .LBB214_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -16955,9 +16745,26 @@ define i64 @atomicrmw_umax_i64_seq_cst(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB214_3<br class="">-; RV32IA-NEXT: j .LBB214_4<br class=""> ; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB214_3<br class="">+; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s0, a1<br class="">+; RV32IA-NEXT: j .LBB214_4<br class="">+; RV32IA-NEXT: .LBB214_3: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32IA-NEXT: sltu a0, s2, a2<br class="">+; RV32IA-NEXT: .LBB214_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32IA-NEXT: sw a2, 0(sp)<br class="">+; RV32IA-NEXT: mv a3, a1<br class="">+; RV32IA-NEXT: bnez a0, .LBB214_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV32IA-NEXT: mv a2, s2<br class="">+; RV32IA-NEXT: mv a3, s0<br class="">+; RV32IA-NEXT: .LBB214_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1<br class=""> ; RV32IA-NEXT: sw a1, 4(sp)<br class=""> ; RV32IA-NEXT: mv a0, s1<br class=""> ; RV32IA-NEXT: mv a1, s3<br class="">@@ -16966,23 +16773,8 @@ define i64 @atomicrmw_umax_i64_seq_cst(i<br class=""> ; RV32IA-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV32IA-NEXT: lw a1, 4(sp)<br class=""> ; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB214_7<br class="">-; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB214_4<br class="">-; RV32IA-NEXT: .LBB214_3: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB214_5<br class="">-; RV32IA-NEXT: .LBB214_4:<br class="">-; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB214_5: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a2, 0(sp)<br class="">-; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB214_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">-; RV32IA-NEXT: mv a2, s2<br class="">-; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB214_1<br class="">-; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: beqz a0, .LBB214_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -17003,25 +16795,23 @@ define i64 @atomicrmw_umax_i64_seq_cst(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB214_3<br class=""> ; RV64I-NEXT: .LBB214_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bltu s0, a2, .LBB214_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB214_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 5<br class=""> ; RV64I-NEXT: addi a4, zero, 5<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB214_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB214_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB214_1<br class="">-; RV64I-NEXT: .LBB214_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB214_1<br class="">-; RV64I-NEXT: .LBB214_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB214_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -17053,35 +16843,37 @@ define i64 @atomicrmw_umin_i64_monotonic<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB215_3<br class="">-; RV32I-NEXT: j .LBB215_4<br class=""> ; RV32I-NEXT: .LBB215_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: mv a4, zero<br class="">-; RV32I-NEXT: mv a5, zero<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB215_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB215_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB215_4<br class="">-; RV32I-NEXT: .LBB215_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB215_5<br class="">-; RV32I-NEXT: .LBB215_4:<br class="">+; RV32I-NEXT: j .LBB215_4<br class="">+; RV32I-NEXT: .LBB215_3: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB215_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB215_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB215_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB215_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB215_1<br class="">-; RV32I-NEXT: .LBB215_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB215_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: mv a4, zero<br class="">+; RV32I-NEXT: mv a5, zero<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB215_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -17105,35 +16897,37 @@ define i64 @atomicrmw_umin_i64_monotonic<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB215_3<br class="">-; RV32IA-NEXT: j .LBB215_4<br class=""> ; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: mv a4, zero<br class="">-; RV32IA-NEXT: mv a5, zero<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB215_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB215_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB215_4<br class="">-; RV32IA-NEXT: .LBB215_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB215_5<br class="">-; RV32IA-NEXT: .LBB215_4:<br class="">+; RV32IA-NEXT: j .LBB215_4<br class="">+; RV32IA-NEXT: .LBB215_3: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB215_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB215_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB215_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB215_1<br class="">-; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB215_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: mv a4, zero<br class="">+; RV32IA-NEXT: mv a5, zero<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB215_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -17154,25 +16948,23 @@ define i64 @atomicrmw_umin_i64_monotonic<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB215_3<br class=""> ; RV64I-NEXT: .LBB215_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bgeu s0, a2, .LBB215_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB215_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: mv a3, zero<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB215_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB215_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB215_1<br class="">-; RV64I-NEXT: .LBB215_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB215_1<br class="">-; RV64I-NEXT: .LBB215_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB215_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -17204,35 +16996,37 @@ define i64 @atomicrmw_umin_i64_acquire(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB216_3<br class="">-; RV32I-NEXT: j .LBB216_4<br class=""> ; RV32I-NEXT: .LBB216_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 2<br class="">-; RV32I-NEXT: addi a5, zero, 2<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB216_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB216_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB216_4<br class="">-; RV32I-NEXT: .LBB216_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB216_5<br class="">-; RV32I-NEXT: .LBB216_4:<br class="">+; RV32I-NEXT: j .LBB216_4<br class="">+; RV32I-NEXT: .LBB216_3: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB216_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB216_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB216_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB216_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB216_1<br class="">-; RV32I-NEXT: .LBB216_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB216_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 2<br class="">+; RV32I-NEXT: addi a5, zero, 2<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB216_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -17256,35 +17050,37 @@ define i64 @atomicrmw_umin_i64_acquire(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB216_3<br class="">-; RV32IA-NEXT: j .LBB216_4<br class=""> ; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 2<br class="">-; RV32IA-NEXT: addi a5, zero, 2<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB216_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB216_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB216_4<br class="">-; RV32IA-NEXT: .LBB216_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB216_5<br class="">-; RV32IA-NEXT: .LBB216_4:<br class="">+; RV32IA-NEXT: j .LBB216_4<br class="">+; RV32IA-NEXT: .LBB216_3: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB216_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB216_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB216_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB216_1<br class="">-; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB216_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 2<br class="">+; RV32IA-NEXT: addi a5, zero, 2<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB216_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -17305,25 +17101,23 @@ define i64 @atomicrmw_umin_i64_acquire(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB216_3<br class=""> ; RV64I-NEXT: .LBB216_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bgeu s0, a2, .LBB216_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB216_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 2<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB216_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB216_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB216_1<br class="">-; RV64I-NEXT: .LBB216_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB216_1<br class="">-; RV64I-NEXT: .LBB216_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB216_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -17355,35 +17149,37 @@ define i64 @atomicrmw_umin_i64_release(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB217_3<br class="">-; RV32I-NEXT: j .LBB217_4<br class=""> ; RV32I-NEXT: .LBB217_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 3<br class="">-; RV32I-NEXT: mv a5, zero<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB217_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB217_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB217_4<br class="">-; RV32I-NEXT: .LBB217_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB217_5<br class="">-; RV32I-NEXT: .LBB217_4:<br class="">+; RV32I-NEXT: j .LBB217_4<br class="">+; RV32I-NEXT: .LBB217_3: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB217_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB217_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB217_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB217_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB217_1<br class="">-; RV32I-NEXT: .LBB217_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB217_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 3<br class="">+; RV32I-NEXT: mv a5, zero<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB217_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -17407,35 +17203,37 @@ define i64 @atomicrmw_umin_i64_release(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB217_3<br class="">-; RV32IA-NEXT: j .LBB217_4<br class=""> ; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 3<br class="">-; RV32IA-NEXT: mv a5, zero<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB217_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB217_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB217_4<br class="">-; RV32IA-NEXT: .LBB217_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB217_5<br class="">-; RV32IA-NEXT: .LBB217_4:<br class="">+; RV32IA-NEXT: j .LBB217_4<br class="">+; RV32IA-NEXT: .LBB217_3: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB217_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB217_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB217_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB217_1<br class="">-; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB217_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 3<br class="">+; RV32IA-NEXT: mv a5, zero<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB217_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -17456,25 +17254,23 @@ define i64 @atomicrmw_umin_i64_release(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB217_3<br class=""> ; RV64I-NEXT: .LBB217_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bgeu s0, a2, .LBB217_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB217_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 3<br class=""> ; RV64I-NEXT: mv a4, zero<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB217_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB217_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB217_1<br class="">-; RV64I-NEXT: .LBB217_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB217_1<br class="">-; RV64I-NEXT: .LBB217_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB217_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -17506,35 +17302,37 @@ define i64 @atomicrmw_umin_i64_acq_rel(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB218_3<br class="">-; RV32I-NEXT: j .LBB218_4<br class=""> ; RV32I-NEXT: .LBB218_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 4<br class="">-; RV32I-NEXT: addi a5, zero, 2<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB218_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB218_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB218_4<br class="">-; RV32I-NEXT: .LBB218_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB218_5<br class="">-; RV32I-NEXT: .LBB218_4:<br class="">+; RV32I-NEXT: j .LBB218_4<br class="">+; RV32I-NEXT: .LBB218_3: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB218_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB218_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB218_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB218_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB218_1<br class="">-; RV32I-NEXT: .LBB218_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB218_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 4<br class="">+; RV32I-NEXT: addi a5, zero, 2<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB218_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -17558,35 +17356,37 @@ define i64 @atomicrmw_umin_i64_acq_rel(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB218_3<br class="">-; RV32IA-NEXT: j .LBB218_4<br class=""> ; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 4<br class="">-; RV32IA-NEXT: addi a5, zero, 2<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB218_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB218_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB218_4<br class="">-; RV32IA-NEXT: .LBB218_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB218_5<br class="">-; RV32IA-NEXT: .LBB218_4:<br class="">+; RV32IA-NEXT: j .LBB218_4<br class="">+; RV32IA-NEXT: .LBB218_3: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB218_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB218_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB218_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB218_1<br class="">-; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB218_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 4<br class="">+; RV32IA-NEXT: addi a5, zero, 2<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB218_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -17607,25 +17407,23 @@ define i64 @atomicrmw_umin_i64_acq_rel(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB218_3<br class=""> ; RV64I-NEXT: .LBB218_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bgeu s0, a2, .LBB218_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB218_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 4<br class=""> ; RV64I-NEXT: addi a4, zero, 2<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB218_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB218_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB218_1<br class="">-; RV64I-NEXT: .LBB218_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB218_1<br class="">-; RV64I-NEXT: .LBB218_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB218_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class="">@@ -17657,35 +17455,37 @@ define i64 @atomicrmw_umin_i64_seq_cst(i<br class=""> ; RV32I-NEXT: lw a1, 4(a0)<br class=""> ; RV32I-NEXT: lw a2, 0(a0)<br class=""> ; RV32I-NEXT: mv s3, sp<br class="">-; RV32I-NEXT: bne a1, s0, .LBB219_3<br class="">-; RV32I-NEXT: j .LBB219_4<br class=""> ; RV32I-NEXT: .LBB219_1: # %atomicrmw.start<br class="">-; RV32I-NEXT: sw a1, 4(sp)<br class="">-; RV32I-NEXT: mv a0, s1<br class="">-; RV32I-NEXT: mv a1, s3<br class="">-; RV32I-NEXT: addi a4, zero, 5<br class="">-; RV32I-NEXT: addi a5, zero, 5<br class="">-; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32I-NEXT: lw a1, 4(sp)<br class="">-; RV32I-NEXT: lw a2, 0(sp)<br class="">-; RV32I-NEXT: bnez a0, .LBB219_7<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: beq a1, s0, .LBB219_3<br class=""> ; RV32I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32I-NEXT: beq a1, s0, .LBB219_4<br class="">-; RV32I-NEXT: .LBB219_3: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s0, a1<br class="">-; RV32I-NEXT: j .LBB219_5<br class="">-; RV32I-NEXT: .LBB219_4:<br class="">+; RV32I-NEXT: j .LBB219_4<br class="">+; RV32I-NEXT: .LBB219_3: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32I-NEXT: sltu a0, s2, a2<br class="">-; RV32I-NEXT: .LBB219_5: # %atomicrmw.start<br class="">+; RV32I-NEXT: .LBB219_4: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32I-NEXT: xori a0, a0, 1<br class=""> ; RV32I-NEXT: sw a2, 0(sp)<br class=""> ; RV32I-NEXT: mv a3, a1<br class="">-; RV32I-NEXT: bnez a0, .LBB219_1<br class="">-; RV32I-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32I-NEXT: bnez a0, .LBB219_6<br class="">+; RV32I-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32I-NEXT: mv a2, s2<br class=""> ; RV32I-NEXT: mv a3, s0<br class="">-; RV32I-NEXT: j .LBB219_1<br class="">-; RV32I-NEXT: .LBB219_7: # %atomicrmw.end<br class="">+; RV32I-NEXT: .LBB219_6: # %atomicrmw.start<br class="">+; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class="">+; RV32I-NEXT: sw a1, 4(sp)<br class="">+; RV32I-NEXT: mv a0, s1<br class="">+; RV32I-NEXT: mv a1, s3<br class="">+; RV32I-NEXT: addi a4, zero, 5<br class="">+; RV32I-NEXT: addi a5, zero, 5<br class="">+; RV32I-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32I-NEXT: lw a1, 4(sp)<br class="">+; RV32I-NEXT: lw a2, 0(sp)<br class="">+; RV32I-NEXT: beqz a0, .LBB219_1<br class="">+; RV32I-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32I-NEXT: mv a0, a2<br class=""> ; RV32I-NEXT: lw s3, 12(sp)<br class=""> ; RV32I-NEXT: lw s2, 16(sp)<br class="">@@ -17709,35 +17509,37 @@ define i64 @atomicrmw_umin_i64_seq_cst(i<br class=""> ; RV32IA-NEXT: lw a1, 4(a0)<br class=""> ; RV32IA-NEXT: lw a2, 0(a0)<br class=""> ; RV32IA-NEXT: mv s3, sp<br class="">-; RV32IA-NEXT: bne a1, s0, .LBB219_3<br class="">-; RV32IA-NEXT: j .LBB219_4<br class=""> ; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start<br class="">-; RV32IA-NEXT: sw a1, 4(sp)<br class="">-; RV32IA-NEXT: mv a0, s1<br class="">-; RV32IA-NEXT: mv a1, s3<br class="">-; RV32IA-NEXT: addi a4, zero, 5<br class="">-; RV32IA-NEXT: addi a5, zero, 5<br class="">-; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">-; RV32IA-NEXT: lw a1, 4(sp)<br class="">-; RV32IA-NEXT: lw a2, 0(sp)<br class="">-; RV32IA-NEXT: bnez a0, .LBB219_7<br class="">+; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32IA-NEXT: beq a1, s0, .LBB219_3<br class=""> ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV32IA-NEXT: beq a1, s0, .LBB219_4<br class="">-; RV32IA-NEXT: .LBB219_3: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s0, a1<br class="">-; RV32IA-NEXT: j .LBB219_5<br class="">-; RV32IA-NEXT: .LBB219_4:<br class="">+; RV32IA-NEXT: j .LBB219_4<br class="">+; RV32IA-NEXT: .LBB219_3: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32IA-NEXT: sltu a0, s2, a2<br class="">-; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: .LBB219_4: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32IA-NEXT: xori a0, a0, 1<br class=""> ; RV32IA-NEXT: sw a2, 0(sp)<br class=""> ; RV32IA-NEXT: mv a3, a1<br class="">-; RV32IA-NEXT: bnez a0, .LBB219_1<br class="">-; RV32IA-NEXT: # %bb.6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: bnez a0, .LBB219_6<br class="">+; RV32IA-NEXT: # %bb.5: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV32IA-NEXT: mv a2, s2<br class=""> ; RV32IA-NEXT: mv a3, s0<br class="">-; RV32IA-NEXT: j .LBB219_1<br class="">-; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end<br class="">+; RV32IA-NEXT: .LBB219_6: # %atomicrmw.start<br class="">+; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1<br class="">+; RV32IA-NEXT: sw a1, 4(sp)<br class="">+; RV32IA-NEXT: mv a0, s1<br class="">+; RV32IA-NEXT: mv a1, s3<br class="">+; RV32IA-NEXT: addi a4, zero, 5<br class="">+; RV32IA-NEXT: addi a5, zero, 5<br class="">+; RV32IA-NEXT: call __atomic_compare_exchange_8<br class="">+; RV32IA-NEXT: lw a1, 4(sp)<br class="">+; RV32IA-NEXT: lw a2, 0(sp)<br class="">+; RV32IA-NEXT: beqz a0, .LBB219_1<br class="">+; RV32IA-NEXT: # %bb.7: # %atomicrmw.end<br class=""> ; RV32IA-NEXT: mv a0, a2<br class=""> ; RV32IA-NEXT: lw s3, 12(sp)<br class=""> ; RV32IA-NEXT: lw s2, 16(sp)<br class="">@@ -17758,25 +17560,23 @@ define i64 @atomicrmw_umin_i64_seq_cst(i<br class=""> ; RV64I-NEXT: mv s1, a0<br class=""> ; RV64I-NEXT: ld a2, 0(a0)<br class=""> ; RV64I-NEXT: addi s2, sp, 8<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bltu s0, a2, .LBB219_3<br class=""> ; RV64I-NEXT: .LBB219_1: # %atomicrmw.start<br class=""> ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV64I-NEXT: sd a2, 8(sp)<br class="">+; RV64I-NEXT: bgeu s0, a2, .LBB219_3<br class="">+; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class="">+; RV64I-NEXT: mv a2, s0<br class="">+; RV64I-NEXT: .LBB219_3: # %atomicrmw.start<br class="">+; RV64I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class=""> ; RV64I-NEXT: mv a0, s1<br class=""> ; RV64I-NEXT: mv a1, s2<br class=""> ; RV64I-NEXT: addi a3, zero, 5<br class=""> ; RV64I-NEXT: addi a4, zero, 5<br class=""> ; RV64I-NEXT: call __atomic_compare_exchange_8<br class=""> ; RV64I-NEXT: ld a2, 8(sp)<br class="">-; RV64I-NEXT: bnez a0, .LBB219_4<br class="">-; RV64I-NEXT: # %bb.2: # %atomicrmw.start<br class="">-; RV64I-NEXT: # in Loop: Header=BB219_1 Depth=1<br class="">-; RV64I-NEXT: sd a2, 8(sp)<br class="">-; RV64I-NEXT: bgeu s0, a2, .LBB219_1<br class="">-; RV64I-NEXT: .LBB219_3: # %atomicrmw.start<br class="">-; RV64I-NEXT: mv a2, s0<br class="">-; RV64I-NEXT: j .LBB219_1<br class="">-; RV64I-NEXT: .LBB219_4: # %atomicrmw.end<br class="">+; RV64I-NEXT: beqz a0, .LBB219_1<br class="">+; RV64I-NEXT: # %bb.4: # %atomicrmw.end<br class=""> ; RV64I-NEXT: mv a0, a2<br class=""> ; RV64I-NEXT: ld s2, 16(sp)<br class=""> ; RV64I-NEXT: ld s1, 24(sp)<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/RISCV/remat.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/remat.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/remat.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/RISCV/remat.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/RISCV/remat.ll Thu Aug 22 09:21:32 2019<br class="">@@ -52,32 +52,24 @@ define i32 @test() nounwind {<br class=""> ; RV32I-NEXT: lui s0, %hi(d)<br class=""> ; RV32I-NEXT: lui s10, %hi(c)<br class=""> ; RV32I-NEXT: lui s11, %hi(b)<br class="">+; RV32I-NEXT: .LBB0_2: # %for.body<br class="">+; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; RV32I-NEXT: lw a1, %lo(l)(s2)<br class="">-; RV32I-NEXT: bnez a1, .LBB0_4<br class="">-; RV32I-NEXT: j .LBB0_5<br class="">-; RV32I-NEXT: .LBB0_2: # %for.inc<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">-; RV32I-NEXT: lw a0, %lo(a)(s9)<br class="">-; RV32I-NEXT: addi a0, a0, -1<br class="">-; RV32I-NEXT: sw a0, %lo(a)(s9)<br class="">-; RV32I-NEXT: beqz a0, .LBB0_11<br class="">-; RV32I-NEXT: # %bb.3: # %for.body<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">-; RV32I-NEXT: lw a1, %lo(l)(s2)<br class="">-; RV32I-NEXT: beqz a1, .LBB0_5<br class="">-; RV32I-NEXT: .LBB0_4: # %if.then<br class="">+; RV32I-NEXT: beqz a1, .LBB0_4<br class="">+; RV32I-NEXT: # %bb.3: # %if.then<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a4, %lo(e)(s1)<br class=""> ; RV32I-NEXT: lw a3, %lo(d)(s0)<br class=""> ; RV32I-NEXT: lw a2, %lo(c)(s10)<br class=""> ; RV32I-NEXT: lw a1, %lo(b)(s11)<br class=""> ; RV32I-NEXT: addi a5, zero, 32<br class=""> ; RV32I-NEXT: call foo<br class="">-; RV32I-NEXT: .LBB0_5: # %if.end<br class="">-; RV32I-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; RV32I-NEXT: .LBB0_4: # %if.end<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a0, %lo(k)(s3)<br class="">-; RV32I-NEXT: beqz a0, .LBB0_7<br class="">-; RV32I-NEXT: # %bb.6: # %if.then3<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">+; RV32I-NEXT: beqz a0, .LBB0_6<br class="">+; RV32I-NEXT: # %bb.5: # %if.then3<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a4, %lo(f)(s8)<br class=""> ; RV32I-NEXT: lw a3, %lo(e)(s1)<br class=""> ; RV32I-NEXT: lw a2, %lo(d)(s0)<br class="">@@ -85,12 +77,12 @@ define i32 @test() nounwind {<br class=""> ; RV32I-NEXT: lw a0, %lo(b)(s11)<br class=""> ; RV32I-NEXT: addi a5, zero, 64<br class=""> ; RV32I-NEXT: call foo<br class="">-; RV32I-NEXT: .LBB0_7: # %if.end5<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">+; RV32I-NEXT: .LBB0_6: # %if.end5<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a0, %lo(j)(s4)<br class="">-; RV32I-NEXT: beqz a0, .LBB0_9<br class="">-; RV32I-NEXT: # %bb.8: # %if.then7<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">+; RV32I-NEXT: beqz a0, .LBB0_8<br class="">+; RV32I-NEXT: # %bb.7: # %if.then7<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a4, %lo(g)(s7)<br class=""> ; RV32I-NEXT: lw a3, %lo(f)(s8)<br class=""> ; RV32I-NEXT: lw a2, %lo(e)(s1)<br class="">@@ -98,12 +90,12 @@ define i32 @test() nounwind {<br class=""> ; RV32I-NEXT: lw a0, %lo(c)(s10)<br class=""> ; RV32I-NEXT: addi a5, zero, 32<br class=""> ; RV32I-NEXT: call foo<br class="">-; RV32I-NEXT: .LBB0_9: # %if.end9<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">+; RV32I-NEXT: .LBB0_8: # %if.end9<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a0, %lo(i)(s6)<br class="">-; RV32I-NEXT: beqz a0, .LBB0_2<br class="">-; RV32I-NEXT: # %bb.10: # %if.then11<br class="">-; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1<br class="">+; RV32I-NEXT: beqz a0, .LBB0_10<br class="">+; RV32I-NEXT: # %bb.9: # %if.then11<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; RV32I-NEXT: lw a4, %lo(h)(s5)<br class=""> ; RV32I-NEXT: lw a3, %lo(g)(s7)<br class=""> ; RV32I-NEXT: lw a2, %lo(f)(s8)<br class="">@@ -111,7 +103,12 @@ define i32 @test() nounwind {<br class=""> ; RV32I-NEXT: lw a0, %lo(d)(s0)<br class=""> ; RV32I-NEXT: addi a5, zero, 32<br class=""> ; RV32I-NEXT: call foo<br class="">-; RV32I-NEXT: j .LBB0_2<br class="">+; RV32I-NEXT: .LBB0_10: # %for.inc<br class="">+; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1<br class="">+; RV32I-NEXT: lw a0, %lo(a)(s9)<br class="">+; RV32I-NEXT: addi a0, a0, -1<br class="">+; RV32I-NEXT: sw a0, %lo(a)(s9)<br class="">+; RV32I-NEXT: bnez a0, .LBB0_2<br class=""> ; RV32I-NEXT: .LBB0_11: # %for.end<br class=""> ; RV32I-NEXT: addi a0, zero, 1<br class=""> ; RV32I-NEXT: lw s11, 12(sp)<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.ll Thu Aug 22 09:21:32 2019<br class="">@@ -10,9 +10,8 @@ define i32 @C(i32 %x, i32* nocapture %y)<br class=""> ; CHECK-NEXT: push {r4, r5, r7, lr}<br class=""> ; CHECK-NEXT: movs r2, #0<br class=""> ; CHECK-NEXT: ldr r3, .LCPI0_0<br class="">+; CHECK-NEXT: b .LBB0_4<br class=""> ; CHECK-NEXT: .LBB0_1:<br class="">-; CHECK-NEXT: cmp r2, #128<br class="">-; CHECK-NEXT: beq .LBB0_5<br class=""> ; CHECK-NEXT: movs r4, #0<br class=""> ; CHECK-NEXT: str r4, [r3, #8]<br class=""> ; CHECK-NEXT: lsls r4, r2, #2<br class="">@@ -21,15 +20,16 @@ define i32 @C(i32 %x, i32* nocapture %y)<br class=""> ; CHECK-NEXT: movs r5, #1<br class=""> ; CHECK-NEXT: str r5, [r3, #12]<br class=""> ; CHECK-NEXT: isb sy<br class="">-; CHECK-NEXT: .LBB0_3:<br class="">+; CHECK-NEXT: .LBB0_2:<br class=""> ; CHECK-NEXT: ldr r5, [r3, #12]<br class=""> ; CHECK-NEXT: cmp r5, #0<br class="">-; CHECK-NEXT: bne .LBB0_3<br class="">+; CHECK-NEXT: bne .LBB0_2<br class=""> ; CHECK-NEXT: ldr r5, [r3, #4]<br class=""> ; CHECK-NEXT: str r5, [r1, r4]<br class=""> ; CHECK-NEXT: adds r2, r2, #1<br class="">-; CHECK-NEXT: b .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_5:<br class="">+; CHECK-NEXT: .LBB0_4:<br class="">+; CHECK-NEXT: cmp r2, #128<br class="">+; CHECK-NEXT: bne .LBB0_1<br class=""> ; CHECK-NEXT: movs r0, #0<br class=""> ; CHECK-NEXT: pop {r4, r5, r7, pc}<br class=""> ; CHECK-NEXT: .p2align 2<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/Thumb/pr42760.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/pr42760.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/pr42760.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/Thumb/pr42760.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/Thumb/pr42760.ll Thu Aug 22 09:21:32 2019<br class="">@@ -6,31 +6,27 @@ define hidden void @test() {<br class=""> ; CHECK: @ %bb.0: @ %entry<br class=""> ; CHECK-NEXT: movs r0, #1<br class=""> ; CHECK-NEXT: lsls r1, r0, #2<br class="">-; CHECK-NEXT: b .LBB0_2<br class="">-; CHECK-NEXT: .LBB0_1: @ %bb2<br class="">-; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1<br class="">-; CHECK-NEXT: cmp r0, #0<br class="">-; CHECK-NEXT: bne .LBB0_6<br class="">-; CHECK-NEXT: .LBB0_2: @ %switch<br class="">+; CHECK-NEXT: .LBB0_1: @ %switch<br class=""> ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1<br class=""> ; CHECK-NEXT: adr r2, .LJTI0_0<br class=""> ; CHECK-NEXT: ldr r2, [r2, r1]<br class=""> ; CHECK-NEXT: mov pc, r2<br class="">-; CHECK-NEXT: @ %bb.3:<br class="">+; CHECK-NEXT: @ %bb.2:<br class=""> ; CHECK-NEXT: .p2align 2<br class=""> ; CHECK-NEXT: .LJTI0_0:<br class="">-; CHECK-NEXT: .long .LBB0_6+1<br class="">+; CHECK-NEXT: .long .LBB0_5+1<br class=""> ; CHECK-NEXT: .long .LBB0_4+1<br class="">-; CHECK-NEXT: .long .LBB0_6+1<br class=""> ; CHECK-NEXT: .long .LBB0_5+1<br class="">-; CHECK-NEXT: .LBB0_4: @ %switch<br class="">-; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1<br class="">-; CHECK-NEXT: b .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_5: @ %bb<br class="">-; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1<br class="">+; CHECK-NEXT: .long .LBB0_3+1<br class="">+; CHECK-NEXT: .LBB0_3: @ %bb<br class="">+; CHECK-NEXT: @ in Loop: Header=BB0_1 Depth=1<br class="">+; CHECK-NEXT: cmp r0, #0<br class="">+; CHECK-NEXT: bne .LBB0_5<br class="">+; CHECK-NEXT: .LBB0_4: @ %bb2<br class="">+; CHECK-NEXT: @ in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: cmp r0, #0<br class=""> ; CHECK-NEXT: beq .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_6: @ %dead<br class="">+; CHECK-NEXT: .LBB0_5: @ %dead<br class=""> entry:<br class=""> br label %switch<br class=""><br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Thu Aug 22 09:21:32 2019<br class="">@@ -82,14 +82,14 @@ define i32 @test_loop_cold_blocks(i32 %i<br class=""> ; Check that we sink cold loop blocks after the hot loop body.<br class=""> ; CHECK-LABEL: test_loop_cold_blocks:<br class=""> ; CHECK: %entry<br class="">-; CHECK: .p2align<br class="">-; CHECK: %body1<br class="">-; CHECK: %body2<br class="">-; CHECK: %body3<br class=""> ; CHECK-NOT: .p2align<br class=""> ; CHECK: %unlikely1<br class=""> ; CHECK-NOT: .p2align<br class=""> ; CHECK: %unlikely2<br class="">+; CHECK: .p2align<br class="">+; CHECK: %body1<br class="">+; CHECK: %body2<br class="">+; CHECK: %body3<br class=""> ; CHECK: %exit<br class=""><br class=""> entry:<br class="">@@ -125,7 +125,7 @@ exit:<br class=""> ret i32 %sum<br class=""> }<br class=""><br class="">-!0 = !{!"branch_weights", i32 1, i32 64}<br class="">+!0 = !{!"branch_weights", i32 4, i32 64}<br class=""><br class=""> define i32 @test_loop_early_exits(i32 %i, i32* %a) {<br class=""> ; Check that we sink early exit blocks out of loop bodies.<br class="">@@ -189,8 +189,8 @@ define i32 @test_loop_rotate(i32 %i, i32<br class=""> ; loop, eliminating unconditional branches to the top.<br class=""> ; CHECK-LABEL: test_loop_rotate:<br class=""> ; CHECK: %entry<br class="">-; CHECK: %body0<br class=""> ; CHECK: %body1<br class="">+; CHECK: %body0<br class=""> ; CHECK: %exit<br class=""><br class=""> entry:<br class="">@@ -957,15 +957,16 @@ define void @benchmark_heapsort(i32 %n,<br class=""> ; CHECK: %if.else<br class=""> ; CHECK: %if.end10<br class=""> ; Second rotated loop top<br class="">+; CHECK: .p2align<br class="">+; CHECK: %if.then24<br class=""> ; CHECK: %while.cond.outer<br class=""> ; Third rotated loop top<br class=""> ; CHECK: .p2align<br class="">-; CHECK: %if.end20<br class=""> ; CHECK: %while.cond<br class=""> ; CHECK: %while.body<br class=""> ; CHECK: %land.lhs.true<br class=""> ; CHECK: %if.then19<br class="">-; CHECK: %if.then24<br class="">+; CHECK: %if.end20<br class=""> ; CHECK: %if.then8<br class=""> ; CHECK: ret<br class=""><br class="">@@ -1545,8 +1546,8 @@ define i32 @not_rotate_if_extra_branch_r<br class=""> ; CHECK-LABEL: not_rotate_if_extra_branch_regression<br class=""> ; CHECK: %.entry<br class=""> ; CHECK: %.first_backedge<br class="">-; CHECK: %.second_header<br class=""> ; CHECK: %.slow<br class="">+; CHECK: %.second_header<br class=""> .entry:<br class=""> %sum.0 = shl nsw i32 %count, 1<br class=""> br label %.first_header<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/code_placement.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/code_placement.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/code_placement.ll Thu Aug 22 09:21:32 2019<br class="">@@ -4,11 +4,6 @@<br class=""> @Te1 = external global [256 x i32]<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; <[256 x i32]*> [#uses=4]<br class=""> @Te3 = external global [256 x i32]<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; <[256 x i32]*> [#uses=2]<br class=""><br class="">-; CHECK: %entry<br class="">-; CHECK: %bb<br class="">-; CHECK: %bb1<br class="">-; CHECK: %bb2<br class="">-<br class=""> define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind ssp {<br class=""> entry:<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>%0 = load i32, i32* %rk, align 4<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; <i32> [#uses=1]<br class="">@@ -17,6 +12,8 @@ entry:<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>%tmp15 = add i32 %r, -1<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; <i32> [#uses=1]<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>%tmp.16 = zext i32 %tmp15 to i64<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; <i64> [#uses=2]<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>br label %bb<br class="">+; CHECK: jmp<br class="">+; CHECK-NEXT: align<br class=""><br class=""> bb:<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; preds = %bb1, %entry<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb1 ]<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>; <i64> [#uses=3]<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll Thu Aug 22 09:21:32 2019<br class="">@@ -1,12 +1,13 @@<br class=""> ; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s | FileCheck %s<br class=""><br class=""> define void @foo() {<br class="">-; After moving the latch to the top of loop, there is no fall through from the<br class="">-; latch to outer loop.<br class="">+; Test that when determining the edge probability from a node in an inner loop<br class="">+; to a node in an outer loop, the weights on edges in the inner loop should be<br class="">+; ignored if we are building the chain for the outer loop.<br class=""> ;<br class=""> ; CHECK-LABEL: foo:<br class="">-; CHECK: callq b<br class=""> ; CHECK: callq c<br class="">+; CHECK: callq b<br class=""><br class=""> entry:<br class=""> %call = call zeroext i1 @a()<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/code_placement_no_header_change.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement_no_header_change.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement_no_header_change.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/code_placement_no_header_change.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/code_placement_no_header_change.ll Thu Aug 22 09:21:32 2019<br class="">@@ -7,9 +7,9 @@ define i32 @bar(i32 %count) {<br class=""> ; Later backedge1 and backedge2 is rotated before loop header.<br class=""> ; CHECK-LABEL: bar<br class=""> ; CHECK: %.entry<br class="">-; CHECK: %.header<br class=""> ; CHECK: %.backedge1<br class=""> ; CHECK: %.backedge2<br class="">+; CHECK: %.header<br class=""> ; CHECK: %.exit<br class=""> .entry:<br class=""> %c = shl nsw i32 %count, 2<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/conditional-tailcall.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/conditional-tailcall.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/conditional-tailcall.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/conditional-tailcall.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/conditional-tailcall.ll Thu Aug 22 09:21:32 2019<br class="">@@ -258,12 +258,9 @@ define zeroext i1 @pr31257(%"class.std::<br class=""> ; CHECK32-NEXT: .cfi_adjust_cfa_offset -4<br class=""> ; CHECK32-NEXT: xorl %edi, %edi # encoding: [0x31,0xff]<br class=""> ; CHECK32-NEXT: incl %edi # encoding: [0x47]<br class="">-; CHECK32-NEXT: .LBB3_1: # %for.cond<br class="">-; CHECK32-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK32-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]<br class="">-; CHECK32-NEXT: je .LBB3_13 # encoding: [0x74,A]<br class="">-; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_13-1, kind: FK_PCRel_1<br class="">-; CHECK32-NEXT: # %bb.2: # %for.body<br class="">+; CHECK32-NEXT: jmp .LBB3_1 # encoding: [0xeb,A]<br class="">+; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_1-1, kind: FK_PCRel_1<br class="">+; CHECK32-NEXT: .LBB3_2: # %for.body<br class=""> ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1<br class=""> ; CHECK32-NEXT: cmpl $2, %ebx # encoding: [0x83,0xfb,0x02]<br class=""> ; CHECK32-NEXT: je .LBB3_11 # encoding: [0x74,A]<br class="">@@ -317,9 +314,12 @@ define zeroext i1 @pr31257(%"class.std::<br class=""> ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1<br class=""> ; CHECK32-NEXT: incl %eax # encoding: [0x40]<br class=""> ; CHECK32-NEXT: decl %edx # encoding: [0x4a]<br class="">-; CHECK32-NEXT: jmp .LBB3_1 # encoding: [0xeb,A]<br class="">-; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_1-1, kind: FK_PCRel_1<br class="">-; CHECK32-NEXT: .LBB3_13:<br class="">+; CHECK32-NEXT: .LBB3_1: # %for.cond<br class="">+; CHECK32-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK32-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]<br class="">+; CHECK32-NEXT: jne .LBB3_2 # encoding: [0x75,A]<br class="">+; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_2-1, kind: FK_PCRel_1<br class="">+; CHECK32-NEXT: # %bb.13:<br class=""> ; CHECK32-NEXT: cmpl $2, %ebx # encoding: [0x83,0xfb,0x02]<br class=""> ; CHECK32-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]<br class=""> ; CHECK32-NEXT: jmp .LBB3_14 # encoding: [0xeb,A]<br class="">@@ -369,59 +369,56 @@ define zeroext i1 @pr31257(%"class.std::<br class=""> ; CHECK64-NEXT: .cfi_adjust_cfa_offset 8<br class=""> ; CHECK64-NEXT: popq %r8 # encoding: [0x41,0x58]<br class=""> ; CHECK64-NEXT: .cfi_adjust_cfa_offset -8<br class="">-; CHECK64-NEXT: .LBB3_1: # %for.cond<br class="">-; CHECK64-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK64-NEXT: testq %rax, %rax # encoding: [0x48,0x85,0xc0]<br class="">-; CHECK64-NEXT: je .LBB3_12 # encoding: [0x74,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_12-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: # %bb.2: # %for.body<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: jmp .LBB3_11 # encoding: [0xeb,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: .LBB3_1: # %for.body<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: cmpl $2, %ecx # encoding: [0x83,0xf9,0x02]<br class="">-; CHECK64-NEXT: je .LBB3_10 # encoding: [0x74,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: # %bb.3: # %for.body<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: je .LBB3_9 # encoding: [0x74,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: # %bb.2: # %for.body<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: cmpl $1, %ecx # encoding: [0x83,0xf9,0x01]<br class="">-; CHECK64-NEXT: je .LBB3_8 # encoding: [0x74,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: # %bb.4: # %for.body<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: je .LBB3_7 # encoding: [0x74,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_7-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: # %bb.3: # %for.body<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: testl %ecx, %ecx # encoding: [0x85,0xc9]<br class="">-; CHECK64-NEXT: jne .LBB3_11 # encoding: [0x75,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: # %bb.5: # %sw.bb<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: jne .LBB3_10 # encoding: [0x75,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: # %bb.4: # %sw.bb<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: movzbl (%rdi), %edx # encoding: [0x0f,0xb6,0x17]<br class=""> ; CHECK64-NEXT: cmpl $43, %edx # encoding: [0x83,0xfa,0x2b]<br class=""> ; CHECK64-NEXT: movl %r8d, %ecx # encoding: [0x44,0x89,0xc1]<br class="">-; CHECK64-NEXT: je .LBB3_11 # encoding: [0x74,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: # %bb.6: # %sw.bb<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: je .LBB3_10 # encoding: [0x74,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: # %bb.5: # %sw.bb<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: cmpb $45, %dl # encoding: [0x80,0xfa,0x2d]<br class=""> ; CHECK64-NEXT: movl %r8d, %ecx # encoding: [0x44,0x89,0xc1]<br class="">-; CHECK64-NEXT: je .LBB3_11 # encoding: [0x74,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: # %bb.7: # %if.else<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: je .LBB3_10 # encoding: [0x74,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: # %bb.6: # %if.else<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: addl $-48, %edx # encoding: [0x83,0xc2,0xd0]<br class=""> ; CHECK64-NEXT: cmpl $10, %edx # encoding: [0x83,0xfa,0x0a]<br class="">-; CHECK64-NEXT: jmp .LBB3_9 # encoding: [0xeb,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: .LBB3_8: # %sw.bb14<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: jmp .LBB3_8 # encoding: [0xeb,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: .LBB3_7: # %sw.bb14<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: movzbl (%rdi), %ecx # encoding: [0x0f,0xb6,0x0f]<br class=""> ; CHECK64-NEXT: addl $-48, %ecx # encoding: [0x83,0xc1,0xd0]<br class=""> ; CHECK64-NEXT: cmpl $10, %ecx # encoding: [0x83,0xf9,0x0a]<br class="">-; CHECK64-NEXT: .LBB3_9: # %if.else<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: .LBB3_8: # %if.else<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: movl %r9d, %ecx # encoding: [0x44,0x89,0xc9]<br class="">-; CHECK64-NEXT: jb .LBB3_11 # encoding: [0x72,A]<br class="">-; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1<br class="">+; CHECK64-NEXT: jb .LBB3_10 # encoding: [0x72,A]<br class="">+; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class=""> ; CHECK64-NEXT: jmp .LBB3_13 # encoding: [0xeb,A]<br class=""> ; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_13-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: .LBB3_10: # %sw.bb22<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: .LBB3_9: # %sw.bb22<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: movzbl (%rdi), %ecx # encoding: [0x0f,0xb6,0x0f]<br class=""> ; CHECK64-NEXT: addl $-48, %ecx # encoding: [0x83,0xc1,0xd0]<br class=""> ; CHECK64-NEXT: cmpl $10, %ecx # encoding: [0x83,0xf9,0x0a]<br class="">@@ -429,13 +426,16 @@ define zeroext i1 @pr31257(%"class.std::<br class=""> ; CHECK64-NEXT: jae _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_ # TAILCALL<br class=""> ; CHECK64-NEXT: # encoding: [0x73,A]<br class=""> ; CHECK64-NEXT: # fixup A - offset: 1, value: _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: .LBB3_11: # %for.inc<br class="">-; CHECK64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; CHECK64-NEXT: .LBB3_10: # %for.inc<br class="">+; CHECK64-NEXT: # in Loop: Header=BB3_11 Depth=1<br class=""> ; CHECK64-NEXT: incq %rdi # encoding: [0x48,0xff,0xc7]<br class=""> ; CHECK64-NEXT: decq %rax # encoding: [0x48,0xff,0xc8]<br class="">-; CHECK64-NEXT: jmp .LBB3_1 # encoding: [0xeb,A]<br class="">+; CHECK64-NEXT: .LBB3_11: # %for.cond<br class="">+; CHECK64-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK64-NEXT: testq %rax, %rax # encoding: [0x48,0x85,0xc0]<br class="">+; CHECK64-NEXT: jne .LBB3_1 # encoding: [0x75,A]<br class=""> ; CHECK64-NEXT: # fixup A - offset: 1, value: .LBB3_1-1, kind: FK_PCRel_1<br class="">-; CHECK64-NEXT: .LBB3_12:<br class="">+; CHECK64-NEXT: # %bb.12:<br class=""> ; CHECK64-NEXT: cmpl $2, %ecx # encoding: [0x83,0xf9,0x02]<br class=""> ; CHECK64-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]<br class=""> ; CHECK64-NEXT: # kill: def $al killed $al killed $eax<br class="">@@ -451,54 +451,51 @@ define zeroext i1 @pr31257(%"class.std::<br class=""> ; WIN64-NEXT: movq -24(%rcx), %r8 # encoding: [0x4c,0x8b,0x41,0xe8]<br class=""> ; WIN64-NEXT: leaq (%rcx,%r8), %rdx # encoding: [0x4a,0x8d,0x14,0x01]<br class=""> ; WIN64-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]<br class="">-; WIN64-NEXT: .LBB3_1: # %for.cond<br class="">-; WIN64-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; WIN64-NEXT: testq %r8, %r8 # encoding: [0x4d,0x85,0xc0]<br class="">-; WIN64-NEXT: je .LBB3_11 # encoding: [0x74,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: # %bb.2: # %for.body<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: jmp .LBB3_10 # encoding: [0xeb,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: .LBB3_1: # %for.body<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: cmpl $2, %eax # encoding: [0x83,0xf8,0x02]<br class="">-; WIN64-NEXT: je .LBB3_9 # encoding: [0x74,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: # %bb.3: # %for.body<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: je .LBB3_8 # encoding: [0x74,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: # %bb.2: # %for.body<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: cmpl $1, %eax # encoding: [0x83,0xf8,0x01]<br class="">-; WIN64-NEXT: je .LBB3_7 # encoding: [0x74,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_7-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: # %bb.4: # %for.body<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: je .LBB3_6 # encoding: [0x74,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_6-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: # %bb.3: # %for.body<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]<br class="">-; WIN64-NEXT: jne .LBB3_10 # encoding: [0x75,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: # %bb.5: # %sw.bb<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: jne .LBB3_9 # encoding: [0x75,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: # %bb.4: # %sw.bb<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: movzbl (%rcx), %r9d # encoding: [0x44,0x0f,0xb6,0x09]<br class=""> ; WIN64-NEXT: cmpl $43, %r9d # encoding: [0x41,0x83,0xf9,0x2b]<br class=""> ; WIN64-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]<br class="">-; WIN64-NEXT: je .LBB3_10 # encoding: [0x74,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: # %bb.6: # %sw.bb<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: je .LBB3_9 # encoding: [0x74,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: # %bb.5: # %sw.bb<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: cmpb $45, %r9b # encoding: [0x41,0x80,0xf9,0x2d]<br class="">-; WIN64-NEXT: je .LBB3_10 # encoding: [0x74,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: jmp .LBB3_8 # encoding: [0xeb,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: .LBB3_7: # %sw.bb14<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: je .LBB3_9 # encoding: [0x74,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: jmp .LBB3_7 # encoding: [0xeb,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_7-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: .LBB3_6: # %sw.bb14<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: movzbl (%rcx), %r9d # encoding: [0x44,0x0f,0xb6,0x09]<br class="">-; WIN64-NEXT: .LBB3_8: # %if.else<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: .LBB3_7: # %if.else<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: addl $-48, %r9d # encoding: [0x41,0x83,0xc1,0xd0]<br class=""> ; WIN64-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]<br class=""> ; WIN64-NEXT: cmpl $10, %r9d # encoding: [0x41,0x83,0xf9,0x0a]<br class="">-; WIN64-NEXT: jb .LBB3_10 # encoding: [0x72,A]<br class="">-; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1<br class="">+; WIN64-NEXT: jb .LBB3_9 # encoding: [0x72,A]<br class="">+; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1<br class=""> ; WIN64-NEXT: jmp .LBB3_12 # encoding: [0xeb,A]<br class=""> ; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_12-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: .LBB3_9: # %sw.bb22<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: .LBB3_8: # %sw.bb22<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: movzbl (%rcx), %r9d # encoding: [0x44,0x0f,0xb6,0x09]<br class=""> ; WIN64-NEXT: addl $-48, %r9d # encoding: [0x41,0x83,0xc1,0xd0]<br class=""> ; WIN64-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]<br class="">@@ -506,13 +503,16 @@ define zeroext i1 @pr31257(%"class.std::<br class=""> ; WIN64-NEXT: jae _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_ # TAILCALL<br class=""> ; WIN64-NEXT: # encoding: [0x73,A]<br class=""> ; WIN64-NEXT: # fixup A - offset: 1, value: _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: .LBB3_10: # %for.inc<br class="">-; WIN64-NEXT: # in Loop: Header=BB3_1 Depth=1<br class="">+; WIN64-NEXT: .LBB3_9: # %for.inc<br class="">+; WIN64-NEXT: # in Loop: Header=BB3_10 Depth=1<br class=""> ; WIN64-NEXT: incq %rcx # encoding: [0x48,0xff,0xc1]<br class=""> ; WIN64-NEXT: decq %r8 # encoding: [0x49,0xff,0xc8]<br class="">-; WIN64-NEXT: jmp .LBB3_1 # encoding: [0xeb,A]<br class="">+; WIN64-NEXT: .LBB3_10: # %for.cond<br class="">+; WIN64-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; WIN64-NEXT: testq %r8, %r8 # encoding: [0x4d,0x85,0xc0]<br class="">+; WIN64-NEXT: jne .LBB3_1 # encoding: [0x75,A]<br class=""> ; WIN64-NEXT: # fixup A - offset: 1, value: .LBB3_1-1, kind: FK_PCRel_1<br class="">-; WIN64-NEXT: .LBB3_11:<br class="">+; WIN64-NEXT: # %bb.11:<br class=""> ; WIN64-NEXT: cmpl $2, %eax # encoding: [0x83,0xf8,0x02]<br class=""> ; WIN64-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]<br class=""> ; WIN64-NEXT: # kill: def $al killed $al killed $eax<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/loop-blocks.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-blocks.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-blocks.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/loop-blocks.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/loop-blocks.ll Thu Aug 22 09:21:32 2019<br class="">@@ -7,14 +7,12 @@<br class=""> ; order to avoid a branch within the loop.<br class=""><br class=""> ; CHECK-LABEL: simple:<br class="">-; CHECK: align<br class="">+; CHECK: jmp .LBB0_1<br class="">+; CHECK-NEXT: align<br class="">+; CHECK-NEXT: .LBB0_2:<br class="">+; CHECK-NEXT: callq loop_latch<br class=""> ; CHECK-NEXT: .LBB0_1:<br class=""> ; CHECK-NEXT: callq loop_header<br class="">-; CHECK: js .LBB0_3<br class="">-; CHECK-NEXT: callq loop_latch<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3:<br class="">-; CHECK-NEXT: callq exit<br class=""><br class=""> define void @simple() nounwind {<br class=""> entry:<br class="">@@ -77,21 +75,17 @@ exit:<br class=""> ; CHECK-LABEL: yet_more_involved:<br class=""> ; CHECK: jmp .LBB2_1<br class=""> ; CHECK-NEXT: align<br class="">-<br class="">-; CHECK: .LBB2_1:<br class="">+; CHECK-NEXT: .LBB2_5:<br class="">+; CHECK-NEXT: callq block_a_true_func<br class="">+; CHECK-NEXT: callq block_a_merge_func<br class="">+; CHECK-NEXT: .LBB2_1:<br class=""> ; CHECK-NEXT: callq body<br class="">-; CHECK-NEXT: callq get<br class="">-; CHECK-NEXT: cmpl $2, %eax<br class="">-; CHECK-NEXT: jge .LBB2_2<br class="">-; CHECK-NEXT: callq bar99<br class="">+;<br class="">+; LBB2_4<br class="">+; CHECK: callq bar99<br class=""> ; CHECK-NEXT: callq get<br class=""> ; CHECK-NEXT: cmpl $2999, %eax<br class="">-; CHECK-NEXT: jg .LBB2_6<br class="">-; CHECK-NEXT: callq block_a_true_func<br class="">-; CHECK-NEXT: callq block_a_merge_func<br class="">-; CHECK-NEXT: jmp .LBB2_1<br class="">-; CHECK-NEXT: align<br class="">-; CHECK-NEXT: .LBB2_6:<br class="">+; CHECK-NEXT: jle .LBB2_5<br class=""> ; CHECK-NEXT: callq block_a_false_func<br class=""> ; CHECK-NEXT: callq block_a_merge_func<br class=""> ; CHECK-NEXT: jmp .LBB2_1<br class="">@@ -207,12 +201,12 @@ block102:<br class=""> }<br class=""><br class=""> ; CHECK-LABEL: check_minsize:<br class="">+; CHECK: jmp .LBB4_1<br class=""> ; CHECK-NOT: align<br class="">-; CHECK: .LBB4_1:<br class="">+; CHECK-NEXT: .LBB4_2:<br class="">+; CHECK-NEXT: callq loop_latch<br class="">+; CHECK-NEXT: .LBB4_1:<br class=""> ; CHECK-NEXT: callq loop_header<br class="">-; CHECK: callq loop_latch<br class="">-; CHECK: .LBB4_3:<br class="">-; CHECK: callq exit<br class=""><br class=""><br class=""> define void @check_minsize() minsize nounwind {<br class=""><br class="">Removed: llvm/trunk/test/CodeGen/X86/loop-rotate.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-rotate.ll?rev=369663&view=auto" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-rotate.ll?rev=369663&view=auto</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/loop-rotate.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/loop-rotate.ll (removed)<br class="">@@ -1,120 +0,0 @@<br class="">-; RUN: llc -mtriple=i686-linux < %s | FileCheck %s<br class="">-<br class="">-; Don't rotate the loop if the number of fall through to exit is not larger<br class="">-; than the number of fall through to header.<br class="">-define void @no_rotate() {<br class="">-; CHECK-LABEL: no_rotate<br class="">-; CHECK: %entry<br class="">-; CHECK: %header<br class="">-; CHECK: %middle<br class="">-; CHECK: %latch1<br class="">-; CHECK: %latch2<br class="">-; CHECK: %end<br class="">-entry:<br class="">- br label %header<br class="">-<br class="">-header:<br class="">- %val1 = call i1 @foo()<br class="">- br i1 %val1, label %middle, label %end<br class="">-<br class="">-middle:<br class="">- %val2 = call i1 @foo()<br class="">- br i1 %val2, label %latch1, label %end<br class="">-<br class="">-latch1:<br class="">- %val3 = call i1 @foo()<br class="">- br i1 %val3, label %latch2, label %header<br class="">-<br class="">-latch2:<br class="">- %val4 = call i1 @foo()<br class="">- br label %header<br class="">-<br class="">-end:<br class="">- ret void<br class="">-}<br class="">-<br class="">-define void @do_rotate() {<br class="">-; CHECK-LABEL: do_rotate<br class="">-; CHECK: %entry<br class="">-; CHECK: %then<br class="">-; CHECK: %else<br class="">-; CHECK: %latch1<br class="">-; CHECK: %latch2<br class="">-; CHECK: %header<br class="">-; CHECK: %end<br class="">-entry:<br class="">- %val0 = call i1 @foo()<br class="">- br i1 %val0, label %then, label %else<br class="">-<br class="">-then:<br class="">- call void @a()<br class="">- br label %header<br class="">-<br class="">-else:<br class="">- call void @b()<br class="">- br label %header<br class="">-<br class="">-header:<br class="">- %val1 = call i1 @foo()<br class="">- br i1 %val1, label %latch1, label %end<br class="">-<br class="">-latch1:<br class="">- %val3 = call i1 @foo()<br class="">- br i1 %val3, label %latch2, label %header<br class="">-<br class="">-latch2:<br class="">- %val4 = call i1 @foo()<br class="">- br label %header<br class="">-<br class="">-end:<br class="">- ret void<br class="">-}<br class="">-<br class="">-; The loop structure is same as in @no_rotate, but the loop header's predecessor<br class="">-; doesn't fall through to it, so it should be rotated to get exit fall through.<br class="">-define void @do_rotate2() {<br class="">-; CHECK-LABEL: do_rotate2<br class="">-; CHECK: %entry<br class="">-; CHECK: %then<br class="">-; CHECK: %middle<br class="">-; CHECK: %latch1<br class="">-; CHECK: %latch2<br class="">-; CHECK: %header<br class="">-; CHECK: %exit<br class="">-entry:<br class="">- %val0 = call i1 @foo()<br class="">- br i1 %val0, label %then, label %header, !prof !1<br class="">-<br class="">-then:<br class="">- call void @a()<br class="">- br label %end<br class="">-<br class="">-header:<br class="">- %val1 = call i1 @foo()<br class="">- br i1 %val1, label %middle, label %exit<br class="">-<br class="">-middle:<br class="">- %val2 = call i1 @foo()<br class="">- br i1 %val2, label %latch1, label %exit<br class="">-<br class="">-latch1:<br class="">- %val3 = call i1 @foo()<br class="">- br i1 %val3, label %latch2, label %header<br class="">-<br class="">-latch2:<br class="">- %val4 = call i1 @foo()<br class="">- br label %header<br class="">-<br class="">-exit:<br class="">- call void @b()<br class="">- br label %end<br class="">-<br class="">-end:<br class="">- ret void<br class="">-}<br class="">-<br class="">-declare i1 @foo()<br class="">-declare void @a()<br class="">-declare void @b()<br class="">-<br class="">-!1 = !{!"branch_weights", i32 10, i32 1}<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll Thu Aug 22 09:21:32 2019<br class="">@@ -21,7 +21,22 @@ define void @t(i8* nocapture %in, i8* no<br class=""> ; GENERIC-NEXT: movq _Te1@{{.*}}(%rip), %r8<br class=""> ; GENERIC-NEXT: movq _Te3@{{.*}}(%rip), %r10<br class=""> ; GENERIC-NEXT: movq %rcx, %r11<br class="">+; GENERIC-NEXT: jmp LBB0_1<br class=""> ; GENERIC-NEXT: .p2align 4, 0x90<br class="">+; GENERIC-NEXT: LBB0_2: ## %bb1<br class="">+; GENERIC-NEXT: ## in Loop: Header=BB0_1 Depth=1<br class="">+; GENERIC-NEXT: movl %edi, %ebx<br class="">+; GENERIC-NEXT: shrl $16, %ebx<br class="">+; GENERIC-NEXT: movzbl %bl, %ebx<br class="">+; GENERIC-NEXT: xorl (%r8,%rbx,4), %eax<br class="">+; GENERIC-NEXT: xorl -4(%r14), %eax<br class="">+; GENERIC-NEXT: shrl $24, %edi<br class="">+; GENERIC-NEXT: movzbl %bpl, %ebx<br class="">+; GENERIC-NEXT: movl (%r10,%rbx,4), %ebx<br class="">+; GENERIC-NEXT: xorl (%r9,%rdi,4), %ebx<br class="">+; GENERIC-NEXT: xorl (%r14), %ebx<br class="">+; GENERIC-NEXT: decq %r11<br class="">+; GENERIC-NEXT: addq $16, %r14<br class=""> ; GENERIC-NEXT: LBB0_1: ## %bb<br class=""> ; GENERIC-NEXT: ## =>This Inner Loop Header: Depth=1<br class=""> ; GENERIC-NEXT: movzbl %al, %edi<br class="">@@ -41,23 +56,8 @@ define void @t(i8* nocapture %in, i8* no<br class=""> ; GENERIC-NEXT: shrl $24, %eax<br class=""> ; GENERIC-NEXT: movl (%r9,%rax,4), %eax<br class=""> ; GENERIC-NEXT: testq %r11, %r11<br class="">-; GENERIC-NEXT: je LBB0_3<br class="">-; GENERIC-NEXT: ## %bb.2: ## %bb1<br class="">-; GENERIC-NEXT: ## in Loop: Header=BB0_1 Depth=1<br class="">-; GENERIC-NEXT: movl %edi, %ebx<br class="">-; GENERIC-NEXT: shrl $16, %ebx<br class="">-; GENERIC-NEXT: movzbl %bl, %ebx<br class="">-; GENERIC-NEXT: xorl (%r8,%rbx,4), %eax<br class="">-; GENERIC-NEXT: xorl -4(%r14), %eax<br class="">-; GENERIC-NEXT: shrl $24, %edi<br class="">-; GENERIC-NEXT: movzbl %bpl, %ebx<br class="">-; GENERIC-NEXT: movl (%r10,%rbx,4), %ebx<br class="">-; GENERIC-NEXT: xorl (%r9,%rdi,4), %ebx<br class="">-; GENERIC-NEXT: xorl (%r14), %ebx<br class="">-; GENERIC-NEXT: decq %r11<br class="">-; GENERIC-NEXT: addq $16, %r14<br class="">-; GENERIC-NEXT: jmp LBB0_1<br class="">-; GENERIC-NEXT: LBB0_3: ## %bb2<br class="">+; GENERIC-NEXT: jne LBB0_2<br class="">+; GENERIC-NEXT: ## %bb.3: ## %bb2<br class=""> ; GENERIC-NEXT: shlq $4, %rcx<br class=""> ; GENERIC-NEXT: andl $-16777216, %eax ## imm = 0xFF000000<br class=""> ; GENERIC-NEXT: movl %edi, %ebx<br class="">@@ -105,7 +105,21 @@ define void @t(i8* nocapture %in, i8* no<br class=""> ; ATOM-NEXT: movq _Te3@{{.*}}(%rip), %r10<br class=""> ; ATOM-NEXT: decl %ecx<br class=""> ; ATOM-NEXT: movq %rcx, %r11<br class="">+; ATOM-NEXT: jmp LBB0_1<br class=""> ; ATOM-NEXT: .p2align 4, 0x90<br class="">+; ATOM-NEXT: LBB0_2: ## %bb1<br class="">+; ATOM-NEXT: ## in Loop: Header=BB0_1 Depth=1<br class="">+; ATOM-NEXT: shrl $16, %eax<br class="">+; ATOM-NEXT: shrl $24, %edi<br class="">+; ATOM-NEXT: decq %r11<br class="">+; ATOM-NEXT: movzbl %al, %ebp<br class="">+; ATOM-NEXT: movzbl %bl, %eax<br class="">+; ATOM-NEXT: movl (%r10,%rax,4), %eax<br class="">+; ATOM-NEXT: xorl (%r8,%rbp,4), %r15d<br class="">+; ATOM-NEXT: xorl (%r9,%rdi,4), %eax<br class="">+; ATOM-NEXT: xorl -4(%r14), %r15d<br class="">+; ATOM-NEXT: xorl (%r14), %eax<br class="">+; ATOM-NEXT: addq $16, %r14<br class=""> ; ATOM-NEXT: LBB0_1: ## %bb<br class=""> ; ATOM-NEXT: ## =>This Inner Loop Header: Depth=1<br class=""> ; ATOM-NEXT: movl %eax, %edi<br class="">@@ -126,22 +140,8 @@ define void @t(i8* nocapture %in, i8* no<br class=""> ; ATOM-NEXT: movl (%r9,%rax,4), %r15d<br class=""> ; ATOM-NEXT: testq %r11, %r11<br class=""> ; ATOM-NEXT: movl %edi, %eax<br class="">-; ATOM-NEXT: je LBB0_3<br class="">-; ATOM-NEXT: ## %bb.2: ## %bb1<br class="">-; ATOM-NEXT: ## in Loop: Header=BB0_1 Depth=1<br class="">-; ATOM-NEXT: shrl $16, %eax<br class="">-; ATOM-NEXT: shrl $24, %edi<br class="">-; ATOM-NEXT: decq %r11<br class="">-; ATOM-NEXT: movzbl %al, %ebp<br class="">-; ATOM-NEXT: movzbl %bl, %eax<br class="">-; ATOM-NEXT: movl (%r10,%rax,4), %eax<br class="">-; ATOM-NEXT: xorl (%r8,%rbp,4), %r15d<br class="">-; ATOM-NEXT: xorl (%r9,%rdi,4), %eax<br class="">-; ATOM-NEXT: xorl -4(%r14), %r15d<br class="">-; ATOM-NEXT: xorl (%r14), %eax<br class="">-; ATOM-NEXT: addq $16, %r14<br class="">-; ATOM-NEXT: jmp LBB0_1<br class="">-; ATOM-NEXT: LBB0_3: ## %bb2<br class="">+; ATOM-NEXT: jne LBB0_2<br class="">+; ATOM-NEXT: ## %bb.3: ## %bb2<br class=""> ; ATOM-NEXT: shrl $16, %eax<br class=""> ; ATOM-NEXT: shrl $8, %edi<br class=""> ; ATOM-NEXT: movzbl %bl, %ebp<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/move_latch_to_loop_top.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/move_latch_to_loop_top.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/move_latch_to_loop_top.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/move_latch_to_loop_top.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/move_latch_to_loop_top.ll Thu Aug 22 09:21:32 2019<br class="">@@ -1,11 +1,11 @@<br class="">-; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s | FileCheck %s<br class="">+; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux --force-precise-rotation-cost < %s | FileCheck %s<br class=""><br class=""> ; The block latch should be moved before header.<br class=""> ;CHECK-LABEL: test1:<br class=""> ;CHECK: %latch<br class=""> ;CHECK: %header<br class=""> ;CHECK: %false<br class="">-define i32 @test1(i32* %p) {<br class="">+define i32 @test1(i32* %p) !prof !0 {<br class=""> entry:<br class=""> br label %header<br class=""><br class="">@@ -39,7 +39,7 @@ exit:<br class=""> ;CHECK: %latch<br class=""> ;CHECK: %header<br class=""> ;CHECK: %false<br class="">-define i32 @test2(i32* %p) {<br class="">+define i32 @test2(i32* %p) !prof !0 {<br class=""> entry:<br class=""> br label %header<br class=""><br class="">@@ -107,7 +107,7 @@ exit:<br class=""> ;CHECK: %latch<br class=""> ;CHECK: %header<br class=""> ;CHECK: %false<br class="">-define i32 @test3(i32* %p) {<br class="">+define i32 @test3(i32* %p) !prof !0 {<br class=""> entry:<br class=""> br label %header<br class=""><br class="">@@ -173,9 +173,9 @@ exit:<br class=""> ;CHECK: %header<br class=""> ;CHECK: %true<br class=""> ;CHECK: %latch<br class="">-;CHECK: %false<br class=""> ;CHECK: %exit<br class="">-define i32 @test4(i32 %t, i32* %p) {<br class="">+;CHECK: %false<br class="">+define i32 @test4(i32 %t, i32* %p) !prof !0 {<br class=""> entry:<br class=""> br label %header<br class=""><br class="">@@ -207,6 +207,7 @@ exit:<br class=""> ret i32 %count4<br class=""> }<br class=""><br class="">+!0 = !{!"function_entry_count", i32 1000}<br class=""> !1 = !{!"branch_weights", i32 100, i32 1}<br class=""> !2 = !{!"branch_weights", i32 16, i32 16}<br class=""> !3 = !{!"branch_weights", i32 51, i32 49}<br class="">@@ -216,7 +217,7 @@ exit:<br class=""> ;CHECK: %entry<br class=""> ;CHECK: %header<br class=""> ;CHECK: %latch<br class="">-define void @test5(i32* %p) {<br class="">+define void @test5(i32* %p) !prof !0 {<br class=""> entry:<br class=""> br label %header<br class=""><br class="">@@ -236,4 +237,3 @@ latch:<br class=""> exit:<br class=""> ret void<br class=""> }<br class="">-<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/pr38185.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38185.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38185.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/pr38185.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/pr38185.ll Thu Aug 22 09:21:32 2019<br class="">@@ -5,13 +5,9 @@ define void @foo(i32* %a, i32* %b, i32*<br class=""> ; CHECK-LABEL: foo:<br class=""> ; CHECK: # %bb.0:<br class=""> ; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)<br class="">+; CHECK-NEXT: jmp .LBB0_1<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_1: # %loop<br class="">-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %r9<br class="">-; CHECK-NEXT: cmpq %rcx, %r9<br class="">-; CHECK-NEXT: je .LBB0_3<br class="">-; CHECK-NEXT: # %bb.2: # %body<br class="">+; CHECK-NEXT: .LBB0_2: # %body<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movl $1, (%rdx,%r9,4)<br class=""> ; CHECK-NEXT: movzbl (%rdi,%r9,4), %r8d<br class="">@@ -21,8 +17,12 @@ define void @foo(i32* %a, i32* %b, i32*<br class=""> ; CHECK-NEXT: movl %eax, (%rdi,%r9,4)<br class=""> ; CHECK-NEXT: incq %r9<br class=""> ; CHECK-NEXT: movq %r9, -{{[0-9]+}}(%rsp)<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3: # %endloop<br class="">+; CHECK-NEXT: .LBB0_1: # %loop<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %r9<br class="">+; CHECK-NEXT: cmpq %rcx, %r9<br class="">+; CHECK-NEXT: jne .LBB0_2<br class="">+; CHECK-NEXT: # %bb.3: # %endloop<br class=""> ; CHECK-NEXT: retq<br class=""> %i = alloca i64<br class=""> store i64 0, i64* %i<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll Thu Aug 22 09:21:32 2019<br class="">@@ -103,34 +103,6 @@ define i8* @SyFgets(i8* %line, i64 %leng<br class=""> ; CHECK-NEXT: xorl %r13d, %r13d<br class=""> ; CHECK-NEXT: jmp LBB0_13<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: LBB0_20: ## %sw.bb256<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: movl %r14d, %r13d<br class="">-; CHECK-NEXT: LBB0_21: ## %while.cond197.backedge<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: decl %r15d<br class="">-; CHECK-NEXT: testl %r15d, %r15d<br class="">-; CHECK-NEXT: movl %r13d, %r14d<br class="">-; CHECK-NEXT: jle LBB0_22<br class="">-; CHECK-NEXT: LBB0_13: ## %while.body200<br class="">-; CHECK-NEXT: ## =>This Loop Header: Depth=1<br class="">-; CHECK-NEXT: ## Child Loop BB0_30 Depth 2<br class="">-; CHECK-NEXT: ## Child Loop BB0_38 Depth 2<br class="">-; CHECK-NEXT: leal -268(%r14), %eax<br class="">-; CHECK-NEXT: cmpl $105, %eax<br class="">-; CHECK-NEXT: ja LBB0_14<br class="">-; CHECK-NEXT: ## %bb.56: ## %while.body200<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: movslq (%rdi,%rax,4), %rax<br class="">-; CHECK-NEXT: addq %rdi, %rax<br class="">-; CHECK-NEXT: jmpq *%rax<br class="">-; CHECK-NEXT: LBB0_44: ## %while.cond1037.preheader<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: testb %dl, %dl<br class="">-; CHECK-NEXT: movl %r14d, %r13d<br class="">-; CHECK-NEXT: jne LBB0_21<br class="">-; CHECK-NEXT: jmp LBB0_55<br class="">-; CHECK-NEXT: .p2align 4, 0x90<br class=""> ; CHECK-NEXT: LBB0_14: ## %while.body200<br class=""> ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class=""> ; CHECK-NEXT: leal 1(%r14), %eax<br class="">@@ -146,6 +118,12 @@ define i8* @SyFgets(i8* %line, i64 %leng<br class=""> ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class=""> ; CHECK-NEXT: movl $1, %r13d<br class=""> ; CHECK-NEXT: jmp LBB0_21<br class="">+; CHECK-NEXT: LBB0_44: ## %while.cond1037.preheader<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: testb %dl, %dl<br class="">+; CHECK-NEXT: movl %r14d, %r13d<br class="">+; CHECK-NEXT: jne LBB0_21<br class="">+; CHECK-NEXT: jmp LBB0_55<br class=""> ; CHECK-NEXT: LBB0_26: ## %sw.bb474<br class=""> ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class=""> ; CHECK-NEXT: testb %dl, %dl<br class="">@@ -159,52 +137,30 @@ define i8* @SyFgets(i8* %line, i64 %leng<br class=""> ; CHECK-NEXT: ## %bb.28: ## %land.rhs485.preheader<br class=""> ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class=""> ; CHECK-NEXT: ## implicit-def: $rax<br class="">-; CHECK-NEXT: testb %al, %al<br class="">-; CHECK-NEXT: jns LBB0_30<br class="">-; CHECK-NEXT: jmp LBB0_55<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: LBB0_32: ## %do.body479.backedge<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_30 Depth=2<br class="">-; CHECK-NEXT: leaq 1(%r12), %rax<br class="">-; CHECK-NEXT: testb %dl, %dl<br class="">-; CHECK-NEXT: je LBB0_33<br class="">-; CHECK-NEXT: ## %bb.29: ## %land.rhs485<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_30 Depth=2<br class="">-; CHECK-NEXT: testb %al, %al<br class="">-; CHECK-NEXT: js LBB0_55<br class="">-; CHECK-NEXT: LBB0_30: ## %cond.true.i.i2780<br class="">+; CHECK-NEXT: LBB0_29: ## %land.rhs485<br class=""> ; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1<br class=""> ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2<br class="">+; CHECK-NEXT: testb %al, %al<br class="">+; CHECK-NEXT: js LBB0_55<br class="">+; CHECK-NEXT: ## %bb.30: ## %cond.true.i.i2780<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2<br class=""> ; CHECK-NEXT: movq %rax, %r12<br class=""> ; CHECK-NEXT: testb %dl, %dl<br class=""> ; CHECK-NEXT: jne LBB0_32<br class=""> ; CHECK-NEXT: ## %bb.31: ## %lor.rhs500<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_30 Depth=2<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2<br class=""> ; CHECK-NEXT: movl $256, %esi ## imm = 0x100<br class=""> ; CHECK-NEXT: callq ___maskrune<br class=""> ; CHECK-NEXT: xorl %edx, %edx<br class=""> ; CHECK-NEXT: testb %dl, %dl<br class="">-; CHECK-NEXT: jne LBB0_32<br class="">-; CHECK-NEXT: jmp LBB0_34<br class="">-; CHECK-NEXT: LBB0_45: ## %sw.bb1134<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax<br class="">-; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx<br class="">-; CHECK-NEXT: cmpq %rax, %rcx<br class="">-; CHECK-NEXT: jb LBB0_55<br class="">-; CHECK-NEXT: ## %bb.46: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: xorl %ebp, %ebp<br class="">-; CHECK-NEXT: movl $268, %r13d ## imm = 0x10C<br class="">-; CHECK-NEXT: jmp LBB0_21<br class="">-; CHECK-NEXT: LBB0_19: ## %sw.bb243<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: movl $2, %r13d<br class="">-; CHECK-NEXT: jmp LBB0_21<br class="">-; CHECK-NEXT: LBB0_40: ## %sw.bb566<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">-; CHECK-NEXT: movl $20, %r13d<br class="">-; CHECK-NEXT: jmp LBB0_21<br class="">-; CHECK-NEXT: LBB0_33: ## %if.end517.loopexitsplit<br class="">+; CHECK-NEXT: je LBB0_34<br class="">+; CHECK-NEXT: LBB0_32: ## %do.body479.backedge<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_29 Depth=2<br class="">+; CHECK-NEXT: leaq 1(%r12), %rax<br class="">+; CHECK-NEXT: testb %dl, %dl<br class="">+; CHECK-NEXT: jne LBB0_29<br class="">+; CHECK-NEXT: ## %bb.33: ## %if.end517.loopexitsplit<br class=""> ; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class=""> ; CHECK-NEXT: incq %r12<br class=""> ; CHECK-NEXT: LBB0_34: ## %if.end517<br class="">@@ -243,6 +199,47 @@ define i8* @SyFgets(i8* %line, i64 %leng<br class=""> ; CHECK-NEXT: leaq {{.*}}(%rip), %rsi<br class=""> ; CHECK-NEXT: leaq {{.*}}(%rip), %rdi<br class=""> ; CHECK-NEXT: jmp LBB0_21<br class="">+; CHECK-NEXT: LBB0_45: ## %sw.bb1134<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax<br class="">+; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx<br class="">+; CHECK-NEXT: cmpq %rax, %rcx<br class="">+; CHECK-NEXT: jb LBB0_55<br class="">+; CHECK-NEXT: ## %bb.46: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: xorl %ebp, %ebp<br class="">+; CHECK-NEXT: movl $268, %r13d ## imm = 0x10C<br class="">+; CHECK-NEXT: jmp LBB0_21<br class="">+; CHECK-NEXT: LBB0_19: ## %sw.bb243<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: movl $2, %r13d<br class="">+; CHECK-NEXT: jmp LBB0_21<br class="">+; CHECK-NEXT: LBB0_40: ## %sw.bb566<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: movl $20, %r13d<br class="">+; CHECK-NEXT: jmp LBB0_21<br class="">+; CHECK-NEXT: .p2align 4, 0x90<br class="">+; CHECK-NEXT: LBB0_13: ## %while.body200<br class="">+; CHECK-NEXT: ## =>This Loop Header: Depth=1<br class="">+; CHECK-NEXT: ## Child Loop BB0_29 Depth 2<br class="">+; CHECK-NEXT: ## Child Loop BB0_38 Depth 2<br class="">+; CHECK-NEXT: leal -268(%r14), %eax<br class="">+; CHECK-NEXT: cmpl $105, %eax<br class="">+; CHECK-NEXT: ja LBB0_14<br class="">+; CHECK-NEXT: ## %bb.56: ## %while.body200<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: movslq (%rdi,%rax,4), %rax<br class="">+; CHECK-NEXT: addq %rdi, %rax<br class="">+; CHECK-NEXT: jmpq *%rax<br class="">+; CHECK-NEXT: LBB0_20: ## %sw.bb256<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: movl %r14d, %r13d<br class="">+; CHECK-NEXT: LBB0_21: ## %while.cond197.backedge<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1<br class="">+; CHECK-NEXT: decl %r15d<br class="">+; CHECK-NEXT: testl %r15d, %r15d<br class="">+; CHECK-NEXT: movl %r13d, %r14d<br class="">+; CHECK-NEXT: jg LBB0_13<br class="">+; CHECK-NEXT: jmp LBB0_22<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class=""> ; CHECK-NEXT: LBB0_42: ## %while.cond864<br class=""> ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/reverse_branches.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/reverse_branches.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/reverse_branches.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/reverse_branches.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/reverse_branches.ll Thu Aug 22 09:21:32 2019<br class="">@@ -85,36 +85,25 @@ define i32 @test_branches_order() uwtabl<br class=""> ; CHECK-NEXT: jg LBB0_16<br class=""> ; CHECK-NEXT: LBB0_9: ## %for.cond18.preheader<br class=""> ; CHECK-NEXT: ## =>This Loop Header: Depth=1<br class="">-; CHECK-NEXT: ## Child Loop BB0_11 Depth 2<br class="">+; CHECK-NEXT: ## Child Loop BB0_10 Depth 2<br class=""> ; CHECK-NEXT: ## Child Loop BB0_12 Depth 3<br class=""> ; CHECK-NEXT: movq %rcx, %rdx<br class=""> ; CHECK-NEXT: xorl %esi, %esi<br class=""> ; CHECK-NEXT: xorl %edi, %edi<br class="">-; CHECK-NEXT: cmpl $999, %edi ## imm = 0x3E7<br class="">-; CHECK-NEXT: jle LBB0_11<br class="">-; CHECK-NEXT: jmp LBB0_15<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: LBB0_14: ## %exit<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_11 Depth=2<br class="">-; CHECK-NEXT: addq %rsi, %rbp<br class="">-; CHECK-NEXT: incq %rdi<br class="">-; CHECK-NEXT: decq %rsi<br class="">-; CHECK-NEXT: addq $1001, %rdx ## imm = 0x3E9<br class="">-; CHECK-NEXT: cmpq $-1000, %rbp ## imm = 0xFC18<br class="">-; CHECK-NEXT: jne LBB0_5<br class="">-; CHECK-NEXT: ## %bb.10: ## %for.cond18<br class="">-; CHECK-NEXT: ## in Loop: Header=BB0_11 Depth=2<br class="">-; CHECK-NEXT: cmpl $999, %edi ## imm = 0x3E7<br class="">-; CHECK-NEXT: jg LBB0_15<br class="">-; CHECK-NEXT: LBB0_11: ## %for.body20<br class="">+; CHECK-NEXT: LBB0_10: ## %for.cond18<br class=""> ; CHECK-NEXT: ## Parent Loop BB0_9 Depth=1<br class=""> ; CHECK-NEXT: ## => This Loop Header: Depth=2<br class=""> ; CHECK-NEXT: ## Child Loop BB0_12 Depth 3<br class="">+; CHECK-NEXT: cmpl $999, %edi ## imm = 0x3E7<br class="">+; CHECK-NEXT: jg LBB0_15<br class="">+; CHECK-NEXT: ## %bb.11: ## %for.body20<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2<br class=""> ; CHECK-NEXT: movq $-1000, %rbp ## imm = 0xFC18<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class=""> ; CHECK-NEXT: LBB0_12: ## %do.body.i<br class=""> ; CHECK-NEXT: ## Parent Loop BB0_9 Depth=1<br class="">-; CHECK-NEXT: ## Parent Loop BB0_11 Depth=2<br class="">+; CHECK-NEXT: ## Parent Loop BB0_10 Depth=2<br class=""> ; CHECK-NEXT: ## => This Inner Loop Header: Depth=3<br class=""> ; CHECK-NEXT: cmpb $120, 1000(%rdx,%rbp)<br class=""> ; CHECK-NEXT: je LBB0_14<br class="">@@ -122,6 +111,16 @@ define i32 @test_branches_order() uwtabl<br class=""> ; CHECK-NEXT: ## in Loop: Header=BB0_12 Depth=3<br class=""> ; CHECK-NEXT: incq %rbp<br class=""> ; CHECK-NEXT: jne LBB0_12<br class="">+; CHECK-NEXT: jmp LBB0_5<br class="">+; CHECK-NEXT: .p2align 4, 0x90<br class="">+; CHECK-NEXT: LBB0_14: ## %exit<br class="">+; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2<br class="">+; CHECK-NEXT: addq %rsi, %rbp<br class="">+; CHECK-NEXT: incq %rdi<br class="">+; CHECK-NEXT: decq %rsi<br class="">+; CHECK-NEXT: addq $1001, %rdx ## imm = 0x3E9<br class="">+; CHECK-NEXT: cmpq $-1000, %rbp ## imm = 0xFC18<br class="">+; CHECK-NEXT: je LBB0_10<br class=""> ; CHECK-NEXT: LBB0_5: ## %if.then<br class=""> ; CHECK-NEXT: leaq {{.*}}(%rip), %rdi<br class=""> ; CHECK-NEXT: callq _puts<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll Thu Aug 22 09:21:32 2019<br class="">@@ -215,7 +215,10 @@ define void @test_basic_loop(i32 %a, i32<br class=""> ; X64-NEXT: movl %esi, %ebp<br class=""> ; X64-NEXT: cmovneq %r15, %rax<br class=""> ; X64-NEXT: xorl %ebx, %ebx<br class="">+; X64-NEXT: jmp .LBB2_3<br class=""> ; X64-NEXT: .p2align 4, 0x90<br class="">+; X64-NEXT: .LBB2_6: # in Loop: Header=BB2_3 Depth=1<br class="">+; X64-NEXT: cmovgeq %r15, %rax<br class=""> ; X64-NEXT: .LBB2_3: # %l.header<br class=""> ; X64-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; X64-NEXT: movslq (%r12), %rcx<br class="">@@ -234,11 +237,8 @@ define void @test_basic_loop(i32 %a, i32<br class=""> ; X64-NEXT: cmovneq %r15, %rax<br class=""> ; X64-NEXT: incl %ebx<br class=""> ; X64-NEXT: cmpl %ebp, %ebx<br class="">-; X64-NEXT: jge .LBB2_4<br class="">-; X64-NEXT: # %bb.6: # in Loop: Header=BB2_3 Depth=1<br class="">-; X64-NEXT: cmovgeq %r15, %rax<br class="">-; X64-NEXT: jmp .LBB2_3<br class="">-; X64-NEXT: .LBB2_4:<br class="">+; X64-NEXT: jl .LBB2_6<br class="">+; X64-NEXT: # %bb.4:<br class=""> ; X64-NEXT: cmovlq %r15, %rax<br class=""> ; X64-NEXT: .LBB2_5: # %exit<br class=""> ; X64-NEXT: shlq $47, %rax<br class="">@@ -328,12 +328,20 @@ define void @test_basic_nested_loop(i32<br class=""> ; X64-NEXT: xorl %r13d, %r13d<br class=""> ; X64-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill<br class=""> ; X64-NEXT: testl %r15d, %r15d<br class="">-; X64-NEXT: jle .LBB3_4<br class="">+; X64-NEXT: jg .LBB3_5<br class="">+; X64-NEXT: jmp .LBB3_4<br class=""> ; X64-NEXT: .p2align 4, 0x90<br class="">+; X64-NEXT: .LBB3_12:<br class="">+; X64-NEXT: cmovgeq %rbp, %rax<br class="">+; X64-NEXT: testl %r15d, %r15d<br class="">+; X64-NEXT: jle .LBB3_4<br class=""> ; X64-NEXT: .LBB3_5: # %l2.header.preheader<br class=""> ; X64-NEXT: cmovleq %rbp, %rax<br class=""> ; X64-NEXT: xorl %r15d, %r15d<br class="">+; X64-NEXT: jmp .LBB3_6<br class=""> ; X64-NEXT: .p2align 4, 0x90<br class="">+; X64-NEXT: .LBB3_11: # in Loop: Header=BB3_6 Depth=1<br class="">+; X64-NEXT: cmovgeq %rbp, %rax<br class=""> ; X64-NEXT: .LBB3_6: # %l2.header<br class=""> ; X64-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; X64-NEXT: movslq (%rbx), %rcx<br class="">@@ -352,12 +360,8 @@ define void @test_basic_nested_loop(i32<br class=""> ; X64-NEXT: cmovneq %rbp, %rax<br class=""> ; X64-NEXT: incl %r15d<br class=""> ; X64-NEXT: cmpl %r12d, %r15d<br class="">-; X64-NEXT: jge .LBB3_7<br class="">-; X64-NEXT: # %bb.11: # in Loop: Header=BB3_6 Depth=1<br class="">-; X64-NEXT: cmovgeq %rbp, %rax<br class="">-; X64-NEXT: jmp .LBB3_6<br class="">-; X64-NEXT: .p2align 4, 0x90<br class="">-; X64-NEXT: .LBB3_7:<br class="">+; X64-NEXT: jl .LBB3_11<br class="">+; X64-NEXT: # %bb.7:<br class=""> ; X64-NEXT: cmovlq %rbp, %rax<br class=""> ; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %r15d # 4-byte Reload<br class=""> ; X64-NEXT: jmp .LBB3_8<br class="">@@ -381,13 +385,8 @@ define void @test_basic_nested_loop(i32<br class=""> ; X64-NEXT: cmovneq %rbp, %rax<br class=""> ; X64-NEXT: incl %r13d<br class=""> ; X64-NEXT: cmpl %r15d, %r13d<br class="">-; X64-NEXT: jge .LBB3_9<br class="">-; X64-NEXT: # %bb.12:<br class="">-; X64-NEXT: cmovgeq %rbp, %rax<br class="">-; X64-NEXT: testl %r15d, %r15d<br class="">-; X64-NEXT: jg .LBB3_5<br class="">-; X64-NEXT: jmp .LBB3_4<br class="">-; X64-NEXT: .LBB3_9:<br class="">+; X64-NEXT: jl .LBB3_12<br class="">+; X64-NEXT: # %bb.9:<br class=""> ; X64-NEXT: cmovlq %rbp, %rax<br class=""> ; X64-NEXT: .LBB3_10: # %exit<br class=""> ; X64-NEXT: shlq $47, %rax<br class="">@@ -419,17 +418,7 @@ define void @test_basic_nested_loop(i32<br class=""> ; X64-LFENCE-NEXT: movl %esi, %r15d<br class=""> ; X64-LFENCE-NEXT: lfence<br class=""> ; X64-LFENCE-NEXT: xorl %r12d, %r12d<br class="">-; X64-LFENCE-NEXT: jmp .LBB3_2<br class=""> ; X64-LFENCE-NEXT: .p2align 4, 0x90<br class="">-; X64-LFENCE-NEXT: .LBB3_5: # %l1.latch<br class="">-; X64-LFENCE-NEXT: # in Loop: Header=BB3_2 Depth=1<br class="">-; X64-LFENCE-NEXT: lfence<br class="">-; X64-LFENCE-NEXT: movslq (%rbx), %rax<br class="">-; X64-LFENCE-NEXT: movl (%r14,%rax,4), %edi<br class="">-; X64-LFENCE-NEXT: callq sink<br class="">-; X64-LFENCE-NEXT: incl %r12d<br class="">-; X64-LFENCE-NEXT: cmpl %r15d, %r12d<br class="">-; X64-LFENCE-NEXT: jge .LBB3_6<br class=""> ; X64-LFENCE-NEXT: .LBB3_2: # %l1.header<br class=""> ; X64-LFENCE-NEXT: # =>This Loop Header: Depth=1<br class=""> ; X64-LFENCE-NEXT: # Child Loop BB3_4 Depth 2<br class="">@@ -451,7 +440,15 @@ define void @test_basic_nested_loop(i32<br class=""> ; X64-LFENCE-NEXT: incl %ebp<br class=""> ; X64-LFENCE-NEXT: cmpl %r13d, %ebp<br class=""> ; X64-LFENCE-NEXT: jl .LBB3_4<br class="">-; X64-LFENCE-NEXT: jmp .LBB3_5<br class="">+; X64-LFENCE-NEXT: .LBB3_5: # %l1.latch<br class="">+; X64-LFENCE-NEXT: # in Loop: Header=BB3_2 Depth=1<br class="">+; X64-LFENCE-NEXT: lfence<br class="">+; X64-LFENCE-NEXT: movslq (%rbx), %rax<br class="">+; X64-LFENCE-NEXT: movl (%r14,%rax,4), %edi<br class="">+; X64-LFENCE-NEXT: callq sink<br class="">+; X64-LFENCE-NEXT: incl %r12d<br class="">+; X64-LFENCE-NEXT: cmpl %r15d, %r12d<br class="">+; X64-LFENCE-NEXT: jl .LBB3_2<br class=""> ; X64-LFENCE-NEXT: .LBB3_6: # %exit<br class=""> ; X64-LFENCE-NEXT: lfence<br class=""> ; X64-LFENCE-NEXT: addq $8, %rsp<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/tail-dup-merge-loop-headers.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-merge-loop-headers.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-merge-loop-headers.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/tail-dup-merge-loop-headers.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/tail-dup-merge-loop-headers.ll Thu Aug 22 09:21:32 2019<br class="">@@ -12,17 +12,14 @@ define void @tail_dup_merge_loops(i32 %a<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; CHECK-NEXT: incq %rsi<br class=""> ; CHECK-NEXT: testl %edi, %edi<br class="">-; CHECK-NEXT: je .LBB0_5<br class="">+; CHECK-NEXT: jne .LBB0_2<br class="">+; CHECK-NEXT: jmp .LBB0_5<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_2: # %inner_loop_top<br class="">-; CHECK-NEXT: # =>This Loop Header: Depth=1<br class="">-; CHECK-NEXT: # Child Loop BB0_4 Depth 2<br class="">-; CHECK-NEXT: cmpb $0, (%rsi)<br class="">-; CHECK-NEXT: js .LBB0_3<br class=""> ; CHECK-NEXT: .LBB0_4: # %inner_loop_latch<br class="">-; CHECK-NEXT: # Parent Loop BB0_2 Depth=1<br class="">-; CHECK-NEXT: # => This Inner Loop Header: Depth=2<br class="">+; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1<br class=""> ; CHECK-NEXT: addq $2, %rsi<br class="">+; CHECK-NEXT: .LBB0_2: # %inner_loop_top<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; CHECK-NEXT: cmpb $0, (%rsi)<br class=""> ; CHECK-NEXT: jns .LBB0_4<br class=""> ; CHECK-NEXT: jmp .LBB0_3<br class="">@@ -133,58 +130,58 @@ define i32 @loop_shared_header(i8* %exe,<br class=""> ; CHECK-NEXT: testl %ebp, %ebp<br class=""> ; CHECK-NEXT: je .LBB1_18<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB1_9: # %shared_loop_header<br class="">+; CHECK-NEXT: .LBB1_8: # %shared_loop_header<br class=""> ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; CHECK-NEXT: testq %rbx, %rbx<br class=""> ; CHECK-NEXT: jne .LBB1_27<br class="">-; CHECK-NEXT: # %bb.10: # %inner_loop_body<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: # %bb.9: # %inner_loop_body<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: testl %eax, %eax<br class="">-; CHECK-NEXT: jns .LBB1_9<br class="">-; CHECK-NEXT: # %bb.11: # %if.end96.i<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: jns .LBB1_8<br class="">+; CHECK-NEXT: # %bb.10: # %if.end96.i<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: cmpl $3, %ebp<br class=""> ; CHECK-NEXT: jae .LBB1_22<br class="">-; CHECK-NEXT: # %bb.12: # %if.end287.i<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: # %bb.11: # %if.end287.i<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: xorl %esi, %esi<br class=""> ; CHECK-NEXT: cmpl $1, %ebp<br class=""> ; CHECK-NEXT: setne %dl<br class=""> ; CHECK-NEXT: testb %al, %al<br class="">-; CHECK-NEXT: jne .LBB1_16<br class="">-; CHECK-NEXT: # %bb.13: # %if.end308.i<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: jne .LBB1_15<br class="">+; CHECK-NEXT: # %bb.12: # %if.end308.i<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: testb %al, %al<br class="">-; CHECK-NEXT: je .LBB1_7<br class="">-; CHECK-NEXT: # %bb.14: # %if.end335.i<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: je .LBB1_17<br class="">+; CHECK-NEXT: # %bb.13: # %if.end335.i<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: xorl %edx, %edx<br class=""> ; CHECK-NEXT: testb %dl, %dl<br class=""> ; CHECK-NEXT: movl $0, %esi<br class="">-; CHECK-NEXT: jne .LBB1_8<br class="">-; CHECK-NEXT: # %bb.15: # %merge_other<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: jne .LBB1_7<br class="">+; CHECK-NEXT: # %bb.14: # %merge_other<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: xorl %esi, %esi<br class="">-; CHECK-NEXT: jmp .LBB1_17<br class="">-; CHECK-NEXT: .LBB1_16: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: jmp .LBB1_16<br class="">+; CHECK-NEXT: .LBB1_15: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: movb %dl, %sil<br class=""> ; CHECK-NEXT: addl $3, %esi<br class="">-; CHECK-NEXT: .LBB1_17: # %outer_loop_latch<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: .LBB1_16: # %outer_loop_latch<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: # implicit-def: $dl<br class="">-; CHECK-NEXT: jmp .LBB1_8<br class="">-; CHECK-NEXT: .LBB1_7: # %merge_predecessor_split<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: jmp .LBB1_7<br class="">+; CHECK-NEXT: .LBB1_17: # %merge_predecessor_split<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: movb $32, %dl<br class=""> ; CHECK-NEXT: xorl %esi, %esi<br class="">-; CHECK-NEXT: .LBB1_8: # %outer_loop_latch<br class="">-; CHECK-NEXT: # in Loop: Header=BB1_9 Depth=1<br class="">+; CHECK-NEXT: .LBB1_7: # %outer_loop_latch<br class="">+; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=1<br class=""> ; CHECK-NEXT: movzwl %si, %esi<br class=""> ; CHECK-NEXT: decl %esi<br class=""> ; CHECK-NEXT: movzwl %si, %esi<br class=""> ; CHECK-NEXT: leaq 1(%rcx,%rsi), %rcx<br class=""> ; CHECK-NEXT: testl %ebp, %ebp<br class="">-; CHECK-NEXT: jne .LBB1_9<br class="">+; CHECK-NEXT: jne .LBB1_8<br class=""> ; CHECK-NEXT: .LBB1_18: # %while.cond.us1412.i<br class=""> ; CHECK-NEXT: xorl %eax, %eax<br class=""> ; CHECK-NEXT: testb %al, %al<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/tail-dup-repeat.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-repeat.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-repeat.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/tail-dup-repeat.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/tail-dup-repeat.ll Thu Aug 22 09:21:32 2019<br class="">@@ -10,30 +10,35 @@<br class=""> define void @repeated_tail_dup(i1 %a1, i1 %a2, i32* %a4, i32* %a5, i8* %a6, i32 %a7) #0 align 2 {<br class=""> ; CHECK-LABEL: repeated_tail_dup:<br class=""> ; CHECK: # %bb.0: # %entry<br class="">-; CHECK-NEXT: testb $1, %dil<br class="">-; CHECK-NEXT: je .LBB0_3<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_2: # %land.lhs.true<br class="">-; CHECK-NEXT: movl $10, (%rdx)<br class="">-; CHECK-NEXT: .LBB0_6: # %dup2<br class="">-; CHECK-NEXT: movl $2, (%rcx)<br class="">-; CHECK-NEXT: testl %r9d, %r9d<br class="">-; CHECK-NEXT: jne .LBB0_8<br class=""> ; CHECK-NEXT: .LBB0_1: # %for.cond<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; CHECK-NEXT: testb $1, %dil<br class="">-; CHECK-NEXT: jne .LBB0_2<br class="">+; CHECK-NEXT: je .LBB0_3<br class="">+; CHECK-NEXT: # %bb.2: # %land.lhs.true<br class="">+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class="">+; CHECK-NEXT: movl $10, (%rdx)<br class="">+; CHECK-NEXT: jmp .LBB0_6<br class="">+; CHECK-NEXT: .p2align 4, 0x90<br class=""> ; CHECK-NEXT: .LBB0_3: # %if.end56<br class="">+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: testb $1, %sil<br class=""> ; CHECK-NEXT: je .LBB0_5<br class=""> ; CHECK-NEXT: # %bb.4: # %if.then64<br class="">+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movb $1, (%r8)<br class=""> ; CHECK-NEXT: testl %r9d, %r9d<br class=""> ; CHECK-NEXT: je .LBB0_1<br class=""> ; CHECK-NEXT: jmp .LBB0_8<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class=""> ; CHECK-NEXT: .LBB0_5: # %if.end70<br class="">+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movl $12, (%rdx)<br class="">-; CHECK-NEXT: jmp .LBB0_6<br class="">+; CHECK-NEXT: .LBB0_6: # %dup2<br class="">+; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class="">+; CHECK-NEXT: movl $2, (%rcx)<br class="">+; CHECK-NEXT: testl %r9d, %r9d<br class="">+; CHECK-NEXT: je .LBB0_1<br class=""> ; CHECK-NEXT: .LBB0_8: # %for.end<br class=""> ; CHECK-NEXT: retq<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/vector-shift-by-select-loop.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-by-select-loop.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-by-select-loop.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/vector-shift-by-select-loop.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/vector-shift-by-select-loop.ll Thu Aug 22 09:21:32 2019<br class="">@@ -115,17 +115,8 @@ define void @vector_variable_shift_left_<br class=""> ; SSE-NEXT: jne .LBB0_4<br class=""> ; SSE-NEXT: # %bb.5: # %middle.block<br class=""> ; SSE-NEXT: cmpq %rax, %rdx<br class="">-; SSE-NEXT: jne .LBB0_6<br class="">-; SSE-NEXT: .LBB0_9: # %for.cond.cleanup<br class="">-; SSE-NEXT: retq<br class="">-; SSE-NEXT: .p2align 4, 0x90<br class="">-; SSE-NEXT: .LBB0_8: # %for.body<br class="">-; SSE-NEXT: # in Loop: Header=BB0_6 Depth=1<br class="">-; SSE-NEXT: # kill: def $cl killed $cl killed $ecx<br class="">-; SSE-NEXT: shll %cl, (%rdi,%rdx,4)<br class="">-; SSE-NEXT: incq %rdx<br class="">-; SSE-NEXT: cmpq %rdx, %rax<br class=""> ; SSE-NEXT: je .LBB0_9<br class="">+; SSE-NEXT: .p2align 4, 0x90<br class=""> ; SSE-NEXT: .LBB0_6: # %for.body<br class=""> ; SSE-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; SSE-NEXT: cmpb $0, (%rsi,%rdx)<br class="">@@ -134,7 +125,15 @@ define void @vector_variable_shift_left_<br class=""> ; SSE-NEXT: # %bb.7: # %for.body<br class=""> ; SSE-NEXT: # in Loop: Header=BB0_6 Depth=1<br class=""> ; SSE-NEXT: movl %r8d, %ecx<br class="">-; SSE-NEXT: jmp .LBB0_8<br class="">+; SSE-NEXT: .LBB0_8: # %for.body<br class="">+; SSE-NEXT: # in Loop: Header=BB0_6 Depth=1<br class="">+; SSE-NEXT: # kill: def $cl killed $cl killed $ecx<br class="">+; SSE-NEXT: shll %cl, (%rdi,%rdx,4)<br class="">+; SSE-NEXT: incq %rdx<br class="">+; SSE-NEXT: cmpq %rdx, %rax<br class="">+; SSE-NEXT: jne .LBB0_6<br class="">+; SSE-NEXT: .LBB0_9: # %for.cond.cleanup<br class="">+; SSE-NEXT: retq<br class=""> ;<br class=""> ; AVX1-LABEL: vector_variable_shift_left_loop:<br class=""> ; AVX1: # %bb.0: # %entry<br class="">@@ -242,19 +241,8 @@ define void @vector_variable_shift_left_<br class=""> ; AVX1-NEXT: jne .LBB0_4<br class=""> ; AVX1-NEXT: # %bb.5: # %middle.block<br class=""> ; AVX1-NEXT: cmpq %rax, %rdx<br class="">-; AVX1-NEXT: jne .LBB0_6<br class="">-; AVX1-NEXT: .LBB0_9: # %for.cond.cleanup<br class="">-; AVX1-NEXT: addq $24, %rsp<br class="">-; AVX1-NEXT: vzeroupper<br class="">-; AVX1-NEXT: retq<br class="">-; AVX1-NEXT: .p2align 4, 0x90<br class="">-; AVX1-NEXT: .LBB0_8: # %for.body<br class="">-; AVX1-NEXT: # in Loop: Header=BB0_6 Depth=1<br class="">-; AVX1-NEXT: # kill: def $cl killed $cl killed $ecx<br class="">-; AVX1-NEXT: shll %cl, (%rdi,%rdx,4)<br class="">-; AVX1-NEXT: incq %rdx<br class="">-; AVX1-NEXT: cmpq %rdx, %rax<br class=""> ; AVX1-NEXT: je .LBB0_9<br class="">+; AVX1-NEXT: .p2align 4, 0x90<br class=""> ; AVX1-NEXT: .LBB0_6: # %for.body<br class=""> ; AVX1-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; AVX1-NEXT: cmpb $0, (%rsi,%rdx)<br class="">@@ -263,7 +251,17 @@ define void @vector_variable_shift_left_<br class=""> ; AVX1-NEXT: # %bb.7: # %for.body<br class=""> ; AVX1-NEXT: # in Loop: Header=BB0_6 Depth=1<br class=""> ; AVX1-NEXT: movl %r8d, %ecx<br class="">-; AVX1-NEXT: jmp .LBB0_8<br class="">+; AVX1-NEXT: .LBB0_8: # %for.body<br class="">+; AVX1-NEXT: # in Loop: Header=BB0_6 Depth=1<br class="">+; AVX1-NEXT: # kill: def $cl killed $cl killed $ecx<br class="">+; AVX1-NEXT: shll %cl, (%rdi,%rdx,4)<br class="">+; AVX1-NEXT: incq %rdx<br class="">+; AVX1-NEXT: cmpq %rdx, %rax<br class="">+; AVX1-NEXT: jne .LBB0_6<br class="">+; AVX1-NEXT: .LBB0_9: # %for.cond.cleanup<br class="">+; AVX1-NEXT: addq $24, %rsp<br class="">+; AVX1-NEXT: vzeroupper<br class="">+; AVX1-NEXT: retq<br class=""> ;<br class=""> ; AVX2-LABEL: vector_variable_shift_left_loop:<br class=""> ; AVX2: # %bb.0: # %entry<br class="">@@ -318,18 +316,8 @@ define void @vector_variable_shift_left_<br class=""> ; AVX2-NEXT: jne .LBB0_4<br class=""> ; AVX2-NEXT: # %bb.5: # %middle.block<br class=""> ; AVX2-NEXT: cmpq %rax, %rdx<br class="">-; AVX2-NEXT: jne .LBB0_6<br class="">-; AVX2-NEXT: .LBB0_9: # %for.cond.cleanup<br class="">-; AVX2-NEXT: vzeroupper<br class="">-; AVX2-NEXT: retq<br class="">-; AVX2-NEXT: .p2align 4, 0x90<br class="">-; AVX2-NEXT: .LBB0_8: # %for.body<br class="">-; AVX2-NEXT: # in Loop: Header=BB0_6 Depth=1<br class="">-; AVX2-NEXT: # kill: def $cl killed $cl killed $ecx<br class="">-; AVX2-NEXT: shll %cl, (%rdi,%rdx,4)<br class="">-; AVX2-NEXT: incq %rdx<br class="">-; AVX2-NEXT: cmpq %rdx, %rax<br class=""> ; AVX2-NEXT: je .LBB0_9<br class="">+; AVX2-NEXT: .p2align 4, 0x90<br class=""> ; AVX2-NEXT: .LBB0_6: # %for.body<br class=""> ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1<br class=""> ; AVX2-NEXT: cmpb $0, (%rsi,%rdx)<br class="">@@ -338,7 +326,16 @@ define void @vector_variable_shift_left_<br class=""> ; AVX2-NEXT: # %bb.7: # %for.body<br class=""> ; AVX2-NEXT: # in Loop: Header=BB0_6 Depth=1<br class=""> ; AVX2-NEXT: movl %r8d, %ecx<br class="">-; AVX2-NEXT: jmp .LBB0_8<br class="">+; AVX2-NEXT: .LBB0_8: # %for.body<br class="">+; AVX2-NEXT: # in Loop: Header=BB0_6 Depth=1<br class="">+; AVX2-NEXT: # kill: def $cl killed $cl killed $ecx<br class="">+; AVX2-NEXT: shll %cl, (%rdi,%rdx,4)<br class="">+; AVX2-NEXT: incq %rdx<br class="">+; AVX2-NEXT: cmpq %rdx, %rax<br class="">+; AVX2-NEXT: jne .LBB0_6<br class="">+; AVX2-NEXT: .LBB0_9: # %for.cond.cleanup<br class="">+; AVX2-NEXT: vzeroupper<br class="">+; AVX2-NEXT: retq<br class=""> entry:<br class=""> %cmp12 = icmp sgt i32 %count, 0<br class=""> br i1 %cmp12, label %for.body.preheader, label %for.cond.cleanup<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_arith-1.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-1.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-1.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_arith-1.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_arith-1.ll Thu Aug 22 09:21:32 2019<br class="">@@ -7,13 +7,9 @@ define void @update(<3 x i8>* %dst, <3 x<br class=""> ; CHECK-NEXT: pushl %eax<br class=""> ; CHECK-NEXT: movl $0, (%esp)<br class=""> ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0<br class="">+; CHECK-NEXT: jmp .LBB0_1<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_1: # %forcond<br class="">-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK-NEXT: movl (%esp), %eax<br class="">-; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax<br class="">-; CHECK-NEXT: jge .LBB0_3<br class="">-; CHECK-NEXT: # %bb.2: # %forbody<br class="">+; CHECK-NEXT: .LBB0_2: # %forbody<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movl (%esp), %eax<br class=""> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx<br class="">@@ -23,8 +19,12 @@ define void @update(<3 x i8>* %dst, <3 x<br class=""> ; CHECK-NEXT: pextrb $2, %xmm1, 2(%ecx,%eax,4)<br class=""> ; CHECK-NEXT: pextrw $0, %xmm1, (%ecx,%eax,4)<br class=""> ; CHECK-NEXT: incl (%esp)<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3: # %afterfor<br class="">+; CHECK-NEXT: .LBB0_1: # %forcond<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK-NEXT: movl (%esp), %eax<br class="">+; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax<br class="">+; CHECK-NEXT: jl .LBB0_2<br class="">+; CHECK-NEXT: # %bb.3: # %afterfor<br class=""> ; CHECK-NEXT: popl %eax<br class=""> ; CHECK-NEXT: retl<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_arith-2.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_arith-2.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_arith-2.ll Thu Aug 22 09:21:32 2019<br class="">@@ -10,13 +10,9 @@ define void @update(i64* %dst_i, i64* %s<br class=""> ; CHECK-NEXT: movl $0, (%esp)<br class=""> ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0<br class=""> ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <4,4,4,4,4,4,4,4,u,u,u,u,u,u,u,u><br class="">+; CHECK-NEXT: jmp .LBB0_1<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_1: # %forcond<br class="">-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK-NEXT: movl (%esp), %eax<br class="">-; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax<br class="">-; CHECK-NEXT: jge .LBB0_3<br class="">-; CHECK-NEXT: # %bb.2: # %forbody<br class="">+; CHECK-NEXT: .LBB0_2: # %forbody<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movl (%esp), %eax<br class=""> ; CHECK-NEXT: leal (,%eax,8), %ecx<br class="">@@ -30,8 +26,12 @@ define void @update(i64* %dst_i, i64* %s<br class=""> ; CHECK-NEXT: pand %xmm1, %xmm2<br class=""> ; CHECK-NEXT: movq %xmm2, (%edx,%eax,8)<br class=""> ; CHECK-NEXT: incl (%esp)<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3: # %afterfor<br class="">+; CHECK-NEXT: .LBB0_1: # %forcond<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK-NEXT: movl (%esp), %eax<br class="">+; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax<br class="">+; CHECK-NEXT: jl .LBB0_2<br class="">+; CHECK-NEXT: # %bb.3: # %afterfor<br class=""> ; CHECK-NEXT: addl $12, %esp<br class=""> ; CHECK-NEXT: retl<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_arith-3.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-3.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-3.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_arith-3.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_arith-3.ll Thu Aug 22 09:21:32 2019<br class="">@@ -17,13 +17,9 @@ define void @update(<3 x i16>* %dst, <3<br class=""> ; CHECK-NEXT: movw $1, {{[0-9]+}}(%esp)<br class=""> ; CHECK-NEXT: movl $65537, {{[0-9]+}}(%esp) # imm = 0x10001<br class=""> ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)<br class="">+; CHECK-NEXT: jmp .LBB0_1<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_1: # %forcond<br class="">-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">-; CHECK-NEXT: cmpl 16(%ebp), %eax<br class="">-; CHECK-NEXT: jge .LBB0_3<br class="">-; CHECK-NEXT: # %bb.2: # %forbody<br class="">+; CHECK-NEXT: .LBB0_2: # %forbody<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class=""> ; CHECK-NEXT: movl 12(%ebp), %edx<br class="">@@ -34,8 +30,12 @@ define void @update(<3 x i16>* %dst, <3<br class=""> ; CHECK-NEXT: pextrw $2, %xmm1, 4(%ecx,%eax,8)<br class=""> ; CHECK-NEXT: movd %xmm1, (%ecx,%eax,8)<br class=""> ; CHECK-NEXT: incl {{[0-9]+}}(%esp)<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3: # %afterfor<br class="">+; CHECK-NEXT: .LBB0_1: # %forcond<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">+; CHECK-NEXT: cmpl 16(%ebp), %eax<br class="">+; CHECK-NEXT: jl .LBB0_2<br class="">+; CHECK-NEXT: # %bb.3: # %afterfor<br class=""> ; CHECK-NEXT: movl %ebp, %esp<br class=""> ; CHECK-NEXT: popl %ebp<br class=""> ; CHECK-NEXT: retl<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_arith-4.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-4.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-4.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_arith-4.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_arith-4.ll Thu Aug 22 09:21:32 2019<br class="">@@ -16,13 +16,9 @@ define void @update(<5 x i16>* %dst, <5<br class=""> ; SSE2-NEXT: movl $0, -{{[0-9]+}}(%rsp)<br class=""> ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = <271,271,271,271,271,u,u,u><br class=""> ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = <2,4,2,2,2,u,u,u><br class="">+; SSE2-NEXT: jmp .LBB0_1<br class=""> ; SSE2-NEXT: .p2align 4, 0x90<br class="">-; SSE2-NEXT: .LBB0_1: # %forcond<br class="">-; SSE2-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax<br class="">-; SSE2-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax<br class="">-; SSE2-NEXT: jge .LBB0_3<br class="">-; SSE2-NEXT: # %bb.2: # %forbody<br class="">+; SSE2-NEXT: .LBB0_2: # %forbody<br class=""> ; SSE2-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; SSE2-NEXT: movslq -{{[0-9]+}}(%rsp), %rax<br class=""> ; SSE2-NEXT: movq -{{[0-9]+}}(%rsp), %rcx<br class="">@@ -35,8 +31,12 @@ define void @update(<5 x i16>* %dst, <5<br class=""> ; SSE2-NEXT: pextrw $4, %xmm2, %edx<br class=""> ; SSE2-NEXT: movw %dx, 8(%rcx,%rax)<br class=""> ; SSE2-NEXT: incl -{{[0-9]+}}(%rsp)<br class="">-; SSE2-NEXT: jmp .LBB0_1<br class="">-; SSE2-NEXT: .LBB0_3: # %afterfor<br class="">+; SSE2-NEXT: .LBB0_1: # %forcond<br class="">+; SSE2-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax<br class="">+; SSE2-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax<br class="">+; SSE2-NEXT: jl .LBB0_2<br class="">+; SSE2-NEXT: # %bb.3: # %afterfor<br class=""> ; SSE2-NEXT: retq<br class=""> ;<br class=""> ; SSE41-LABEL: update:<br class="">@@ -49,13 +49,9 @@ define void @update(<5 x i16>* %dst, <5<br class=""> ; SSE41-NEXT: movw $0, -{{[0-9]+}}(%rsp)<br class=""> ; SSE41-NEXT: movl $0, -{{[0-9]+}}(%rsp)<br class=""> ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <271,271,271,271,271,u,u,u><br class="">+; SSE41-NEXT: jmp .LBB0_1<br class=""> ; SSE41-NEXT: .p2align 4, 0x90<br class="">-; SSE41-NEXT: .LBB0_1: # %forcond<br class="">-; SSE41-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; SSE41-NEXT: movl -{{[0-9]+}}(%rsp), %eax<br class="">-; SSE41-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax<br class="">-; SSE41-NEXT: jge .LBB0_3<br class="">-; SSE41-NEXT: # %bb.2: # %forbody<br class="">+; SSE41-NEXT: .LBB0_2: # %forbody<br class=""> ; SSE41-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; SSE41-NEXT: movslq -{{[0-9]+}}(%rsp), %rax<br class=""> ; SSE41-NEXT: movq -{{[0-9]+}}(%rsp), %rcx<br class="">@@ -70,8 +66,12 @@ define void @update(<5 x i16>* %dst, <5<br class=""> ; SSE41-NEXT: pextrw $4, %xmm1, 8(%rcx,%rax)<br class=""> ; SSE41-NEXT: movq %xmm2, (%rcx,%rax)<br class=""> ; SSE41-NEXT: incl -{{[0-9]+}}(%rsp)<br class="">-; SSE41-NEXT: jmp .LBB0_1<br class="">-; SSE41-NEXT: .LBB0_3: # %afterfor<br class="">+; SSE41-NEXT: .LBB0_1: # %forcond<br class="">+; SSE41-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; SSE41-NEXT: movl -{{[0-9]+}}(%rsp), %eax<br class="">+; SSE41-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax<br class="">+; SSE41-NEXT: jl .LBB0_2<br class="">+; SSE41-NEXT: # %bb.3: # %afterfor<br class=""> ; SSE41-NEXT: retq<br class=""> entry:<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>%dst.addr = alloca <5 x i16>*<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_arith-5.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-5.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-5.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_arith-5.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_arith-5.ll Thu Aug 22 09:21:32 2019<br class="">@@ -14,13 +14,9 @@ define void @update(<3 x i32>* %dst, <3<br class=""> ; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp)<br class=""> ; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)<br class=""> ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <3,3,3,u><br class="">+; CHECK-NEXT: jmp .LBB0_1<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_1: # %forcond<br class="">-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax<br class="">-; CHECK-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax<br class="">-; CHECK-NEXT: jge .LBB0_3<br class="">-; CHECK-NEXT: # %bb.2: # %forbody<br class="">+; CHECK-NEXT: .LBB0_2: # %forbody<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rax<br class=""> ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx<br class="">@@ -32,8 +28,12 @@ define void @update(<3 x i32>* %dst, <3<br class=""> ; CHECK-NEXT: pextrd $2, %xmm1, 8(%rcx,%rax)<br class=""> ; CHECK-NEXT: movq %xmm1, (%rcx,%rax)<br class=""> ; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3: # %afterfor<br class="">+; CHECK-NEXT: .LBB0_1: # %forcond<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax<br class="">+; CHECK-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax<br class="">+; CHECK-NEXT: jl .LBB0_2<br class="">+; CHECK-NEXT: # %bb.3: # %afterfor<br class=""> ; CHECK-NEXT: retq<br class=""> entry:<br class=""> <span class="Apple-tab-span" style="white-space:pre"> </span>%dst.addr = alloca <3 x i32>*<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_arith-6.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-6.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-6.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_arith-6.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_arith-6.ll Thu Aug 22 09:21:32 2019<br class="">@@ -15,13 +15,9 @@ define void @update(<3 x float>* %dst, <<br class=""> ; CHECK-NEXT: movl $1065353216, {{[0-9]+}}(%esp) # imm = 0x3F800000<br class=""> ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)<br class=""> ; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1.97604004E+3,1.97604004E+3,1.97604004E+3,u><br class="">+; CHECK-NEXT: jmp .LBB0_1<br class=""> ; CHECK-NEXT: .p2align 4, 0x90<br class="">-; CHECK-NEXT: .LBB0_1: # %forcond<br class="">-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">-; CHECK-NEXT: cmpl 16(%ebp), %eax<br class="">-; CHECK-NEXT: jge .LBB0_3<br class="">-; CHECK-NEXT: # %bb.2: # %forbody<br class="">+; CHECK-NEXT: .LBB0_2: # %forbody<br class=""> ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class=""> ; CHECK-NEXT: movl 8(%ebp), %ecx<br class="">@@ -34,8 +30,12 @@ define void @update(<3 x float>* %dst, <<br class=""> ; CHECK-NEXT: extractps $1, %xmm1, 4(%ecx,%eax)<br class=""> ; CHECK-NEXT: movss %xmm1, (%ecx,%eax)<br class=""> ; CHECK-NEXT: incl {{[0-9]+}}(%esp)<br class="">-; CHECK-NEXT: jmp .LBB0_1<br class="">-; CHECK-NEXT: .LBB0_3: # %afterfor<br class="">+; CHECK-NEXT: .LBB0_1: # %forcond<br class="">+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">+; CHECK-NEXT: cmpl 16(%ebp), %eax<br class="">+; CHECK-NEXT: jl .LBB0_2<br class="">+; CHECK-NEXT: # %bb.3: # %afterfor<br class=""> ; CHECK-NEXT: movl %ebp, %esp<br class=""> ; CHECK-NEXT: popl %ebp<br class=""> ; CHECK-NEXT: retl<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/widen_cast-4.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-4.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-4.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/widen_cast-4.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/widen_cast-4.ll Thu Aug 22 09:21:32 2019<br class="">@@ -11,13 +11,9 @@ define void @update(i64* %dst_i, i64* %s<br class=""> ; WIDE-NEXT: pcmpeqd %xmm0, %xmm0<br class=""> ; WIDE-NEXT: movdqa {{.*#+}} xmm1 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]<br class=""> ; WIDE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]<br class="">+; WIDE-NEXT: jmp .LBB0_1<br class=""> ; WIDE-NEXT: .p2align 4, 0x90<br class="">-; WIDE-NEXT: .LBB0_1: # %forcond<br class="">-; WIDE-NEXT: # =>This Inner Loop Header: Depth=1<br class="">-; WIDE-NEXT: movl (%esp), %eax<br class="">-; WIDE-NEXT: cmpl {{[0-9]+}}(%esp), %eax<br class="">-; WIDE-NEXT: jge .LBB0_3<br class="">-; WIDE-NEXT: # %bb.2: # %forbody<br class="">+; WIDE-NEXT: .LBB0_2: # %forbody<br class=""> ; WIDE-NEXT: # in Loop: Header=BB0_1 Depth=1<br class=""> ; WIDE-NEXT: movl (%esp), %eax<br class=""> ; WIDE-NEXT: leal (,%eax,8), %ecx<br class="">@@ -34,8 +30,12 @@ define void @update(i64* %dst_i, i64* %s<br class=""> ; WIDE-NEXT: psubb %xmm2, %xmm3<br class=""> ; WIDE-NEXT: movq %xmm3, (%edx,%eax,8)<br class=""> ; WIDE-NEXT: incl (%esp)<br class="">-; WIDE-NEXT: jmp .LBB0_1<br class="">-; WIDE-NEXT: .LBB0_3: # %afterfor<br class="">+; WIDE-NEXT: .LBB0_1: # %forcond<br class="">+; WIDE-NEXT: # =>This Inner Loop Header: Depth=1<br class="">+; WIDE-NEXT: movl (%esp), %eax<br class="">+; WIDE-NEXT: cmpl {{[0-9]+}}(%esp), %eax<br class="">+; WIDE-NEXT: jl .LBB0_2<br class="">+; WIDE-NEXT: # %bb.3: # %afterfor<br class=""> ; WIDE-NEXT: addl $12, %esp<br class=""> ; WIDE-NEXT: retl<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/DebugInfo/X86/PR37234.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/PR37234.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/PR37234.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/DebugInfo/X86/PR37234.ll (original)<br class="">+++ llvm/trunk/test/DebugInfo/X86/PR37234.ll Thu Aug 22 09:21:32 2019<br class="">@@ -21,18 +21,18 @@<br class=""> ; CHECK-LABEL: # %bb.{{.*}}:<br class=""> ; CHECK: #DEBUG_VALUE: main:aa <- 0<br class=""> ; CHECK: <span class="Apple-tab-span" style="white-space:pre"> </span>#DEBUG_VALUE: main:aa <- $[[REG:[0-9a-z]+]]<br class="">-; CHECK: .LBB0_1:<br class="">-; CHECK: #DEBUG_VALUE: main:aa <- $[[REG]]<br class="">-; CHECK: je .LBB0_4<br class="">-; CHECK: # %bb.{{.*}}:<br class="">+; CHECK: <span class="Apple-tab-span" style="white-space:pre"> </span>jmp<span class="Apple-tab-span" style="white-space:pre"> </span>.LBB0_1<br class="">+; CHECK: .LBB0_2:<br class=""> ; CHECK: #DEBUG_VALUE: main:aa <- $[[REG]]<br class=""> ; CHECK: jne .LBB0_1<br class=""> ; CHECK: # %bb.{{.*}}:<br class=""> ; CHECK: #DEBUG_VALUE: main:aa <- $[[REG]]<br class=""> ; CHECK: incl %[[REG]]<br class=""> ; CHECK: #DEBUG_VALUE: main:aa <- $[[REG]]<br class="">-; CHECK: jmp .LBB0_1<br class="">-; CHECK: .LBB0_4:<br class="">+; CHECK: .LBB0_1:<br class="">+; CHECK: <span class="Apple-tab-span" style="white-space:pre"> </span>#DEBUG_VALUE: main:aa <- $[[REG]]<br class="">+; CHECK: jne .LBB0_2<br class="">+; CHECK: # %bb.{{.*}}:<br class=""> ; CHECK: <span class="Apple-tab-span" style="white-space:pre"> </span>#DEBUG_VALUE: main:aa <- $[[REG]]<br class=""> ; CHECK: <span class="Apple-tab-span" style="white-space:pre"> </span>retq<br class=""><br class=""><br class="">Modified: llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll?rev=369664&r1=369663&r2=369664&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll?rev=369664&r1=369663&r2=369664&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll (original)<br class="">+++ llvm/trunk/test/DebugInfo/X86/dbg-value-transfer-order.ll Thu Aug 22 09:21:32 2019<br class="">@@ -24,12 +24,6 @@<br class=""> ; with the Orders insertion point vector.<br class=""><br class=""> ; CHECK-LABEL: f: # @f<br class="">-; CHECK: .LBB0_4:<br class="">-; Check that this DEBUG_VALUE comes before the left shift.<br class="">-; CHECK: #DEBUG_VALUE: bit_offset <- $ecx<br class="">-; CHECK: .cv_loc 0 1 8 28 # t.c:8:28<br class="">-; CHECK: movl $1, %[[reg:[^ ]*]]<br class="">-; CHECK: shll %cl, %[[reg]]<br class=""> ; CHECK: .LBB0_2: # %while.body<br class=""> ; CHECK: movl $32, %ecx<br class=""> ; CHECK: testl {{.*}}<br class="">@@ -37,7 +31,12 @@<br class=""> ; CHECK: # %bb.3: # %if.then<br class=""> ; CHECK: callq if_then<br class=""> ; CHECK: movl %eax, %ecx<br class="">-; CHECK: jmp .LBB0_4<br class="">+; CHECK: .LBB0_4: # %if.end<br class="">+; Check that this DEBUG_VALUE comes before the left shift.<br class="">+; CHECK: #DEBUG_VALUE: bit_offset <- $ecx<br class="">+; CHECK: .cv_loc 0 1 8 28 # t.c:8:28<br class="">+; CHECK: movl $1, %[[reg:[^ ]*]]<br class="">+; CHECK: shll %cl, %[[reg]]<br class=""><br class=""> ; ModuleID = 't.c'<br class=""> source_filename = "t.c"<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></div></div></blockquote></div><br class=""></div></body></html>