<div dir="ltr"><div>I have reverted this in r370006 since it causes fatal errors in the backend when compiling an instrumented version of Clang. There is a reduced testcase posted to <a href="https://reviews.llvm.org/D66537">https://reviews.llvm.org/D66537</a></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Aug 26, 2019 at 10:00 AM Amaury Sechet via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: deadalnix<br>
Date: Mon Aug 26 10:02:12 2019<br>
New Revision: 369927<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=369927&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=369927&view=rev</a><br>
Log:<br>
[DAGCombiner] Remove a bunch of redundant AddToWorklist calls.<br>
<br>
Summary:<br>
This comes as a first step toward processing the DAG nodes in topological orders. Doing so ensure that arguments of a node are combined before the node itself is combined, which exposes ore opportunities for optimization and/or reduce the amount of patterns a node has to match for.<br>
<br>
DAGCombiner adding nodes to the worklist is various places causes the nodes to be in a different order from what is expected. In addition, this is reduant because these nodes end up being added to the worklist anyways due to the machinery at line 1621.<br>
<br>
Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri<br>
<br>
Subscribers: llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D66537" rel="noreferrer" target="_blank">https://reviews.llvm.org/D66537</a><br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=369927&r1=369926&r2=369927&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=369927&r1=369926&r2=369927&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Aug 26 10:02:12 2019<br>
@@ -1383,7 +1383,6 @@ SDValue DAGCombiner::SExtPromoteOperand(<br>
SDValue NewOp = PromoteOperand(Op, PVT, Replace);<br>
if (!NewOp.getNode())<br>
return SDValue();<br>
- AddToWorklist(NewOp.getNode());<br>
<br>
if (Replace)<br>
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());<br>
@@ -1398,7 +1397,6 @@ SDValue DAGCombiner::ZExtPromoteOperand(<br>
SDValue NewOp = PromoteOperand(Op, PVT, Replace);<br>
if (!NewOp.getNode())<br>
return SDValue();<br>
- AddToWorklist(NewOp.getNode());<br>
<br>
if (Replace)<br>
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());<br>
@@ -1457,14 +1455,10 @@ SDValue DAGCombiner::PromoteIntBinOp(SDV<br>
std::swap(NN0, NN1);<br>
}<br>
<br>
- if (Replace0) {<br>
- AddToWorklist(NN0.getNode());<br>
+ if (Replace0)<br>
ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());<br>
- }<br>
- if (Replace1) {<br>
- AddToWorklist(NN1.getNode());<br>
+ if (Replace1)<br>
ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());<br>
- }<br>
return Op;<br>
}<br>
return SDValue();<br>
@@ -2938,7 +2932,6 @@ SDValue DAGCombiner::visitADDCARRY(SDNod<br>
EVT VT = N0.getValueType();<br>
EVT CarryVT = CarryIn.getValueType();<br>
SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);<br>
- AddToWorklist(CarryExt.getNode());<br>
return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,<br>
DAG.getConstant(1, DL, VT)),<br>
DAG.getConstant(0, DL, CarryVT));<br>
@@ -3001,11 +2994,9 @@ static SDValue combineADDCARRYDiamond(DA<br>
return SDValue();<br>
}<br>
<br>
-<br>
auto cancelDiamond = [&](SDValue A,SDValue B) {<br>
SDLoc DL(N);<br>
SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);<br>
- Combiner.AddToWorklist(NewY.getNode());<br>
return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,<br>
DAG.getConstant(0, DL, X.getValueType()),<br>
NewY.getValue(1));<br>
@@ -3892,8 +3883,6 @@ SDValue DAGCombiner::visitSDIV(SDNode *N<br>
{ N0, N1 })) {<br>
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);<br>
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);<br>
- AddToWorklist(Mul.getNode());<br>
- AddToWorklist(Sub.getNode());<br>
CombineTo(RemNode, Sub);<br>
}<br>
return V;<br>
@@ -3949,15 +3938,11 @@ SDValue DAGCombiner::visitSDIVLike(SDVal<br>
// Splat the sign bit into the register<br>
SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,<br>
DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));<br>
- AddToWorklist(Sign.getNode());<br>
<br>
// Add (N0 < 0) ? abs2 - 1 : 0;<br>
SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);<br>
- AddToWorklist(Srl.getNode());<br>
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);<br>
- AddToWorklist(Add.getNode());<br>
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);<br>
- AddToWorklist(Sra.getNode());<br>
<br>
// Special case: (sdiv X, 1) -> X<br>
// Special Case: (sdiv X, -1) -> 0-X<br>
@@ -4030,8 +4015,6 @@ SDValue DAGCombiner::visitUDIV(SDNode *N<br>
{ N0, N1 })) {<br>
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);<br>
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);<br>
- AddToWorklist(Mul.getNode());<br>
- AddToWorklist(Sub.getNode());<br>
CombineTo(RemNode, Sub);<br>
}<br>
return V;<br>
@@ -4056,11 +4039,8 @@ SDValue DAGCombiner::visitUDIVLike(SDVal<br>
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&<br>
DAG.isKnownToBeAPowerOfTwo(N1)) {<br>
SDValue LogBase2 = BuildLogBase2(N1, DL);<br>
- AddToWorklist(LogBase2.getNode());<br>
-<br>
EVT ShiftVT = getShiftAmountTy(N0.getValueType());<br>
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);<br>
- AddToWorklist(Trunc.getNode());<br>
return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);<br>
}<br>
<br>
@@ -4070,13 +4050,10 @@ SDValue DAGCombiner::visitUDIVLike(SDVal<br>
if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&<br>
DAG.isKnownToBeAPowerOfTwo(N10)) {<br>
SDValue LogBase2 = BuildLogBase2(N10, DL);<br>
- AddToWorklist(LogBase2.getNode());<br>
<br>
EVT ADDVT = N1.getOperand(1).getValueType();<br>
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);<br>
- AddToWorklist(Trunc.getNode());<br>
SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);<br>
- AddToWorklist(Add.getNode());<br>
return DAG.getNode(ISD::SRL, DL, VT, N0, Add);<br>
}<br>
}<br>
@@ -4129,14 +4106,12 @@ SDValue DAGCombiner::visitREM(SDNode *N)<br>
if (DAG.isKnownToBeAPowerOfTwo(N1)) {<br>
// fold (urem x, pow2) -> (and x, pow2-1)<br>
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);<br>
- AddToWorklist(Add.getNode());<br>
return DAG.getNode(ISD::AND, DL, VT, N0, Add);<br>
}<br>
if (N1.getOpcode() == ISD::SHL &&<br>
DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {<br>
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))<br>
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);<br>
- AddToWorklist(Add.getNode());<br>
return DAG.getNode(ISD::AND, DL, VT, N0, Add);<br>
}<br>
}<br>
@@ -4161,8 +4136,6 @@ SDValue DAGCombiner::visitREM(SDNode *N)<br>
CombineTo(DivNode, OptimizedDiv);<br>
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);<br>
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);<br>
- AddToWorklist(OptimizedDiv.getNode());<br>
- AddToWorklist(Mul.getNode());<br>
return Sub;<br>
}<br>
}<br>
@@ -4305,7 +4278,6 @@ SDValue DAGCombiner::SimplifyNodeWithTwo<br>
// If the two computed results can be simplified separately, separate them.<br>
if (LoExists) {<br>
SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());<br>
- AddToWorklist(Lo.getNode());<br>
SDValue LoOpt = combine(Lo.getNode());<br>
if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&<br>
(!LegalOperations ||<br>
@@ -4315,7 +4287,6 @@ SDValue DAGCombiner::SimplifyNodeWithTwo<br>
<br>
if (HiExists) {<br>
SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());<br>
- AddToWorklist(Hi.getNode());<br>
SDValue HiOpt = combine(Hi.getNode());<br>
if (HiOpt.getNode() && HiOpt != Hi &&<br>
(!LegalOperations ||<br>
@@ -4664,7 +4635,6 @@ SDValue DAGCombiner::foldLogicOfSetCCs(b<br>
// (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)<br>
if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {<br>
SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);<br>
- AddToWorklist(Or.getNode());<br>
return DAG.getSetCC(DL, VT, Or, LR, CC1);<br>
}<br>
<br>
@@ -4683,7 +4653,6 @@ SDValue DAGCombiner::foldLogicOfSetCCs(b<br>
// (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)<br>
if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {<br>
SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);<br>
- AddToWorklist(And.getNode());<br>
return DAG.getSetCC(DL, VT, And, LR, CC1);<br>
}<br>
}<br>
@@ -4697,7 +4666,6 @@ SDValue DAGCombiner::foldLogicOfSetCCs(b<br>
SDValue One = DAG.getConstant(1, DL, OpVT);<br>
SDValue Two = DAG.getConstant(2, DL, OpVT);<br>
SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);<br>
- AddToWorklist(Add.getNode());<br>
return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);<br>
}<br>
<br>
@@ -5388,7 +5356,6 @@ SDValue DAGCombiner::visitAND(SDNode *N)<br>
if (SDValue Res = ReduceLoadWidth(N)) {<br>
LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND<br>
? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);<br>
- AddToWorklist(N);<br>
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);<br>
return SDValue(N, 0);<br>
}<br>
@@ -5454,7 +5421,6 @@ SDValue DAGCombiner::visitAND(SDNode *N)<br>
SDValue ExtLoad =<br>
DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),<br>
LN0->getBasePtr(), MemVT, LN0->getMemOperand());<br>
- AddToWorklist(N);<br>
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));<br>
return SDValue(N, 0); // Return N so it doesn't get rechecked!<br>
}<br>
@@ -5963,7 +5929,6 @@ SDValue DAGCombiner::visitOR(SDNode *N)<br>
if (SDValue COR = DAG.FoldConstantArithmetic(<br>
ISD::OR, SDLoc(N1), VT, N1.getNode(), N0.getOperand(1).getNode())) {<br>
SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);<br>
- AddToWorklist(IOR.getNode());<br>
return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);<br>
}<br>
}<br>
@@ -7063,7 +7028,6 @@ SDValue DAGCombiner::visitXOR(SDNode *N)<br>
SDLoc DL0(N0);<br>
V = DAG.getNode(ISD::XOR, DL0, V.getValueType(), V,<br>
DAG.getConstant(1, DL0, V.getValueType()));<br>
- AddToWorklist(V.getNode());<br>
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, V);<br>
}<br>
<br>
@@ -7075,7 +7039,6 @@ SDValue DAGCombiner::visitXOR(SDNode *N)<br>
unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;<br>
LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS<br>
RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS<br>
- AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());<br>
return DAG.getNode(NewOpcode, DL, VT, LHS, RHS);<br>
}<br>
}<br>
@@ -7087,7 +7050,6 @@ SDValue DAGCombiner::visitXOR(SDNode *N)<br>
unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;<br>
LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS<br>
RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS<br>
- AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());<br>
return DAG.getNode(NewOpcode, DL, VT, LHS, RHS);<br>
}<br>
}<br>
@@ -7105,7 +7067,6 @@ SDValue DAGCombiner::visitXOR(SDNode *N)<br>
if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) {<br>
SDValue X = N0.getOperand(0);<br>
SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);<br>
- AddToWorklist(NotX.getNode());<br>
return DAG.getNode(ISD::AND, DL, VT, NotX, N1);<br>
}<br>
<br>
@@ -7279,8 +7240,6 @@ SDValue DAGCombiner::distributeTruncateT<br>
SDValue N00 = N->getOperand(0).getOperand(0);<br>
SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00);<br>
SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01);<br>
- AddToWorklist(Trunc00.getNode());<br>
- AddToWorklist(Trunc01.getNode());<br>
return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01);<br>
}<br>
}<br>
@@ -7501,7 +7460,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N)<br>
EVT InnerShiftAmtVT = N0Op0.getOperand(1).getValueType();<br>
SDValue NewSHL = DAG.getZExtOrTrunc(N1, DL, InnerShiftAmtVT);<br>
NewSHL = DAG.getNode(ISD::SHL, DL, N0Op0.getValueType(), N0Op0, NewSHL);<br>
- AddToWorklist(NewSHL.getNode());<br>
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);<br>
}<br>
}<br>
@@ -7575,8 +7533,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N)<br>
TLI.isDesirableToCommuteWithShift(N, Level)) {<br>
SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);<br>
SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);<br>
- AddToWorklist(Shl0.getNode());<br>
- AddToWorklist(Shl1.getNode());<br>
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1);<br>
}<br>
<br>
@@ -7875,7 +7831,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N)<br>
SDLoc DL(N);<br>
SDValue Mask =<br>
DAG.getNode(ISD::SRL, DL, VT, DAG.getAllOnesConstant(DL, VT), N1);<br>
- AddToWorklist(Mask.getNode());<br>
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), Mask);<br>
}<br>
<br>
@@ -7895,7 +7850,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N)<br>
N0.getOperand(0),<br>
DAG.getConstant(ShiftAmt, DL0,<br>
getShiftAmountTy(SmallVT)));<br>
- AddToWorklist(SmallShift.getNode());<br>
APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt);<br>
SDLoc DL(N);<br>
return DAG.getNode(ISD::AND, DL, VT,<br>
@@ -7939,7 +7893,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N)<br>
Op = DAG.getNode(ISD::SRL, DL, VT, Op,<br>
DAG.getConstant(ShAmt, DL,<br>
getShiftAmountTy(Op.getValueType())));<br>
- AddToWorklist(Op.getNode());<br>
}<br>
<br>
SDLoc DL(N);<br>
@@ -8360,13 +8313,11 @@ SDValue DAGCombiner::visitSELECT(SDNode<br>
// fold (select C, 0, X) -> (and (not C), X)<br>
if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) {<br>
SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);<br>
- AddToWorklist(NOTNode.getNode());<br>
return DAG.getNode(ISD::AND, DL, VT, NOTNode, N2);<br>
}<br>
// fold (select C, X, 1) -> (or (not C), X)<br>
if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) {<br>
SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);<br>
- AddToWorklist(NOTNode.getNode());<br>
return DAG.getNode(ISD::OR, DL, VT, NOTNode, N1);<br>
}<br>
// fold (select X, Y, X) -> (and X, Y)<br>
@@ -8722,8 +8673,6 @@ SDValue DAGCombiner::visitVSELECT(SDNode<br>
ISD::SRA, DL, VT, LHS,<br>
DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT));<br>
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);<br>
- AddToWorklist(Shift.getNode());<br>
- AddToWorklist(Add.getNode());<br>
return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);<br>
}<br>
<br>
@@ -9696,7 +9645,6 @@ SDValue DAGCombiner::visitZERO_EXTEND(SD<br>
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {<br>
SDValue Op = N0.getOperand(0);<br>
Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());<br>
- AddToWorklist(Op.getNode());<br>
SDValue ZExtOrTrunc = DAG.getZExtOrTrunc(Op, SDLoc(N), VT);<br>
// Transfer the debug info; the new node is equivalent to N0.<br>
DAG.transferDbgValues(N0, ZExtOrTrunc);<br>
@@ -9706,7 +9654,6 @@ SDValue DAGCombiner::visitZERO_EXTEND(SD<br>
<br>
if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) {<br>
SDValue Op = DAG.getAnyExtOrTrunc(N0.getOperand(0), SDLoc(N), VT);<br>
- AddToWorklist(Op.getNode());<br>
SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());<br>
// We may safely transfer the debug info describing the truncate node over<br>
// to the equivalent and operation.<br>
@@ -10247,7 +10194,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDN<br>
PtrType, LN0->getBasePtr(),<br>
DAG.getConstant(PtrOff, DL, PtrType),<br>
Flags);<br>
- AddToWorklist(NewPtr.getNode());<br>
<br>
SDValue Load;<br>
if (ExtType == ISD::NON_EXTLOAD)<br>
@@ -10405,7 +10351,6 @@ SDValue DAGCombiner::visitSIGN_EXTEND_IN<br>
LN0->getMemOperand());<br>
CombineTo(N, ExtLoad);<br>
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));<br>
- AddToWorklist(ExtLoad.getNode());<br>
return SDValue(N, 0); // Return N so it doesn't get rechecked!<br>
}<br>
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use<br>
@@ -10566,10 +10511,8 @@ SDValue DAGCombiner::visitTRUNCATE(SDNod<br>
EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());<br>
<br>
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));<br>
- if (AmtVT != Amt.getValueType()) {<br>
+ if (AmtVT != Amt.getValueType())<br>
Amt = DAG.getZExtOrTrunc(Amt, SL, AmtVT);<br>
- AddToWorklist(Amt.getNode());<br>
- }<br>
return DAG.getNode(ISD::SHL, SL, VT, Trunc, Amt);<br>
}<br>
}<br>
@@ -10686,7 +10629,6 @@ SDValue DAGCombiner::visitTRUNCATE(SDNod<br>
continue;<br>
}<br>
SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);<br>
- AddToWorklist(NV.getNode());<br>
Opnds.push_back(NV);<br>
}<br>
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);<br>
@@ -10968,7 +10910,6 @@ SDValue DAGCombiner::visitBITCAST(SDNode<br>
N0.getNode()->hasOneUse() && VT.isInteger() &&<br>
!VT.isVector() && !N0.getValueType().isVector()) {<br>
SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0));<br>
- AddToWorklist(NewConv.getNode());<br>
<br>
SDLoc DL(N);<br>
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {<br>
@@ -10978,20 +10919,16 @@ SDValue DAGCombiner::visitBITCAST(SDNode<br>
SDValue FlipBit;<br>
if (N0.getOpcode() == ISD::FNEG) {<br>
FlipBit = SignBit;<br>
- AddToWorklist(FlipBit.getNode());<br>
} else {<br>
assert(N0.getOpcode() == ISD::FABS);<br>
SDValue Hi =<br>
DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(NewConv), MVT::i64, NewConv,<br>
DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG),<br>
SDLoc(NewConv)));<br>
- AddToWorklist(Hi.getNode());<br>
FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit);<br>
- AddToWorklist(FlipBit.getNode());<br>
}<br>
SDValue FlipBits =<br>
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);<br>
- AddToWorklist(FlipBits.getNode());<br>
return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits);<br>
}<br>
APInt SignBit = APInt::getSignMask(VT.getSizeInBits());<br>
@@ -11021,12 +10958,13 @@ SDValue DAGCombiner::visitBITCAST(SDNode<br>
EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);<br>
if (isTypeLegal(IntXVT)) {<br>
SDValue X = DAG.getBitcast(IntXVT, N0.getOperand(1));<br>
- AddToWorklist(X.getNode());<br>
<br>
// If X has a different width than the result/lhs, sext it or truncate it.<br>
unsigned VTWidth = VT.getSizeInBits();<br>
if (OrigXWidth < VTWidth) {<br>
X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);<br>
+ // TODO: This call to AddToWorklist is likely redundent, but was not<br>
+ // removed due to lack of test coverage.<br>
AddToWorklist(X.getNode());<br>
} else if (OrigXWidth > VTWidth) {<br>
// To get the sign bit in the right place, we have to shift it right<br>
@@ -11036,42 +10974,38 @@ SDValue DAGCombiner::visitBITCAST(SDNode<br>
X.getValueType(), X,<br>
DAG.getConstant(OrigXWidth-VTWidth, DL,<br>
X.getValueType()));<br>
+ // TODO: This call to AddToWorklist is likely redundent, but was not<br>
+ // removed due to lack of test coverage.<br>
AddToWorklist(X.getNode());<br>
X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);<br>
+ // TODO: This call to AddToWorklist is likely redundent, but was not<br>
+ // removed due to lack of test coverage.<br>
AddToWorklist(X.getNode());<br>
}<br>
<br>
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {<br>
APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2);<br>
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));<br>
- AddToWorklist(Cst.getNode());<br>
SDValue X = DAG.getBitcast(VT, N0.getOperand(1));<br>
- AddToWorklist(X.getNode());<br>
SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X);<br>
- AddToWorklist(XorResult.getNode());<br>
SDValue XorResult64 = DAG.getNode(<br>
ISD::EXTRACT_ELEMENT, SDLoc(XorResult), MVT::i64, XorResult,<br>
DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG),<br>
SDLoc(XorResult)));<br>
- AddToWorklist(XorResult64.getNode());<br>
SDValue FlipBit =<br>
DAG.getNode(ISD::AND, SDLoc(XorResult64), MVT::i64, XorResult64,<br>
DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64));<br>
- AddToWorklist(FlipBit.getNode());<br>
SDValue FlipBits =<br>
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);<br>
- AddToWorklist(FlipBits.getNode());<br>
return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits);<br>
}<br>
APInt SignBit = APInt::getSignMask(VT.getSizeInBits());<br>
X = DAG.getNode(ISD::AND, SDLoc(X), VT,<br>
X, DAG.getConstant(SignBit, SDLoc(X), VT));<br>
- AddToWorklist(X.getNode());<br>
<br>
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));<br>
Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,<br>
Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT));<br>
- AddToWorklist(Cst.getNode());<br>
<br>
return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);<br>
}<br>
@@ -11160,7 +11094,6 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode<br>
if (Op.getValueType() != SrcEltVT)<br>
Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);<br>
Ops.push_back(DAG.getBitcast(DstEltVT, Op));<br>
- AddToWorklist(Ops.back().getNode());<br>
}<br>
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,<br>
BV->getValueType(0).getVectorNumElements());<br>
@@ -12026,10 +11959,9 @@ SDValue DAGCombiner::visitFADD(SDNode *N<br>
} // enable-unsafe-fp-math<br>
<br>
// FADD -> FMA combines:<br>
- if (SDValue Fused = visitFADDForFMACombine(N)) {<br>
- AddToWorklist(Fused.getNode());<br>
+ if (SDValue Fused = visitFADDForFMACombine(N))<br>
return Fused;<br>
- }<br>
+<br>
return SDValue();<br>
}<br>
<br>
@@ -12102,10 +12034,8 @@ SDValue DAGCombiner::visitFSUB(SDNode *N<br>
ForCodeSize), Flags);<br>
<br>
// FSUB -> FMA combines:<br>
- if (SDValue Fused = visitFSUBForFMACombine(N)) {<br>
- AddToWorklist(Fused.getNode());<br>
+ if (SDValue Fused = visitFSUBForFMACombine(N))<br>
return Fused;<br>
- }<br>
<br>
return SDValue();<br>
}<br>
@@ -12244,10 +12174,8 @@ SDValue DAGCombiner::visitFMUL(SDNode *N<br>
}<br>
<br>
// FMUL -> FMA combines:<br>
- if (SDValue Fused = visitFMULForFMADistributiveCombine(N)) {<br>
- AddToWorklist(Fused.getNode());<br>
+ if (SDValue Fused = visitFMULForFMADistributiveCombine(N))<br>
return Fused;<br>
- }<br>
<br>
return SDValue();<br>
}<br>
@@ -12322,7 +12250,6 @@ SDValue DAGCombiner::visitFMA(SDNode *N)<br>
if (N1CFP->isExactlyValue(-1.0) &&<br>
(!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {<br>
SDValue RHSNeg = DAG.getNode(ISD::FNEG, DL, VT, N0);<br>
- AddToWorklist(RHSNeg.getNode());<br>
// TODO: The FMA node should have flags that propagate to this node.<br>
return DAG.getNode(ISD::FADD, DL, VT, N2, RHSNeg);<br>
}<br>
@@ -12487,7 +12414,6 @@ SDValue DAGCombiner::visitFDIV(SDNode *N<br>
if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0).getOperand(0),<br>
Flags)) {<br>
RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);<br>
- AddToWorklist(RV.getNode());<br>
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);<br>
}<br>
} else if (N1.getOpcode() == ISD::FP_ROUND &&<br>
@@ -12495,7 +12421,6 @@ SDValue DAGCombiner::visitFDIV(SDNode *N<br>
if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0).getOperand(0),<br>
Flags)) {<br>
RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));<br>
- AddToWorklist(RV.getNode());<br>
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);<br>
}<br>
} else if (N1.getOpcode() == ISD::FMUL) {<br>
@@ -12515,17 +12440,14 @@ SDValue DAGCombiner::visitFDIV(SDNode *N<br>
// x / (y * sqrt(z)) -> x * (rsqrt(z) / y)<br>
if (SDValue RV = buildRsqrtEstimate(SqrtOp.getOperand(0), Flags)) {<br>
RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp, Flags);<br>
- AddToWorklist(RV.getNode());<br>
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);<br>
}<br>
}<br>
}<br>
<br>
// Fold into a reciprocal estimate and multiply instead of a real divide.<br>
- if (SDValue RV = BuildReciprocalEstimate(N1, Flags)) {<br>
- AddToWorklist(RV.getNode());<br>
+ if (SDValue RV = BuildReciprocalEstimate(N1, Flags))<br>
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);<br>
- }<br>
}<br>
<br>
// (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)<br>
@@ -12978,7 +12900,6 @@ SDValue DAGCombiner::visitFP_ROUND(SDNod<br>
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {<br>
SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,<br>
N0.getOperand(0), N1);<br>
- AddToWorklist(Tmp.getNode());<br>
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,<br>
Tmp, N0.getOperand(1));<br>
}<br>
@@ -13138,7 +13059,6 @@ SDValue DAGCombiner::visitFNEG(SDNode *N<br>
SDLoc DL0(N0);<br>
Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int,<br>
DAG.getConstant(SignMask, DL0, IntVT));<br>
- AddToWorklist(Int.getNode());<br>
return DAG.getBitcast(VT, Int);<br>
}<br>
}<br>
@@ -13236,7 +13156,6 @@ SDValue DAGCombiner::visitFABS(SDNode *N<br>
SDLoc DL(N0);<br>
Int = DAG.getNode(ISD::AND, DL, IntVT, Int,<br>
DAG.getConstant(SignMask, DL, IntVT));<br>
- AddToWorklist(Int.getNode());<br>
return DAG.getBitcast(N->getValueType(0), Int);<br>
}<br>
}<br>
@@ -14888,9 +14807,6 @@ SDValue DAGCombiner::ReduceLoadOpStoreWi<br>
DAG.getStore(Chain, SDLoc(N), NewVal, NewPtr,<br>
ST->getPointerInfo().getWithOffset(PtrOff), NewAlign);<br>
<br>
- AddToWorklist(NewPtr.getNode());<br>
- AddToWorklist(NewLD.getNode());<br>
- AddToWorklist(NewVal.getNode());<br>
WorklistRemover DeadNodes(*this);<br>
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));<br>
++OpsNarrowed;<br>
@@ -16137,7 +16053,6 @@ SDValue DAGCombiner::visitSTORE(SDNode *<br>
// See if we can simplify the input to this truncstore with knowledge that<br>
// only the low bits are being used. For example:<br>
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"<br>
- AddToWorklist(Value.getNode());<br>
if (SDValue Shorter = DAG.GetDemandedBits(Value, TruncDemandedBits))<br>
return DAG.getTruncStore(Chain, SDLoc(N), Shorter, Ptr, ST->getMemoryVT(),<br>
ST->getMemOperand());<br>
@@ -16472,9 +16387,6 @@ SDValue DAGCombiner::combineInsertEltToS<br>
// Step 3: Shuffle in the padded subvector.<br>
SDValue DestVecBC = DAG.getBitcast(ShufVT, DestVec);<br>
SDValue Shuf = DAG.getVectorShuffle(ShufVT, DL, DestVecBC, PaddedSubV, Mask);<br>
- AddToWorklist(PaddedSubV.getNode());<br>
- AddToWorklist(DestVecBC.getNode());<br>
- AddToWorklist(Shuf.getNode());<br>
return DAG.getBitcast(VT, Shuf);<br>
}<br>
<br>
@@ -16527,7 +16439,6 @@ SDValue DAGCombiner::visitINSERT_VECTOR_<br>
// Swap nodes.<br>
SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT,<br>
InVec.getOperand(0), InVal, EltNo);<br>
- AddToWorklist(NewOp.getNode());<br>
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),<br>
VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));<br>
}<br>
@@ -17052,8 +16963,6 @@ SDValue DAGCombiner::reduceBuildVecExtTo<br>
// Make the new BUILD_VECTOR.<br>
SDValue BV = DAG.getBuildVector(VecVT, DL, Ops);<br>
<br>
- // The new BUILD_VECTOR node has the potential to be further optimized.<br>
- AddToWorklist(BV.getNode());<br>
// Bitcast to the desired type.<br>
return DAG.getBitcast(VT, BV);<br>
}<br>
@@ -19257,6 +19166,8 @@ SDValue DAGCombiner::visitINSERT_SUBVECT<br>
// Swap nodes.<br>
SDValue NewOp = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT,<br>
N0.getOperand(0), N1, N2);<br>
+ // TODO: This call to AddToWorklist is likely redundent, but was not<br>
+ // removed due to lack of test coverage.<br>
AddToWorklist(NewOp.getNode());<br>
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()),<br>
VT, NewOp, N0.getOperand(1), N0.getOperand(2));<br>
@@ -19593,6 +19504,8 @@ SDValue DAGCombiner::SimplifySelect(cons<br>
N0.getValueType(),<br>
SCC.getOperand(0), SCC.getOperand(1),<br>
SCC.getOperand(4), Flags);<br>
+ // TODO: This call to AddToWorklist is likely redundent, but was not<br>
+ // removed due to lack of test coverage.<br>
AddToWorklist(SETCC.getNode());<br>
SDValue SelectNode = DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,<br>
SCC.getOperand(2), SCC.getOperand(3));<br>
@@ -19834,12 +19747,9 @@ SDValue DAGCombiner::foldSelectCCToShift<br>
unsigned ShCt = XType.getSizeInBits() - N2C->getAPIntValue().logBase2() - 1;<br>
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);<br>
SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);<br>
- AddToWorklist(Shift.getNode());<br>
<br>
- if (XType.bitsGT(AType)) {<br>
+ if (XType.bitsGT(AType))<br>
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);<br>
- AddToWorklist(Shift.getNode());<br>
- }<br>
<br>
if (CC == ISD::SETGT)<br>
Shift = DAG.getNOT(DL, Shift, AType);<br>
@@ -19849,12 +19759,9 @@ SDValue DAGCombiner::foldSelectCCToShift<br>
<br>
SDValue ShiftAmt = DAG.getConstant(XType.getSizeInBits() - 1, DL, ShiftAmtTy);<br>
SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);<br>
- AddToWorklist(Shift.getNode());<br>
<br>
- if (XType.bitsGT(AType)) {<br>
+ if (XType.bitsGT(AType))<br>
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);<br>
- AddToWorklist(Shift.getNode());<br>
- }<br>
<br>
if (CC == ISD::SETGT)<br>
Shift = DAG.getNOT(DL, Shift, AType);<br>
@@ -19909,11 +19816,8 @@ SDValue DAGCombiner::convertSelectOfFPCo<br>
SDValue One = DAG.getIntPtrConstant(EltSize, SDLoc(FV));<br>
SDValue Cond =<br>
DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), N0, N1, CC);<br>
- AddToWorklist(Cond.getNode());<br>
SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(), Cond, One, Zero);<br>
- AddToWorklist(CstOffset.getNode());<br>
CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx, CstOffset);<br>
- AddToWorklist(CPIdx.getNode());<br>
return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,<br>
MachinePointerInfo::getConstantPool(<br>
DAG.getMachineFunction()), Alignment);<br>
@@ -20012,9 +19916,6 @@ SDValue DAGCombiner::SimplifySelectCC(co<br>
Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);<br>
}<br>
<br>
- AddToWorklist(SCC.getNode());<br>
- AddToWorklist(Temp.getNode());<br>
-<br>
if (N2C->isOne())<br>
return Temp;<br>
<br>
@@ -20169,8 +20070,6 @@ SDValue DAGCombiner::BuildReciprocalEsti<br>
// refinement steps.<br>
int Iterations = TLI.getDivRefinementSteps(VT, MF);<br>
if (SDValue Est = TLI.getRecipEstimate(Op, DAG, Enabled, Iterations)) {<br>
- AddToWorklist(Est.getNode());<br>
-<br>
if (Iterations) {<br>
SDLoc DL(Op);<br>
SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);<br>
<br>
<br>
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