<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Jul 31, 2019 at 6:32 PM Stanislav Mekhanoshin via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: rampitec<br>
Date: Wed Jul 31 09:33:11 2019<br>
New Revision: 367443<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=367443&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=367443&view=rev</a><br>
Log:<br>
[AMDGPU] Fix for vectorizer crash with pointers of different size<br>
<br>
When vectorizer strips pointers it can eventually end up with<br>
pointers of two different sizes, then SCEV will crash.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D65480" rel="noreferrer" target="_blank">https://reviews.llvm.org/D65480</a><br>
<br>
Added:<br>
    llvm/trunk/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll<br>
Modified:<br>
    llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp<br>
<br>
Modified: llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp?rev=367443&r1=367442&r2=367443&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp?rev=367443&r1=367442&r2=367443&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp Wed Jul 31 09:33:11 2019<br>
@@ -339,11 +339,16 @@ bool Vectorizer::areConsecutivePointers(<br>
                                         const APInt &PtrDelta,<br>
                                         unsigned Depth) const {<br>
   unsigned PtrBitWidth = DL.getPointerTypeSizeInBits(PtrA->getType());<br>
+  unsigned PtrAS = PtrA->getType()->getPointerAddressSpace();<br>
   APInt OffsetA(PtrBitWidth, 0);<br>
   APInt OffsetB(PtrBitWidth, 0);<br>
   PtrA = PtrA->stripAndAccumulateInBoundsConstantOffsets(DL, OffsetA);<br>
   PtrB = PtrB->stripAndAccumulateInBoundsConstantOffsets(DL, OffsetB);<br>
<br>
+  if (PtrA->getType()->getPointerAddressSpace() != PtrAS ||<br>
+      PtrB->getType()->getPointerAddressSpace() != PtrAS)<br>
+    return false;<br></blockquote><div><br></div><div>This is too aggressive, it will prevent any pointer pair that's addrspacecast'ed from ever being recognized as consecutive. What's the reason for not checking the size? I'm seeing regressions where pointers are getting loaded from memory and then casted to the right addresspace.</div><div><br></div><div>- Ben</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+<br>
   APInt OffsetDelta = OffsetB - OffsetA;<br>
<br>
   // Check if they are based on the same pointer. That makes the offsets<br>
<br>
Added: llvm/trunk/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll?rev=367443&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll?rev=367443&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll (added)<br>
+++ llvm/trunk/test/Transforms/LoadStoreVectorizer/AMDGPU/vect-ptr-ptr-size-mismatch.ll Wed Jul 31 09:33:11 2019<br>
@@ -0,0 +1,18 @@<br>
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -load-store-vectorizer -S < %s | FileCheck %s<br>
+<br>
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32"<br>
+<br>
+; CHECK-LABEL: @test<br>
+; CHECK: store i32* undef, i32** %tmp9, align 8<br>
+; CHECK: store i32* undef, i32** %tmp7, align 8<br>
+define amdgpu_kernel void @test() {<br>
+entry:<br>
+  %a10.ascast.i = addrspacecast i32* addrspace(5)* null to i32**<br>
+  %tmp4 = icmp eq i32 undef, 0<br>
+  %tmp6 = select i1 false, i32** undef, i32** undef<br>
+  %tmp7 = select i1 %tmp4, i32** null, i32** %tmp6<br>
+  %tmp9 = select i1 %tmp4, i32** %a10.ascast.i, i32** null<br>
+  store i32* undef, i32** %tmp9, align 8<br>
+  store i32* undef, i32** %tmp7, align 8<br>
+  unreachable<br>
+}<br>
<br>
<br>
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</blockquote></div></div>