<div dir="ltr">Yes, that seems to fix the test case, at least with a stage1 build. (The stage2 is chugging along very slowly...) Would you like me to commit it or did you want to commit it along with a test case?<div><br><div>Thanks!</div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Jul 9, 2019 at 4:44 PM Topper, Craig <<a href="mailto:craig.topper@intel.com">craig.topper@intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div lang="EN-US">
<div class="gmail-m_-7713438526913434753WordSection1">
<p class="MsoNormal">Can you try this patch and see if it helps?<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp<u></u><u></u></p>
<p class="MsoNormal">index 40e3070..2812b08 100644<u></u><u></u></p>
<p class="MsoNormal">--- a/llvm/lib/Target/X86/X86ISelLowering.cpp<u></u><u></u></p>
<p class="MsoNormal">+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp<u></u><u></u></p>
<p class="MsoNormal">@@ -5788,7 +5788,7 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, int Idx,<u></u><u></u></p>
<p class="MsoNormal">}<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">static const Constant *getTargetConstantFromNode(LoadSDNode *Load) {<u></u><u></u></p>
<p class="MsoNormal">- if (!Load)<u></u><u></u></p>
<p class="MsoNormal">+ if (!Load || !ISD::isNormalLoad(Load))<u></u><u></u></p>
<p class="MsoNormal"> return nullptr;<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"> SDValue Ptr = Load->getBasePtr();<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"><a name="m_-7713438526913434753______replyseparator"></a><b>From:</b> Jordan Rupprecht <<a href="mailto:rupprecht@google.com" target="_blank">rupprecht@google.com</a>>
<br>
<b>Sent:</b> Tuesday, July 9, 2019 4:28 PM<br>
<b>To:</b> Topper, Craig <<a href="mailto:craig.topper@intel.com" target="_blank">craig.topper@intel.com</a>><br>
<b>Cc:</b> llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>><br>
<b>Subject:</b> Re: [llvm] r364977 - [X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">Sure:<u></u><u></u></p>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"> .LCPI3_0:<br>
- .quad 12884901889 # 0x300000001<br>
- .quad 12884901889 # 0x300000001<br>
-.LCPI3_1:<br>
- .quad 1 # 0x1<br>
- .quad 1 # 0x1<br>
-.LCPI3_2:<br>
- .quad 8 # 0x8<br>
- .quad 8 # 0x8<br>
-.LCPI3_6:<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 8 # 0x8<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+ .byte 0 # 0x0<br>
+.LCPI3_4:<br>
.zero 16,205<br>
.section .rodata.cst4,"aM",@progbits,4<br>
.p2align 2<br>
-.LCPI3_3:<br>
+.LCPI3_1:<br>
.long 1066192077 # float 1.10000002<br>
-.LCPI3_4:<br>
+.LCPI3_2:<br>
.long 1067030938 # float 1.20000005<br>
-.LCPI3_5:<br>
+.LCPI3_3:<br>
.long 1067869798 # float 1.29999995<br>
.section .text,"ax",@progbits,unique,4<br>
.globl _ZN35FloatArrayTest_SomeAllowedMask_Test8TestBodyEv<br>
.p2align 5, 0x90<br>
.type _ZN35FloatArrayTest_SomeAllowedMask_Test8TestBodyEv,@function<br>
_ZN35FloatArrayTest_SomeAllowedMask_Test8TestBodyEv: # @_ZN35FloatArrayTest_SomeAllowedMask_Test8TestBodyEv <br>
.cfi_startproc<br>
# %bb.0:<u></u><u></u></p>
</div>
</div>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<div>
<p class="MsoNormal">On Tue, Jul 9, 2019 at 4:25 PM Topper, Craig <<a href="mailto:craig.topper@intel.com" target="_blank">craig.topper@intel.com</a>> wrote:<u></u><u></u></p>
</div>
<blockquote style="border-top:none;border-right:none;border-bottom:none;border-left:1pt solid rgb(204,204,204);padding:0in 0in 0in 6pt;margin-left:4.8pt;margin-right:0in">
<div>
<div>
<p class="MsoNormal">Ca you also send the values for the 3 constant pool entries before and after the change
<span style="font-size:12pt;font-family:Arial,sans-serif;color:rgb(34,34,34);background:white">
LCPI3_0, </span>LCPI3_1, and LCPI3_2.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal"><a name="m_-7713438526913434753_m_-6451203015682045683______replyseparat"></a><b>From:</b> Jordan Rupprecht <<a href="mailto:rupprecht@google.com" target="_blank">rupprecht@google.com</a>>
<br>
<b>Sent:</b> Tuesday, July 9, 2019 4:21 PM<br>
<b>To:</b> Topper, Craig <<a href="mailto:craig.topper@intel.com" target="_blank">craig.topper@intel.com</a>><br>
<b>Cc:</b> llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>><br>
<b>Subject:</b> Re: [llvm] r364977 - [X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<div>
<p class="MsoNormal">I have the C++ code reduced to this:<u></u><u></u></p>
<div>
<p class="MsoNormal"><br>
#include <array><br>
#include <vector><br>
<br>
#include "gtest/gtest.h"<br>
<br>
using FloatArray = std::array<float, 8>;<br>
<br>
class Bitmap {<br>
public:<br>
Bitmap() : bitmap_(0) {}<br>
explicit Bitmap(int bitmap) : bitmap_(bitmap) {}<br>
bool Get(int index) const { return bitmap_ & (1 << index); }<br>
void Set(int index) { bitmap_ |= (1 << index); }<br>
<br>
private:<br>
int bitmap_;<br>
};<br>
<br>
const FloatArray MaskFloatArray(const FloatArray& input_array,<br>
Bitmap mask_types) {<br>
FloatArray tmp_array;<br>
for (size_t i = 0; i < 8; ++i)<br>
tmp_array[i] = mask_types.Get(i) ? input_array[i] : 0;<br>
return tmp_array;<br>
}<br>
<br>
namespace {<br>
<br>
Bitmap FromIndexesBitmap(const std::vector<int>& indexes) {<br>
Bitmap bm;<br>
for (size_t i = 0; i < indexes.size(); ++i) bm.Set(indexes[i]);<br>
return bm;<br>
}<br>
<br>
} // namespace<br>
<br>
TEST(FloatArrayTest, AllAllowedMask) {<br>
FloatArray input = {{0, 1.1, 1.2, 1.3}};<br>
const FloatArray output =<br>
MaskFloatArray(input, FromIndexesBitmap({0, 1, 2, 3, 4}));<br>
EXPECT_EQ(output, input);<br>
}<br>
<br>
TEST(FloatArrayTest, SomeAllowedMask) {<br>
FloatArray input = {{0, 1.1, 1.2, 1.3}};<br>
const FloatArray output = MaskFloatArray(input, FromIndexesBitmap({1, 3}));<br>
<br>
FloatArray expected_output = {{0, 1.1, 0, 1.3}};<br>
EXPECT_EQ(output, expected_output);<br>
}<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> <u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">With the test failure being the mismatch in SomeAllowedMask:<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">Expected equality of these values:<br>
output<br>
Which is: { 0, 0, 0, 1.3, 0, 0, 0, 0 }<br>
expected_output<br>
Which is: { 0, 1.1, 0, 1.3, 0, 0, 0, 0 }<br>
Stack trace:<br>
0x5650b1e08424: FloatArrayTest_SomeAllowedMask_Test::TestBody() @ ../sysdeps/x86_64/start.S:121<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> <u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">The major difference seems to be the generated assembly for the test body:<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> FloatArrayTest_SomeAllowedMask_Test::TestBody(): # @FloatArrayTest_SomeAllowedMask_Test::TestBody()<br>
.cfi_startproc<br>
# %bb.0:<br>
pushq %rbp<br>
.cfi_def_cfa_offset 16<br>
.cfi_offset %rbp, -16<br>
movq %rsp, %rbp<br>
.cfi_def_cfa_register %rbp<br>
pushq %rbx<br>
subq $104, %rsp<br>
.cfi_offset %rbx, -24<br>
movl $8, %edi<br>
callq operator new(unsigned long)@PLT<br>
movabsq $12884901889, %rcx # imm = 0x300000001<br>
- pmovzxdq .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,mem[1],zero<br>
- movdqa .LCPI3_1(%rip), %xmm1 # xmm1 = [1,1]<br>
- psllq %xmm0, %xmm1<br>
- pblendw $240, .LCPI3_2(%rip), %xmm1 # xmm1 = xmm1[0,1,2,3],mem[4,5,6,7]<br>
movq %rcx, (%rax)<br>
- pshufd $78, %xmm1, %xmm0 # xmm0 = xmm1[2,3,0,1]<br>
- por %xmm1, %xmm0<br>
+ movl $8, %ecx<br>
+ movd %ecx, %xmm0<br>
+ por .LCPI3_0(%rip), %xmm0<br>
movd %xmm0, %ecx<br>
movl $0, -64(%rbp)<br>
pxor %xmm0, %xmm0<br>
- pxor %xmm1, %xmm1<br>
+ xorps %xmm1, %xmm1<br>
testb $2, %cl<br>
jne .LBB3_1<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> <u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">Sadly I can't get this to reproduce outside of our internal testing setup. Is the above enough for you to make sense of the test failure cause?<u></u><u></u></p>
</div>
</div>
<p class="MsoNormal"> <u></u><u></u></p>
<div>
<div>
<p class="MsoNormal">On Tue, Jul 9, 2019 at 11:02 AM Jordan Rupprecht <<a href="mailto:rupprecht@google.com" target="_blank">rupprecht@google.com</a>> wrote:<u></u><u></u></p>
</div>
<blockquote style="border-top:none;border-right:none;border-bottom:none;border-left:1pt solid rgb(204,204,204);padding:0in 0in 0in 6pt;margin:5pt 0in 5pt 4.8pt">
<div>
<p class="MsoNormal">I'm still pruning down the list of what's required to trigger it, but the features we're building with are: "-msse4.2 -mpclmul -maes"<u></u><u></u></p>
</div>
<p class="MsoNormal"> <u></u><u></u></p>
<div>
<div>
<p class="MsoNormal">On Tue, Jul 9, 2019 at 10:56 AM Topper, Craig <<a href="mailto:craig.topper@intel.com" target="_blank">craig.topper@intel.com</a>> wrote:<u></u><u></u></p>
</div>
<blockquote style="border-top:none;border-right:none;border-bottom:none;border-left:1pt solid rgb(204,204,204);padding:0in 0in 0in 6pt;margin:5pt 0in 5pt 4.8pt">
<div>
<div>
<p class="MsoNormal">Do you know what ISA features its being compiled for? I think I shouldn’t be doing this unless at least SSE4.1 is supported, but I don’t know if that would cause a failure.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal"><a name="m_-7713438526913434753_m_-6451203015682045683_m_-64548489555038"></a><b>From:</b> Jordan Rupprecht <<a href="mailto:rupprecht@google.com" target="_blank">rupprecht@google.com</a>>
<br>
<b>Sent:</b> Monday, July 8, 2019 4:34 PM<br>
<b>To:</b> Topper, Craig <<a href="mailto:craig.topper@intel.com" target="_blank">craig.topper@intel.com</a>><br>
<b>Cc:</b> llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>><br>
<b>Subject:</b> Re: [llvm] r364977 - [X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<div>
<p class="MsoNormal">FYI, we're seeing some kinda strange test failures after this patch. I'm unable to get a reproducer, but it's on some utility code that is (at a very high level) implementing a
vector<bool>-type thing, and is now returning 0 for some elements that were previously set.<u></u><u></u></p>
</div>
<p class="MsoNormal"> <u></u><u></u></p>
<div>
<div>
<p class="MsoNormal">On Tue, Jul 2, 2019 at 4:20 PM Craig Topper via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<u></u><u></u></p>
</div>
<blockquote style="border-top:none;border-right:none;border-bottom:none;border-left:1pt solid rgb(204,204,204);padding:0in 0in 0in 6pt;margin:5pt 0in 5pt 4.8pt">
<p class="MsoNormal">Author: ctopper<br>
Date: Tue Jul 2 16:20:03 2019<br>
New Revision: 364977<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=364977&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=364977&view=rev</a><br>
Log:<br>
[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.<br>
<br>
Remove the corresponding isel patterns that did the same thing without checking for volatile.<br>
<br>
This fixes another variation of PR42079<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=364977&r1=364976&r2=364977&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=364977&r1=364976&r2=364977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 2 16:20:03 2019<br>
@@ -1876,6 +1876,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setTargetDAGCombine(ISD::SIGN_EXTEND);<br>
setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);<br>
setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);<br>
+ setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);<br>
setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);<br>
setTargetDAGCombine(ISD::SINT_TO_FP);<br>
setTargetDAGCombine(ISD::UINT_TO_FP);<br>
@@ -43914,16 +43915,35 @@ static SDValue combinePMULDQ(SDNode *N,<br>
}<br>
<br>
static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,<br>
+ TargetLowering::DAGCombinerInfo &DCI,<br>
const X86Subtarget &Subtarget) {<br>
+ EVT VT = N->getValueType(0);<br>
+ SDValue In = N->getOperand(0);<br>
+<br>
+ // Try to merge vector loads and extend_inreg to an extload.<br>
+ if (!DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(In.getNode()) &&<br>
+ In.hasOneUse()) {<br>
+ auto *Ld = cast<LoadSDNode>(In);<br>
+ if (!Ld->isVolatile()) {<br>
+ MVT SVT = In.getSimpleValueType().getVectorElementType();<br>
+ ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;<br>
+ EVT MemVT = EVT::getVectorVT(*DAG.getContext(), SVT,<br>
+ VT.getVectorNumElements());<br>
+ SDValue Load =<br>
+ DAG.getExtLoad(Ext, SDLoc(N), VT, Ld->getChain(), Ld->getBasePtr(),<br>
+ Ld->getPointerInfo(), MemVT, Ld->getAlignment(),<br>
+ Ld->getMemOperand()->getFlags());<br>
+ DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));<br>
+ return Load;<br>
+ }<br>
+ }<br>
+<br>
// Disabling for widening legalization for now. We can enable if we find a<br>
// case that needs it. Otherwise it can be deleted when we switch to<br>
// widening legalization.<br>
if (ExperimentalVectorWideningLegalization)<br>
return SDValue();<br>
<br>
- EVT VT = N->getValueType(0);<br>
- SDValue In = N->getOperand(0);<br>
-<br>
// Combine (ext_invec (ext_invec X)) -> (ext_invec X)<br>
const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
if (In.getOpcode() == N->getOpcode() &&<br>
@@ -43932,7 +43952,7 @@ static SDValue combineExtInVec(SDNode *N<br>
<br>
// Attempt to combine as a shuffle.<br>
// TODO: SSE41 support<br>
- if (Subtarget.hasAVX()) {<br>
+ if (Subtarget.hasAVX() && N->getOpcode() != ISD::SIGN_EXTEND_VECTOR_INREG) {<br>
SDValue Op(N, 0);<br>
if (TLI.isTypeLegal(VT) && TLI.isTypeLegal(In.getValueType()))<br>
if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))<br>
@@ -44010,7 +44030,9 @@ SDValue X86TargetLowering::PerformDAGCom<br>
case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget);<br>
case ISD::SIGN_EXTEND_INREG: return combineSignExtendInReg(N, DAG, Subtarget);<br>
case ISD::ANY_EXTEND_VECTOR_INREG:<br>
- case ISD::ZERO_EXTEND_VECTOR_INREG: return combineExtInVec(N, DAG, Subtarget);<br>
+ case ISD::SIGN_EXTEND_VECTOR_INREG:<br>
+ case ISD::ZERO_EXTEND_VECTOR_INREG: return combineExtInVec(N, DAG, DCI,<br>
+ Subtarget);<br>
case ISD::SETCC: return combineSetCC(N, DAG, Subtarget);<br>
case X86ISD::SETCC: return combineX86SetCC(N, DAG, Subtarget);<br>
case X86ISD::BRCOND: return combineBrCond(N, DAG, Subtarget);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=364977&r1=364976&r2=364977&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=364977&r1=364976&r2=364977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Jul 2 16:20:03 2019<br>
@@ -9632,21 +9632,15 @@ multiclass AVX512_pmovx_patterns<string<br>
(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;<br>
def : Pat<(v8i16 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;<br>
- def : Pat<(v8i16 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;<br>
}<br>
let Predicates = [HasVLX] in {<br>
def : Pat<(v4i32 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;<br>
def : Pat<(v4i32 (InVecOp (v16i8 (vzload_v4i32 addr:$src)))),<br>
(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;<br>
- def : Pat<(v4i32 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;<br>
<br>
def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;<br>
- def : Pat<(v2i64 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;<br>
<br>
def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;<br>
@@ -9654,15 +9648,11 @@ multiclass AVX512_pmovx_patterns<string<br>
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;<br>
def : Pat<(v4i32 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;<br>
- def : Pat<(v4i32 (InVecOp (loadv8i16 addr:$src))),<br>
- (!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;<br>
<br>
def : Pat<(v2i64 (InVecOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;<br>
def : Pat<(v2i64 (InVecOp (v8i16 (vzload_v4i32 addr:$src)))),<br>
(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;<br>
- def : Pat<(v2i64 (InVecOp (loadv8i16 addr:$src))),<br>
- (!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;<br>
<br>
def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;<br>
@@ -9670,37 +9660,27 @@ multiclass AVX512_pmovx_patterns<string<br>
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;<br>
def : Pat<(v2i64 (InVecOp (v4i32 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;<br>
- def : Pat<(v2i64 (InVecOp (loadv4i32 addr:$src))),<br>
- (!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;<br>
}<br>
let Predicates = [HasVLX] in {<br>
def : Pat<(v8i32 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;<br>
def : Pat<(v8i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;<br>
- def : Pat<(v8i32 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;<br>
<br>
def : Pat<(v4i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;<br>
def : Pat<(v4i64 (InVecOp (v16i8 (vzload_v4i32 addr:$src)))),<br>
(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;<br>
- def : Pat<(v4i64 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;<br>
<br>
def : Pat<(v4i64 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;<br>
def : Pat<(v4i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;<br>
- def : Pat<(v4i64 (InVecOp (loadv8i16 addr:$src))),<br>
- (!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;<br>
}<br>
// 512-bit patterns<br>
let Predicates = [HasAVX512] in {<br>
def : Pat<(v8i64 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#BQZrm) addr:$src)>;<br>
- def : Pat<(v8i64 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BQZrm) addr:$src)>;<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=364977&r1=364976&r2=364977&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=364977&r1=364976&r2=364977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 2 16:20:03 2019<br>
@@ -4947,8 +4947,6 @@ multiclass SS41I_pmovx_avx2_patterns<str<br>
(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;<br>
def : Pat<(v8i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;<br>
- def : Pat<(v8i32 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;<br>
<br>
def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),<br>
(!cast<I>(OpcPrefix#DQYrm) addr:$src)>;<br>
@@ -4957,15 +4955,11 @@ multiclass SS41I_pmovx_avx2_patterns<str<br>
(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;<br>
def : Pat<(v4i64 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;<br>
- def : Pat<(v4i64 (InVecOp (loadv16i8 addr:$src))),<br>
- (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;<br>
<br>
def : Pat<(v4i64 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),<br>
(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;<br>
def : Pat<(v4i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),<br>
(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;<br>
- def : Pat<(v4i64 (InVecOp (loadv8i16 addr:$src))),<br>
- (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;<br>
}<br>
}<br>
<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><u></u><u></u></p>
</blockquote>
</div>
</div>
</div>
</blockquote>
</div>
</blockquote>
</div>
</div>
</div>
</blockquote>
</div>
</div>
</div>
</blockquote></div>