<div dir="ltr">Actually, the test started failing in ubsan mode right after this commit. <div>Please fix ASAP. </div><div>Reproduce: build with -DLLVM_USE_SANITIZER=Undefined, then "ninja check-llvm"</div><div><br></div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jun 27, 2019 at 1:40 PM Kostya Serebryany <<a href="mailto:kcc@google.com">kcc@google.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Hi Simon, <div><br></div><div>This new test is currently failing on the ubsan build. </div><div>Could you please take a look? </div><div>I don't yet know is the breaking change. </div><div><br></div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/33133/steps/check-llvm%20ubsan/logs/stdio" target="_blank">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/33133/steps/check-llvm%20ubsan/logs/stdio</a><br></div><div><br></div><div><pre style="font-family:"Courier New",courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-m_4939499004758951942gmail-stdout">FAIL: LLVM :: MC/Disassembler/ARM/mve-load-store.txt (22713 of 32124)
******************** TEST 'LLVM :: MC/Disassembler/ARM/mve-load-store.txt' FAILED ********************
Script:
--
: 'RUN: at line 1'; /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding /b/sanitizer-x86_64-linux-fast/build/llvm/test/MC/Disassembler/ARM/mve-load-store.txt 2> /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/test/MC/Disassembler/ARM/Output/mve-load-store.txt.tmp | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/MC/Disassembler/ARM/mve-load-store.txt
: 'RUN: at line 2'; /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck --check-prefix=ERROR < /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/test/MC/Disassembler/ARM/Output/mve-load-store.txt.tmp /b/sanitizer-x86_64-linux-fast/build/llvm/test/MC/Disassembler/ARM/mve-load-store.txt
: 'RUN: at line 3'; not /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding /b/sanitizer-x86_64-linux-fast/build/llvm/test/MC/Disassembler/ARM/mve-load-store.txt &> /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/test/MC/Disassembler/ARM/Output/mve-load-store.txt.tmp
: 'RUN: at line 4'; /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck --check-prefix=CHECK-NOMVE < /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/test/MC/Disassembler/ARM/Output/mve-load-store.txt.tmp /b/sanitizer-x86_64-linux-fast/build/llvm/test/MC/Disassembler/ARM/mve-load-store.txt
--
Exit Code: 1
Command Output (stderr):
--
/b/sanitizer-x86_64-linux-fast/build/llvm/test/MC/Disassembler/ARM/mve-load-store.txt:269:10: error: CHECK: expected string not found in input
# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]
^
<stdin>:68:2: note: scanning from here
vldr
^
--
</span></pre><br class="gmail-m_4939499004758951942gmail-Apple-interchange-newline"></div><div><br></div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Jun 25, 2019 at 4:24 AM Simon Tatham via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: statham<br>
Date: Tue Jun 25 04:24:18 2019<br>
New Revision: 364291<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=364291&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=364291&view=rev</a><br>
Log:<br>
[ARM] Add MVE vector load/store instructions.<br>
<br>
This adds the rest of the vector memory access instructions. It<br>
includes contiguous loads/stores, with an ordinary addressing mode<br>
such as [r0,#offset] (plus writeback variants); gather loads and<br>
scatter stores with a scalar base address register and a vector of<br>
offsets from it (written [r0,q1] or similar); and gather/scatters with<br>
a vector of base addresses (written [q0,#offset], again with<br>
writeback). Additionally, some of the loads can widen each loaded<br>
value into a larger vector lane, and the corresponding stores narrow<br>
them again.<br>
<br>
To implement these, we also have to add the addressing modes they<br>
need. Also, in AsmParser, the `isMem` query function now has<br>
subqueries `isGPRMem` and `isMVEMem`, according to which kind of base<br>
register is used by a given memory access operand.<br>
<br>
I've also had to add an extra check in `checkTargetMatchPredicate` in<br>
the AsmParser, without which our last-minute check of `rGPR` register<br>
operands against SP and PC was failing an assertion because Tablegen<br>
had inserted an immediate 0 in place of one of a pair of tied register<br>
operands. (This matches the way the corresponding check for `MCK_rGPR`<br>
in `validateTargetOperandClass` is guarded.) Apparently the MVE load<br>
instructions were the first to have ever triggered this assertion, but<br>
I think only because they were the first to have a combination of the<br>
usual Arm pre/post writeback system and the `rGPR` class in particular.<br>
<br>
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover<br>
<br>
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D62680" rel="noreferrer" target="_blank">https://reviews.llvm.org/D62680</a><br>
<br>
Added:<br>
llvm/trunk/test/MC/ARM/mve-load-store.s (with props)<br>
llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt (with props)<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td<br>
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td<br>
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun 25 04:24:18 2019<br>
@@ -2477,11 +2477,14 @@ bool llvm::rewriteARMFrameIndex(MachineI<br>
NumBits = 8;<br>
Scale = 2;<br>
break;<br>
+ case ARMII::AddrModeT2_i7:<br>
+ case ARMII::AddrModeT2_i7s2:<br>
case ARMII::AddrModeT2_i7s4:<br>
ImmIdx = FrameRegIdx+1;<br>
InstrOffs = MI.getOperand(ImmIdx).getImm();<br>
NumBits = 7;<br>
- Scale = 4;<br>
+ Scale = (AddrMode == ARMII::AddrModeT2_i7s2 ? 2 :<br>
+ AddrMode == ARMII::AddrModeT2_i7s4 ? 4 : 1);<br>
break;<br>
default:<br>
llvm_unreachable("Unsupported addressing mode!");<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jun 25 04:24:18 2019<br>
@@ -110,6 +110,8 @@ def AddrMode_i12 : AddrMode<16>;<br>
def AddrMode5FP16 : AddrMode<17>;<br>
def AddrModeT2_ldrex : AddrMode<18>;<br>
def AddrModeT2_i7s4 : AddrMode<19>;<br>
+def AddrModeT2_i7s2 : AddrMode<20>;<br>
+def AddrModeT2_i7 : AddrMode<21>;<br>
<br>
// Load / store index mode.<br>
class IndexMode<bits<2> val> {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jun 25 04:24:18 2019<br>
@@ -1234,6 +1234,15 @@ def addr_offset_none : MemOperand,<br>
let MIOperandInfo = (ops GPR:$base);<br>
}<br>
<br>
+// t_addr_offset_none := reg [r0-r7]<br>
+def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; }<br>
+def t_addr_offset_none : MemOperand {<br>
+ let PrintMethod = "printAddrMode7Operand";<br>
+ let DecoderMethod = "DecodetGPRRegisterClass";<br>
+ let ParserMatchClass = MemNoOffsetTAsmOperand;<br>
+ let MIOperandInfo = (ops tGPR:$base);<br>
+}<br>
+<br>
def nohash_imm : Operand<i32> {<br>
let PrintMethod = "printNoHashImmediate";<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Tue Jun 25 04:24:18 2019<br>
@@ -153,6 +153,127 @@ def VecList4Q : RegisterOperand<QQQQPR,<br>
let PrintMethod = "printMVEVectorList<4>";<br>
}<br>
<br>
+// taddrmode_imm7 := reg[r0-r7] +/- (imm7 << shift)<br>
+class TMemImm7ShiftOffsetAsmOperand<int shift> : AsmOperandClass {<br>
+ let Name = "TMemImm7Shift"#shift#"Offset";<br>
+ let PredicateMethod = "isMemImm7ShiftedOffset<"#shift#",ARM::tGPRRegClassID>";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
+<br>
+class taddrmode_imm7<int shift> : MemOperand {<br>
+ let ParserMatchClass = TMemImm7ShiftOffsetAsmOperand<shift>;<br>
+ // They are printed the same way as the T2 imm8 version<br>
+ let PrintMethod = "printT2AddrModeImm8Operand<false>";<br>
+ // This can also be the same as the T2 version.<br>
+ let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";<br>
+ let DecoderMethod = "DecodeTAddrModeImm7<"#shift#">";<br>
+ let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);<br>
+}<br>
+<br>
+// t2addrmode_imm7 := reg +/- (imm7)<br>
+class MemImm7ShiftOffsetAsmOperand<int shift> : AsmOperandClass {<br>
+ let Name = "MemImm7Shift"#shift#"Offset";<br>
+ let PredicateMethod = "isMemImm7ShiftedOffset<" # shift #<br>
+ ",ARM::GPRnopcRegClassID>";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
+<br>
+def MemImm7Shift0OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<0>;<br>
+def MemImm7Shift1OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<1>;<br>
+def MemImm7Shift2OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<2>;<br>
+class T2AddrMode_Imm7<int shift> : MemOperand,<br>
+ ComplexPattern<i32, 2, "SelectT2AddrModeImm7<"#shift#">", []> {<br>
+ let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";<br>
+ let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 0>";<br>
+ let ParserMatchClass =<br>
+ !cast<AsmOperandClass>("MemImm7Shift"#shift#"OffsetAsmOperand");<br>
+ let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);<br>
+}<br>
+<br>
+class t2addrmode_imm7<int shift> : T2AddrMode_Imm7<shift> {<br>
+ // They are printed the same way as the imm8 version<br>
+ let PrintMethod = "printT2AddrModeImm8Operand<false>";<br>
+}<br>
+<br>
+class MemImm7ShiftOffsetWBAsmOperand<int shift> : AsmOperandClass {<br>
+ let Name = "MemImm7Shift"#shift#"OffsetWB";<br>
+ let PredicateMethod = "isMemImm7ShiftedOffset<" # shift #<br>
+ ",ARM::rGPRRegClassID>";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
+<br>
+def MemImm7Shift0OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<0>;<br>
+def MemImm7Shift1OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<1>;<br>
+def MemImm7Shift2OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<2>;<br>
+<br>
+class t2addrmode_imm7_pre<int shift> : T2AddrMode_Imm7<shift> {<br>
+ // They are printed the same way as the imm8 version<br>
+ let PrintMethod = "printT2AddrModeImm8Operand<true>";<br>
+ let ParserMatchClass =<br>
+ !cast<AsmOperandClass>("MemImm7Shift"#shift#"OffsetWBAsmOperand");<br>
+ let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 1>";<br>
+ let MIOperandInfo = (ops rGPR:$base, i32imm:$offsim);<br>
+}<br>
+<br>
+class t2am_imm7shiftOffsetAsmOperand<int shift><br>
+ : AsmOperandClass { let Name = "Imm7Shift"#shift; }<br>
+def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;<br>
+def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;<br>
+def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;<br>
+<br>
+class t2am_imm7_offset<int shift> : MemOperand {<br>
+ // They are printed the same way as the imm8 version<br>
+ let PrintMethod = "printT2AddrModeImm8OffsetOperand";<br>
+ let ParserMatchClass =<br>
+ !cast<AsmOperandClass>("t2am_imm7shift"#shift#"OffsetAsmOperand");<br>
+ let EncoderMethod = "getT2ScaledImmOpValue<7,"#shift#">";<br>
+ let DecoderMethod = "DecodeT2Imm7<"#shift#">";<br>
+}<br>
+<br>
+// Operands for gather/scatter loads of the form [Rbase, Qoffsets]<br>
+class MemRegRQOffsetAsmOperand<int shift> : AsmOperandClass {<br>
+ let Name = "MemRegRQS"#shift#"Offset";<br>
+ let PredicateMethod = "isMemRegRQOffset<"#shift#">";<br>
+ let RenderMethod = "addMemRegRQOffsetOperands";<br>
+}<br>
+<br>
+def MemRegRQS0OffsetAsmOperand : MemRegRQOffsetAsmOperand<0>;<br>
+def MemRegRQS1OffsetAsmOperand : MemRegRQOffsetAsmOperand<1>;<br>
+def MemRegRQS2OffsetAsmOperand : MemRegRQOffsetAsmOperand<2>;<br>
+def MemRegRQS3OffsetAsmOperand : MemRegRQOffsetAsmOperand<3>;<br>
+<br>
+// mve_addr_rq_shift := reg + vreg{ << UXTW #shift}<br>
+class mve_addr_rq_shift<int shift> : MemOperand {<br>
+ let EncoderMethod = "getMveAddrModeRQOpValue";<br>
+ let PrintMethod = "printMveAddrModeRQOperand<"#shift#">";<br>
+ let ParserMatchClass =<br>
+ !cast<AsmOperandClass>("MemRegRQS"#shift#"OffsetAsmOperand");<br>
+ let DecoderMethod = "DecodeMveAddrModeRQ";<br>
+ let MIOperandInfo = (ops GPRnopc:$base, MQPR:$offsreg);<br>
+}<br>
+<br>
+class MemRegQOffsetAsmOperand<int shift> : AsmOperandClass {<br>
+ let Name = "MemRegQS"#shift#"Offset";<br>
+ let PredicateMethod = "isMemRegQOffset<"#shift#">";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
+<br>
+def MemRegQS2OffsetAsmOperand : MemRegQOffsetAsmOperand<2>;<br>
+def MemRegQS3OffsetAsmOperand : MemRegQOffsetAsmOperand<3>;<br>
+<br>
+// mve_addr_q_shift := vreg {+ #imm7s2/4}<br>
+class mve_addr_q_shift<int shift> : MemOperand {<br>
+ let EncoderMethod = "getMveAddrModeQOpValue<"#shift#">";<br>
+ // Can be printed same way as other reg + imm operands<br>
+ let PrintMethod = "printT2AddrModeImm8Operand<false>";<br>
+ let ParserMatchClass =<br>
+ !cast<AsmOperandClass>("MemRegQS"#shift#"OffsetAsmOperand");<br>
+ let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">";<br>
+ let MIOperandInfo = (ops MQPR:$base, i32imm:$imm);<br>
+}<br>
+<br>
+// --------- Start of base classes for the instructions themselves<br>
+<br>
class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,<br>
string ops, string cstr, list<dag> pattern><br>
: Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,<br>
@@ -3245,6 +3366,359 @@ foreach wb = [MVE_vldst24_writeback<<br>
<br>
// end of MVE interleaving load/store<br>
<br>
+// start of MVE predicable load/store<br>
+<br>
+// A parameter class for the direction of transfer.<br>
+class MVE_ldst_direction<bit b, dag Oo, dag Io, string c=""> {<br>
+ bit load = b;<br>
+ dag Oops = Oo;<br>
+ dag Iops = Io;<br>
+ string cstr = c;<br>
+}<br>
+def MVE_ld: MVE_ldst_direction<1, (outs MQPR:$Qd), (ins), ",@earlyclobber $Qd">;<br>
+def MVE_st: MVE_ldst_direction<0, (outs), (ins MQPR:$Qd)>;<br>
+<br>
+// A parameter class for the size of memory access in a load.<br>
+class MVE_memsz<bits<2> e, int s, AddrMode m, string mn, list<string> types> {<br>
+ bits<2> encoding = e; // opcode bit(s) for encoding<br>
+ int shift = s; // shift applied to immediate load offset<br>
+ AddrMode AM = m;<br>
+<br>
+ // For instruction aliases: define the complete list of type<br>
+ // suffixes at this size, and the canonical ones for loads and<br>
+ // stores.<br>
+ string MnemonicLetter = mn;<br>
+ int TypeBits = !shl(8, s);<br>
+ string CanonLoadSuffix = ".u" # TypeBits;<br>
+ string CanonStoreSuffix = "." # TypeBits;<br>
+ list<string> suffixes = !foreach(letter, types, "." # letter # TypeBits);<br>
+}<br>
+<br>
+// Instances of MVE_memsz.<br>
+//<br>
+// (memD doesn't need an AddrMode, because those are only for<br>
+// contiguous loads, and memD is only used by gather/scatters.)<br>
+def MVE_memB: MVE_memsz<0b00, 0, AddrModeT2_i7, "b", ["", "u", "s"]>;<br>
+def MVE_memH: MVE_memsz<0b01, 1, AddrModeT2_i7s2, "h", ["", "u", "s", "f"]>;<br>
+def MVE_memW: MVE_memsz<0b10, 2, AddrModeT2_i7s4, "w", ["", "u", "s", "f"]>;<br>
+def MVE_memD: MVE_memsz<0b11, 3, ?, "d", ["", "u", "s", "f"]>;<br>
+<br>
+// This is the base class for all the MVE loads and stores other than<br>
+// the interleaving ones. All the non-interleaving loads/stores share<br>
+// the characteristic that they operate on just one vector register,<br>
+// so they are VPT-predicable.<br>
+//<br>
+// The predication operand is vpred_n, for both loads and stores. For<br>
+// store instructions, the reason is obvious: if there is no output<br>
+// register, there can't be a need for an input parameter giving the<br>
+// output register's previous value. Load instructions also don't need<br>
+// that input parameter, because unlike MVE data processing<br>
+// instructions, predicated loads are defined to set the inactive<br>
+// lanes of the output register to zero, instead of preserving their<br>
+// input values.<br>
+class MVE_VLDRSTR_base<MVE_ldst_direction dir, bit U, bit P, bit W, bit opc,<br>
+ dag oops, dag iops, string asm, string suffix,<br>
+ string ops, string cstr, list<dag> pattern=[]><br>
+ : MVE_p<oops, iops, NoItinerary, asm, suffix, ops, vpred_n, cstr, pattern> {<br>
+ bits<3> Qd;<br>
+<br>
+ let Inst{28} = U;<br>
+ let Inst{25} = 0b0;<br>
+ let Inst{24} = P;<br>
+ let Inst{22} = 0b0;<br>
+ let Inst{21} = W;<br>
+ let Inst{20} = dir.load;<br>
+ let Inst{15-13} = Qd{2-0};<br>
+ let Inst{12} = opc;<br>
+ let Inst{11-9} = 0b111;<br>
+<br>
+ let mayLoad = dir.load;<br>
+ let mayStore = !eq(dir.load,0);<br>
+}<br>
+<br>
+// Contiguous load and store instructions. These come in two main<br>
+// categories: same-size loads/stores in which 128 bits of vector<br>
+// register is transferred to or from 128 bits of memory in the most<br>
+// obvious way, and widening loads / narrowing stores, in which the<br>
+// size of memory accessed is less than the size of a vector register,<br>
+// so the load instructions sign- or zero-extend each memory value<br>
+// into a wider vector lane, and the store instructions truncate<br>
+// correspondingly.<br>
+//<br>
+// The instruction mnemonics for these two classes look reasonably<br>
+// similar, but the actual encodings are different enough to need two<br>
+// separate base classes.<br>
+<br>
+// Contiguous, same size<br>
+class MVE_VLDRSTR_cs<MVE_ldst_direction dir, MVE_memsz memsz, bit P, bit W,<br>
+ dag oops, dag iops, string asm, string suffix,<br>
+ IndexMode im, string ops, string cstr><br>
+ : MVE_VLDRSTR_base<dir, 0, P, W, 1, oops, iops, asm, suffix, ops, cstr> {<br>
+ bits<12> addr;<br>
+ let Inst{23} = addr{7};<br>
+ let Inst{19-16} = addr{11-8};<br>
+ let Inst{8-7} = memsz.encoding;<br>
+ let Inst{6-0} = addr{6-0};<br>
+}<br>
+<br>
+// Contiguous, widening/narrowing<br>
+class MVE_VLDRSTR_cw<MVE_ldst_direction dir, MVE_memsz memsz, bit U,<br>
+ bit P, bit W, bits<2> size, dag oops, dag iops,<br>
+ string asm, string suffix, IndexMode im,<br>
+ string ops, string cstr><br>
+ : MVE_VLDRSTR_base<dir, U, P, W, 0, oops, iops, asm, suffix, ops, cstr> {<br>
+ bits<11> addr;<br>
+ let Inst{23} = addr{7};<br>
+ let Inst{19} = memsz.encoding{0}; // enough to tell 16- from 32-bit<br>
+ let Inst{18-16} = addr{10-8};<br>
+ let Inst{8-7} = size;<br>
+ let Inst{6-0} = addr{6-0};<br>
+<br>
+ let IM = im;<br>
+}<br>
+<br>
+// Multiclass wrapper on each of the _cw and _cs base classes, to<br>
+// generate three writeback modes (none, preindex, postindex).<br>
+<br>
+multiclass MVE_VLDRSTR_cw_m<MVE_ldst_direction dir, MVE_memsz memsz,<br>
+ string asm, string suffix, bit U, bits<2> size> {<br>
+ let AM = memsz.AM in {<br>
+ def "" : MVE_VLDRSTR_cw<<br>
+ dir, memsz, U, 1, 0, size,<br>
+ dir.Oops, !con(dir.Iops, (ins taddrmode_imm7<memsz.shift>:$addr)),<br>
+ asm, suffix, IndexModeNone, "$Qd, $addr", "">;<br>
+<br>
+ def _pre : MVE_VLDRSTR_cw<<br>
+ dir, memsz, U, 1, 1, size,<br>
+ !con((outs tGPR:$wb), dir.Oops),<br>
+ !con(dir.Iops, (ins taddrmode_imm7<memsz.shift>:$addr)),<br>
+ asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {<br>
+ let DecoderMethod = "DecodeMVE_MEM_1_pre<"#memsz.shift#">";<br>
+ }<br>
+<br>
+ def _post : MVE_VLDRSTR_cw<<br>
+ dir, memsz, U, 0, 1, size,<br>
+ !con((outs tGPR:$wb), dir.Oops),<br>
+ !con(dir.Iops, (ins t_addr_offset_none:$Rn,<br>
+ t2am_imm7_offset<memsz.shift>:$addr)),<br>
+ asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {<br>
+ bits<4> Rn;<br>
+ let Inst{18-16} = Rn{2-0};<br>
+ }<br>
+ }<br>
+}<br>
+<br>
+multiclass MVE_VLDRSTR_cs_m<MVE_ldst_direction dir, MVE_memsz memsz,<br>
+ string asm, string suffix> {<br>
+ let AM = memsz.AM in {<br>
+ def "" : MVE_VLDRSTR_cs<<br>
+ dir, memsz, 1, 0,<br>
+ dir.Oops, !con(dir.Iops, (ins t2addrmode_imm7<memsz.shift>:$addr)),<br>
+ asm, suffix, IndexModeNone, "$Qd, $addr", "">;<br>
+<br>
+ def _pre : MVE_VLDRSTR_cs<<br>
+ dir, memsz, 1, 1,<br>
+ !con((outs rGPR:$wb), dir.Oops),<br>
+ !con(dir.Iops, (ins t2addrmode_imm7_pre<memsz.shift>:$addr)),<br>
+ asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {<br>
+ let DecoderMethod = "DecodeMVE_MEM_2_pre<"#memsz.shift#">";<br>
+ }<br>
+<br>
+ def _post : MVE_VLDRSTR_cs<<br>
+ dir, memsz, 0, 1,<br>
+ !con((outs rGPR:$wb), dir.Oops),<br>
+ // We need an !if here to select the base register class,<br>
+ // because it's legal to write back to SP in a load of this<br>
+ // type, but not in a store.<br>
+ !con(dir.Iops, (ins !if(dir.load, t2_addr_offset_none,<br>
+ t2_nosp_addr_offset_none):$Rn,<br>
+ t2am_imm7_offset<memsz.shift>:$addr)),<br>
+ asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {<br>
+ bits<4> Rn;<br>
+ let Inst{19-16} = Rn{3-0};<br>
+ }<br>
+ }<br>
+}<br>
+<br>
+// Now actually declare all the contiguous load/stores, via those<br>
+// multiclasses. The instruction ids coming out of this are the bare<br>
+// names shown in the defm, with _pre or _post appended for writeback,<br>
+// e.g. MVE_VLDRBS16, MVE_VSTRB16_pre, MVE_VSTRHU16_post.<br>
+<br>
+defm MVE_VLDRBS16: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "s16", 0, 0b01>;<br>
+defm MVE_VLDRBS32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "s32", 0, 0b10>;<br>
+defm MVE_VLDRBU16: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "u16", 1, 0b01>;<br>
+defm MVE_VLDRBU32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "u32", 1, 0b10>;<br>
+defm MVE_VLDRHS32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memH, "vldrh", "s32", 0, 0b10>;<br>
+defm MVE_VLDRHU32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memH, "vldrh", "u32", 1, 0b10>;<br>
+<br>
+defm MVE_VLDRBU8: MVE_VLDRSTR_cs_m<MVE_ld, MVE_memB, "vldrb", "u8">;<br>
+defm MVE_VLDRHU16: MVE_VLDRSTR_cs_m<MVE_ld, MVE_memH, "vldrh", "u16">;<br>
+defm MVE_VLDRWU32: MVE_VLDRSTR_cs_m<MVE_ld, MVE_memW, "vldrw", "u32">;<br>
+<br>
+defm MVE_VSTRB16: MVE_VLDRSTR_cw_m<MVE_st, MVE_memB, "vstrb", "16", 0, 0b01>;<br>
+defm MVE_VSTRB32: MVE_VLDRSTR_cw_m<MVE_st, MVE_memB, "vstrb", "32", 0, 0b10>;<br>
+defm MVE_VSTRH32: MVE_VLDRSTR_cw_m<MVE_st, MVE_memH, "vstrh", "32", 0, 0b10>;<br>
+<br>
+defm MVE_VSTRBU8 : MVE_VLDRSTR_cs_m<MVE_st, MVE_memB, "vstrb", "8">;<br>
+defm MVE_VSTRHU16: MVE_VLDRSTR_cs_m<MVE_st, MVE_memH, "vstrh", "16">;<br>
+defm MVE_VSTRWU32: MVE_VLDRSTR_cs_m<MVE_st, MVE_memW, "vstrw", "32">;<br>
+<br>
+// Gather loads / scatter stores whose address operand is of the form<br>
+// [Rn,Qm], i.e. a single GPR as the common base address, plus a<br>
+// vector of offset from it. ('Load/store this sequence of elements of<br>
+// the same array.')<br>
+//<br>
+// Like the contiguous family, these loads and stores can widen the<br>
+// loaded values / truncate the stored ones, or they can just<br>
+// load/store the same size of memory and vector lane. But unlike the<br>
+// contiguous family, there's no particular difference in encoding<br>
+// between those two cases.<br>
+//<br>
+// This family also comes with the option to scale the offset values<br>
+// in Qm by the size of the loaded memory (i.e. to treat them as array<br>
+// indices), or not to scale them (to treat them as plain byte offsets<br>
+// in memory, so that perhaps the loaded values are unaligned). The<br>
+// scaled instructions' address operand in assembly looks like<br>
+// [Rn,Qm,UXTW #2] or similar.<br>
+<br>
+// Base class.<br>
+class MVE_VLDRSTR_rq<MVE_ldst_direction dir, MVE_memsz memsz, bit U,<br>
+ bits<2> size, bit os, string asm, string suffix, int shift><br>
+ : MVE_VLDRSTR_base<dir, U, 0b0, 0b0, 0, dir.Oops,<br>
+ !con(dir.Iops, (ins mve_addr_rq_shift<shift>:$addr)),<br>
+ asm, suffix, "$Qd, $addr", dir.cstr> {<br>
+ bits<7> addr;<br>
+ let Inst{23} = 0b1;<br>
+ let Inst{19-16} = addr{6-3};<br>
+ let Inst{8-7} = size;<br>
+ let Inst{6} = memsz.encoding{1};<br>
+ let Inst{5} = 0;<br>
+ let Inst{4} = memsz.encoding{0};<br>
+ let Inst{3-1} = addr{2-0};<br>
+ let Inst{0} = os;<br>
+}<br>
+<br>
+// Multiclass that defines the scaled and unscaled versions of an<br>
+// instruction, when the memory size is wider than a byte. The scaled<br>
+// version gets the default name like MVE_VLDRBU16_rq; the unscaled /<br>
+// potentially unaligned version gets a "_u" suffix, e.g.<br>
+// MVE_VLDRBU16_rq_u.<br>
+multiclass MVE_VLDRSTR_rq_w<MVE_ldst_direction dir, MVE_memsz memsz,<br>
+ string asm, string suffix, bit U, bits<2> size> {<br>
+ def _u : MVE_VLDRSTR_rq<dir, memsz, U, size, 0, asm, suffix, 0>;<br>
+ def "" : MVE_VLDRSTR_rq<dir, memsz, U, size, 1, asm, suffix, memsz.shift>;<br>
+}<br>
+<br>
+// Subclass of MVE_VLDRSTR_rq with the same API as that multiclass,<br>
+// for use when the memory size is one byte, so there's no 'scaled'<br>
+// version of the instruction at all. (This is encoded as if it were<br>
+// unscaled, but named in the default way with no _u suffix.)<br>
+class MVE_VLDRSTR_rq_b<MVE_ldst_direction dir, MVE_memsz memsz,<br>
+ string asm, string suffix, bit U, bits<2> size><br>
+ : MVE_VLDRSTR_rq<dir, memsz, U, size, 0, asm, suffix, 0>;<br>
+<br>
+// Actually define all the loads and stores in this family.<br>
+<br>
+def MVE_VLDRBU8_rq : MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb","u8", 1,0b00>;<br>
+def MVE_VLDRBU16_rq: MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb","u16", 1,0b01>;<br>
+def MVE_VLDRBS16_rq: MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb","s16", 0,0b01>;<br>
+def MVE_VLDRBU32_rq: MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb","u32", 1,0b10>;<br>
+def MVE_VLDRBS32_rq: MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb","s32", 0,0b10>;<br>
+<br>
+defm MVE_VLDRHU16_rq: MVE_VLDRSTR_rq_w<MVE_ld, MVE_memH, "vldrh","u16", 1,0b01>;<br>
+defm MVE_VLDRHU32_rq: MVE_VLDRSTR_rq_w<MVE_ld, MVE_memH, "vldrh","u32", 1,0b10>;<br>
+defm MVE_VLDRHS32_rq: MVE_VLDRSTR_rq_w<MVE_ld, MVE_memH, "vldrh","s32", 0,0b10>;<br>
+defm MVE_VLDRWU32_rq: MVE_VLDRSTR_rq_w<MVE_ld, MVE_memW, "vldrw","u32", 1,0b10>;<br>
+defm MVE_VLDRDU64_rq: MVE_VLDRSTR_rq_w<MVE_ld, MVE_memD, "vldrd","u64", 1,0b11>;<br>
+<br>
+def MVE_VSTRB8_rq : MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb","8", 0,0b00>;<br>
+def MVE_VSTRB16_rq : MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb","16", 0,0b01>;<br>
+def MVE_VSTRB32_rq : MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb","32", 0,0b10>;<br>
+<br>
+defm MVE_VSTRH16_rq : MVE_VLDRSTR_rq_w<MVE_st, MVE_memH, "vstrh","16", 0,0b01>;<br>
+defm MVE_VSTRH32_rq : MVE_VLDRSTR_rq_w<MVE_st, MVE_memH, "vstrh","32", 0,0b10>;<br>
+defm MVE_VSTRW32_rq : MVE_VLDRSTR_rq_w<MVE_st, MVE_memW, "vstrw","32", 0,0b10>;<br>
+defm MVE_VSTRD64_rq : MVE_VLDRSTR_rq_w<MVE_st, MVE_memD, "vstrd","64", 0,0b11>;<br>
+<br>
+// Gather loads / scatter stores whose address operand is of the form<br>
+// [Qm,#imm], i.e. a vector containing a full base address for each<br>
+// loaded item, plus an immediate offset applied consistently to all<br>
+// of them. ('Load/store the same field from this vector of pointers<br>
+// to a structure type.')<br>
+//<br>
+// This family requires the vector lane size to be at least 32 bits<br>
+// (so there's room for an address in each lane at all). It has no<br>
+// widening/narrowing variants. But it does support preindex<br>
+// writeback, in which the address vector is updated to hold the<br>
+// addresses actually loaded from.<br>
+<br>
+// Base class.<br>
+class MVE_VLDRSTR_qi<MVE_ldst_direction dir, MVE_memsz memsz, bit W, dag wbops,<br>
+ string asm, string wbAsm, string suffix, string cstr = ""><br>
+ : MVE_VLDRSTR_base<dir, 1, 1, W, 1, !con(wbops, dir.Oops),<br>
+ !con(dir.Iops, (ins mve_addr_q_shift<memsz.shift>:$addr)),<br>
+ asm, suffix, "$Qd, $addr" # wbAsm, cstr # dir.cstr> {<br>
+ bits<11> addr;<br>
+ let Inst{23} = addr{7};<br>
+ let Inst{19-17} = addr{10-8};<br>
+ let Inst{16} = 0;<br>
+ let Inst{8} = memsz.encoding{0}; // enough to distinguish 32- from 64-bit<br>
+ let Inst{7} = 0;<br>
+ let Inst{6-0} = addr{6-0};<br>
+}<br>
+<br>
+// Multiclass that generates the non-writeback and writeback variants.<br>
+multiclass MVE_VLDRSTR_qi_m<MVE_ldst_direction dir, MVE_memsz memsz,<br>
+ string asm, string suffix> {<br>
+ def "" : MVE_VLDRSTR_qi<dir, memsz, 0, (outs), asm, "", suffix>;<br>
+ def _pre : MVE_VLDRSTR_qi<dir, memsz, 1, (outs MQPR:$wb), asm, "!", suffix,<br>
+ "$addr.base = $wb"> {<br>
+ let DecoderMethod="DecodeMVE_MEM_3_pre<"#memsz.shift#">";<br>
+ }<br>
+}<br>
+<br>
+// Actual instruction definitions.<br>
+defm MVE_VLDRWU32_qi: MVE_VLDRSTR_qi_m<MVE_ld, MVE_memW, "vldrw", "u32">;<br>
+defm MVE_VLDRDU64_qi: MVE_VLDRSTR_qi_m<MVE_ld, MVE_memD, "vldrd", "u64">;<br>
+defm MVE_VSTRW32_qi: MVE_VLDRSTR_qi_m<MVE_st, MVE_memW, "vstrw", "32">;<br>
+defm MVE_VSTRD64_qi: MVE_VLDRSTR_qi_m<MVE_st, MVE_memD, "vstrd", "64">;<br>
+<br>
+// Define aliases for all the instructions where memory size and<br>
+// vector lane size are the same. These are mnemonic aliases, so they<br>
+// apply consistently across all of the above families - contiguous<br>
+// loads, and both the rq and qi types of gather/scatter.<br>
+//<br>
+// Rationale: As long as you're loading (for example) 16-bit memory<br>
+// values into 16-bit vector lanes, you can think of them as signed or<br>
+// unsigned integers, fp16 or just raw 16-bit blobs and it makes no<br>
+// difference. So we permit all of vldrh.16, vldrh.u16, vldrh.s16,<br>
+// vldrh.f16 and treat them all as equivalent to the canonical<br>
+// spelling (which happens to be .u16 for loads, and just .16 for<br>
+// stores).<br>
+<br>
+foreach vpt_cond = ["", "t", "e"] in<br>
+foreach memsz = [MVE_memB, MVE_memH, MVE_memW, MVE_memD] in<br>
+foreach suffix = memsz.suffixes in {<br>
+<br>
+ // These foreaches are conceptually ifs, implemented by iterating a<br>
+ // dummy variable over a list with 0 or 1 elements depending on the<br>
+ // condition. The idea is to iterate over _nearly_ all the suffixes<br>
+ // in memsz.suffixes, but omit the one we want all the others to alias.<br>
+<br>
+ foreach _ = !if(!ne(suffix, memsz.CanonLoadSuffix), [1], []<int>) in<br>
+ def : MnemonicAlias<<br>
+ "vldr" # memsz.MnemonicLetter # vpt_cond # suffix,<br>
+ "vldr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonLoadSuffix>;<br>
+<br>
+ foreach _ = !if(!ne(suffix, memsz.CanonStoreSuffix), [1], []<int>) in<br>
+ def : MnemonicAlias<<br>
+ "vstr" # memsz.MnemonicLetter # vpt_cond # suffix,<br>
+ "vstr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonStoreSuffix>;<br>
+}<br>
+<br>
+// end of MVE predicable load/store<br>
+<br>
class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]><br>
: MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {<br>
bits<3> fc;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 25 04:24:18 2019<br>
@@ -212,31 +212,40 @@ def t2adrlabel : Operand<i32> {<br>
}<br>
<br>
// t2addrmode_posimm8 := reg + imm8<br>
-def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}<br>
+def MemPosImm8OffsetAsmOperand : AsmOperandClass {<br>
+ let Name="MemPosImm8Offset";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
def t2addrmode_posimm8 : MemOperand {<br>
let PrintMethod = "printT2AddrModeImm8Operand<false>";<br>
- let EncoderMethod = "getT2AddrModeImm8OpValue";<br>
+ let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";<br>
let DecoderMethod = "DecodeT2AddrModeImm8";<br>
let ParserMatchClass = MemPosImm8OffsetAsmOperand;<br>
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);<br>
}<br>
<br>
// t2addrmode_negimm8 := reg - imm8<br>
-def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}<br>
+def MemNegImm8OffsetAsmOperand : AsmOperandClass {<br>
+ let Name="MemNegImm8Offset";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
def t2addrmode_negimm8 : MemOperand,<br>
ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {<br>
let PrintMethod = "printT2AddrModeImm8Operand<false>";<br>
- let EncoderMethod = "getT2AddrModeImm8OpValue";<br>
+ let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";<br>
let DecoderMethod = "DecodeT2AddrModeImm8";<br>
let ParserMatchClass = MemNegImm8OffsetAsmOperand;<br>
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);<br>
}<br>
<br>
// t2addrmode_imm8 := reg +/- imm8<br>
-def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }<br>
+def MemImm8OffsetAsmOperand : AsmOperandClass {<br>
+ let Name = "MemImm8Offset";<br>
+ let RenderMethod = "addMemImmOffsetOperands";<br>
+}<br>
class T2AddrMode_Imm8 : MemOperand,<br>
ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {<br>
- let EncoderMethod = "getT2AddrModeImm8OpValue";<br>
+ let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";<br>
let DecoderMethod = "DecodeT2AddrModeImm8";<br>
let ParserMatchClass = MemImm8OffsetAsmOperand;<br>
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jun 25 04:24:18 2019<br>
@@ -1025,7 +1025,7 @@ public:<br>
if (!CE) return false;<br>
Val = CE->getValue();<br>
}<br>
- else if (isMem()) {<br>
+ else if (isGPRMem()) {<br>
if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;<br>
if(Memory.BaseRegNum != ARM::PC) return false;<br>
Val = Memory.OffsetImm->getValue();<br>
@@ -1059,7 +1059,14 @@ public:<br>
int64_t Value = CE->getValue();<br>
return ((Value & 3) == 0) && Value >= N && Value <= M;<br>
}<br>
-<br>
+ template<int64_t N, int64_t M><br>
+ bool isImmediateS2() const {<br>
+ if (!isImm()) return false;<br>
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>
+ if (!CE) return false;<br>
+ int64_t Value = CE->getValue();<br>
+ return ((Value & 1) == 0) && Value >= N && Value <= M;<br>
+ }<br>
bool isFBits16() const {<br>
return isImmediate<0, 17>();<br>
}<br>
@@ -1072,6 +1079,18 @@ public:<br>
bool isImm7s4() const {<br>
return isImmediateS4<-508, 508>();<br>
}<br>
+ bool isImm7Shift0() const {<br>
+ return isImmediate<-127, 127>();<br>
+ }<br>
+ bool isImm7Shift1() const {<br>
+ return isImmediateS2<-255, 255>();<br>
+ }<br>
+ bool isImm7Shift2() const {<br>
+ return isImmediateS4<-511, 511>();<br>
+ }<br>
+ bool isImm7() const {<br>
+ return isImmediate<-127, 127>();<br>
+ }<br>
bool isImm0_1020s4() const {<br>
return isImmediateS4<0, 1020>();<br>
}<br>
@@ -1253,6 +1272,22 @@ public:<br>
bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }<br>
bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }<br>
bool isMem() const override {<br>
+ return isGPRMem() || isMVEMem();<br>
+ }<br>
+ bool isMVEMem() const {<br>
+ if (Kind != k_Memory)<br>
+ return false;<br>
+ if (Memory.BaseRegNum &&<br>
+ !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&<br>
+ !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))<br>
+ return false;<br>
+ if (Memory.OffsetRegNum &&<br>
+ !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(<br>
+ Memory.OffsetRegNum))<br>
+ return false;<br>
+ return true;<br>
+ }<br>
+ bool isGPRMem() const {<br>
if (Kind != k_Memory)<br>
return false;<br>
if (Memory.BaseRegNum &&<br>
@@ -1332,14 +1367,14 @@ public:<br>
return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;<br>
}<br>
bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {<br>
- if (!isMem())<br>
+ if (!isGPRMem())<br>
return false;<br>
// No offset of any kind.<br>
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&<br>
(alignOK || Memory.Alignment == Alignment);<br>
}<br>
bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {<br>
- if (!isMem())<br>
+ if (!isGPRMem())<br>
return false;<br>
<br>
if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(<br>
@@ -1351,7 +1386,7 @@ public:<br>
(alignOK || Memory.Alignment == Alignment);<br>
}<br>
bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {<br>
- if (!isMem())<br>
+ if (!isGPRMem())<br>
return false;<br>
<br>
if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(<br>
@@ -1362,8 +1397,20 @@ public:<br>
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&<br>
(alignOK || Memory.Alignment == Alignment);<br>
}<br>
+ bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {<br>
+ if (!isGPRMem())<br>
+ return false;<br>
+<br>
+ if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(<br>
+ Memory.BaseRegNum))<br>
+ return false;<br>
+<br>
+ // No offset of any kind.<br>
+ return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&<br>
+ (alignOK || Memory.Alignment == Alignment);<br>
+ }<br>
bool isMemPCRelImm12() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Base register must be PC.<br>
if (Memory.BaseRegNum != ARM::PC)<br>
@@ -1450,7 +1497,7 @@ public:<br>
}<br>
<br>
bool isAddrMode2() const {<br>
- if (!isMem() || Memory.Alignment != 0) return false;<br>
+ if (!isGPRMem() || Memory.Alignment != 0) return false;<br>
// Check for register offset.<br>
if (Memory.OffsetRegNum) return true;<br>
// Immediate offset in range [-4095, 4095].<br>
@@ -1475,7 +1522,7 @@ public:<br>
// and we reject it.<br>
if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
return true;<br>
- if (!isMem() || Memory.Alignment != 0) return false;<br>
+ if (!isGPRMem() || Memory.Alignment != 0) return false;<br>
// No shifts are legal for AM3.<br>
if (Memory.ShiftType != ARM_AM::no_shift) return false;<br>
// Check for register offset.<br>
@@ -1509,7 +1556,7 @@ public:<br>
// and we reject it.<br>
if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
return true;<br>
- if (!isMem() || Memory.Alignment != 0) return false;<br>
+ if (!isGPRMem() || Memory.Alignment != 0) return false;<br>
// Check for register offset.<br>
if (Memory.OffsetRegNum) return false;<br>
// Immediate offset in range [-1020, 1020] and a multiple of 4.<br>
@@ -1525,7 +1572,7 @@ public:<br>
// and we reject it.<br>
if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
return true;<br>
- if (!isMem() || Memory.Alignment != 0) return false;<br>
+ if (!isGPRMem() || Memory.Alignment != 0) return false;<br>
// Check for register offset.<br>
if (Memory.OffsetRegNum) return false;<br>
// Immediate offset in range [-510, 510] and a multiple of 2.<br>
@@ -1536,14 +1583,14 @@ public:<br>
}<br>
<br>
bool isMemTBB() const {<br>
- if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
+ if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)<br>
return false;<br>
return true;<br>
}<br>
<br>
bool isMemTBH() const {<br>
- if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
+ if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||<br>
Memory.Alignment != 0 )<br>
return false;<br>
@@ -1551,13 +1598,13 @@ public:<br>
}<br>
<br>
bool isMemRegOffset() const {<br>
- if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)<br>
return false;<br>
return true;<br>
}<br>
<br>
bool isT2MemRegOffset() const {<br>
- if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
+ if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)<br>
return false;<br>
// Only lsl #{0, 1, 2, 3} allowed.<br>
@@ -1571,7 +1618,7 @@ public:<br>
bool isMemThumbRR() const {<br>
// Thumb reg+reg addressing is simple. Just two registers, a base and<br>
// an offset. No shifts, negations or any other complicating factors.<br>
- if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
+ if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||<br>
Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)<br>
return false;<br>
return isARMLowRegister(Memory.BaseRegNum) &&<br>
@@ -1579,7 +1626,7 @@ public:<br>
}<br>
<br>
bool isMemThumbRIs4() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 ||<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 ||<br>
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset, multiple of 4 in range [0, 124].<br>
@@ -1589,7 +1636,7 @@ public:<br>
}<br>
<br>
bool isMemThumbRIs2() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 ||<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 ||<br>
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset, multiple of 4 in range [0, 62].<br>
@@ -1599,7 +1646,7 @@ public:<br>
}<br>
<br>
bool isMemThumbRIs1() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 ||<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 ||<br>
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset in range [0, 31].<br>
@@ -1609,7 +1656,7 @@ public:<br>
}<br>
<br>
bool isMemThumbSPI() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 ||<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 ||<br>
Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset, multiple of 4 in range [0, 1020].<br>
@@ -1624,7 +1671,7 @@ public:<br>
// and we reject it.<br>
if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
return true;<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset a multiple of 4 in range [-1020, 1020].<br>
if (!Memory.OffsetImm) return true;<br>
@@ -1639,7 +1686,7 @@ public:<br>
// and we reject it.<br>
if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
return true;<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||<br>
!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(<br>
Memory.BaseRegNum))<br>
return false;<br>
@@ -1650,7 +1697,7 @@ public:<br>
return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;<br>
}<br>
bool isMemImm0_1020s4Offset() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset a multiple of 4 in range [0, 1020].<br>
if (!Memory.OffsetImm) return true;<br>
@@ -1659,7 +1706,7 @@ public:<br>
}<br>
<br>
bool isMemImm8Offset() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Base reg of PC isn't allowed for these encodings.<br>
if (Memory.BaseRegNum == ARM::PC) return false;<br>
@@ -1670,8 +1717,81 @@ public:<br>
(Val > -256 && Val < 256);<br>
}<br>
<br>
+ template<unsigned Bits, unsigned RegClassID><br>
+ bool isMemImm7ShiftedOffset() const {<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||<br>
+ !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))<br>
+ return false;<br>
+<br>
+ // Expect an immediate offset equal to an element of the range<br>
+ // [-127, 127], shifted left by Bits.<br>
+<br>
+ if (!Memory.OffsetImm) return true;<br>
+ int64_t Val = Memory.OffsetImm->getValue();<br>
+<br>
+ // INT32_MIN is a special-case value (indicating the encoding with<br>
+ // zero offset and the subtract bit set)<br>
+ if (Val == INT32_MIN)<br>
+ return true;<br>
+<br>
+ unsigned Divisor = 1U << Bits;<br>
+<br>
+ // Check that the low bits are zero<br>
+ if (Val % Divisor != 0)<br>
+ return false;<br>
+<br>
+ // Check that the remaining offset is within range.<br>
+ Val /= Divisor;<br>
+ return (Val >= -127 && Val <= 127);<br>
+ }<br>
+<br>
+ template <int shift> bool isMemRegRQOffset() const {<br>
+ if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)<br>
+ return false;<br>
+<br>
+ if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(<br>
+ Memory.BaseRegNum))<br>
+ return false;<br>
+ if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(<br>
+ Memory.OffsetRegNum))<br>
+ return false;<br>
+<br>
+ if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)<br>
+ return false;<br>
+<br>
+ if (shift > 0 &&<br>
+ (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))<br>
+ return false;<br>
+<br>
+ return true;<br>
+ }<br>
+<br>
+ template <int shift> bool isMemRegQOffset() const {<br>
+ if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ return false;<br>
+<br>
+ if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(<br>
+ Memory.BaseRegNum))<br>
+ return false;<br>
+<br>
+ if(!Memory.OffsetImm) return true;<br>
+ static_assert(shift < 56,<br>
+ "Such that we dont shift by a value higher than 62");<br>
+ int64_t Val = Memory.OffsetImm->getValue();<br>
+<br>
+ // The value must be a multiple of (1 << shift)<br>
+ if ((Val & ((1U << shift) - 1)) != 0)<br>
+ return false;<br>
+<br>
+ // And be in the right range, depending on the amount that it is shifted<br>
+ // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set<br>
+ // separately.<br>
+ int64_t Range = (1U << (7+shift)) - 1;<br>
+ return (Val == INT32_MIN) || (Val > -Range && Val < Range);<br>
+ }<br>
+<br>
bool isMemPosImm8Offset() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset in range [0, 255].<br>
if (!Memory.OffsetImm) return true;<br>
@@ -1680,7 +1800,7 @@ public:<br>
}<br>
<br>
bool isMemNegImm8Offset() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Base reg of PC isn't allowed for these encodings.<br>
if (Memory.BaseRegNum == ARM::PC) return false;<br>
@@ -1692,7 +1812,7 @@ public:<br>
}<br>
<br>
bool isMemUImm12Offset() const {<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset in range [0, 4095].<br>
if (!Memory.OffsetImm) return true;<br>
@@ -1708,7 +1828,7 @@ public:<br>
if (isImm() && !isa<MCConstantExpr>(getImm()))<br>
return true;<br>
<br>
- if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
+ if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)<br>
return false;<br>
// Immediate offset in range [-4095, 4095].<br>
if (!Memory.OffsetImm) return true;<br>
@@ -2423,6 +2543,34 @@ public:<br>
Inst.addOperand(MCOperand::createImm(CE->getValue()));<br>
}<br>
<br>
+ void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 1 && "Invalid number of operands!");<br>
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>
+ assert(CE != nullptr && "Invalid operand type!");<br>
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));<br>
+ }<br>
+<br>
+ void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 1 && "Invalid number of operands!");<br>
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>
+ assert(CE != nullptr && "Invalid operand type!");<br>
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));<br>
+ }<br>
+<br>
+ void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 1 && "Invalid number of operands!");<br>
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>
+ assert(CE != nullptr && "Invalid operand type!");<br>
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));<br>
+ }<br>
+<br>
+ void addImm7Operands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 1 && "Invalid number of operands!");<br>
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());<br>
+ assert(CE != nullptr && "Invalid operand type!");<br>
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));<br>
+ }<br>
+<br>
void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {<br>
assert(N == 1 && "Invalid number of operands!");<br>
// The immediate is scaled by four in the encoding and is stored<br>
@@ -2532,7 +2680,7 @@ public:<br>
return;<br>
}<br>
<br>
- assert(isMem() && "Unknown value type!");<br>
+ assert(isGPRMem() && "Unknown value type!");<br>
assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");<br>
Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));<br>
}<br>
@@ -2567,6 +2715,11 @@ public:<br>
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));<br>
}<br>
<br>
+ void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 1 && "Invalid number of operands!");<br>
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));<br>
+ }<br>
+<br>
void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {<br>
assert(N == 1 && "Invalid number of operands!");<br>
int32_t Imm = Memory.OffsetImm->getValue();<br>
@@ -2808,19 +2961,17 @@ public:<br>
Inst.addOperand(MCOperand::createImm(Val));<br>
}<br>
<br>
- void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {<br>
+ void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {<br>
assert(N == 2 && "Invalid number of operands!");<br>
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;<br>
Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));<br>
Inst.addOperand(MCOperand::createImm(Val));<br>
}<br>
<br>
- void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {<br>
- addMemImm8OffsetOperands(Inst, N);<br>
- }<br>
-<br>
- void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {<br>
- addMemImm8OffsetOperands(Inst, N);<br>
+ void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {<br>
+ assert(N == 2 && "Invalid number of operands!");<br>
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));<br>
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));<br>
}<br>
<br>
void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {<br>
@@ -5657,6 +5808,8 @@ bool ARMAsmParser::parseMemRegOffsetShif<br>
St = ARM_AM::ror;<br>
else if (ShiftName == "rrx" || ShiftName == "RRX")<br>
St = ARM_AM::rrx;<br>
+ else if (ShiftName == "uxtw" || ShiftName == "UXTW")<br>
+ St = ARM_AM::uxtw;<br>
else<br>
return Error(Loc, "illegal shift operator");<br>
Parser.Lex(); // Eat shift type token.<br>
@@ -6518,7 +6671,7 @@ void ARMAsmParser::fixupGNULDRDAlias(Str<br>
<br>
if (!Op2.isReg())<br>
return;<br>
- if (!Op3.isMem())<br>
+ if (!Op3.isGPRMem())<br>
return;<br>
<br>
const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);<br>
@@ -7291,6 +7444,54 @@ bool ARMAsmParser::validateInstruction(M<br>
"destination register and base register can't be identical");<br>
return false;<br>
}<br>
+<br>
+ case ARM::MVE_VLDRBU8_rq:<br>
+ case ARM::MVE_VLDRBU16_rq:<br>
+ case ARM::MVE_VLDRBS16_rq:<br>
+ case ARM::MVE_VLDRBU32_rq:<br>
+ case ARM::MVE_VLDRBS32_rq:<br>
+ case ARM::MVE_VLDRHU16_rq:<br>
+ case ARM::MVE_VLDRHU16_rq_u:<br>
+ case ARM::MVE_VLDRHU32_rq:<br>
+ case ARM::MVE_VLDRHU32_rq_u:<br>
+ case ARM::MVE_VLDRHS32_rq:<br>
+ case ARM::MVE_VLDRHS32_rq_u:<br>
+ case ARM::MVE_VLDRWU32_rq:<br>
+ case ARM::MVE_VLDRWU32_rq_u:<br>
+ case ARM::MVE_VLDRDU64_rq:<br>
+ case ARM::MVE_VLDRDU64_rq_u:<br>
+ case ARM::MVE_VLDRWU32_qi:<br>
+ case ARM::MVE_VLDRWU32_qi_pre:<br>
+ case ARM::MVE_VLDRDU64_qi:<br>
+ case ARM::MVE_VLDRDU64_qi_pre: {<br>
+ // Qd must be different from Qm.<br>
+ unsigned QdIdx = 0, QmIdx = 2;<br>
+ bool QmIsPointer = false;<br>
+ switch (Opcode) {<br>
+ case ARM::MVE_VLDRWU32_qi:<br>
+ case ARM::MVE_VLDRDU64_qi:<br>
+ QmIdx = 1;<br>
+ QmIsPointer = true;<br>
+ break;<br>
+ case ARM::MVE_VLDRWU32_qi_pre:<br>
+ case ARM::MVE_VLDRDU64_qi_pre:<br>
+ QdIdx = 1;<br>
+ QmIsPointer = true;<br>
+ break;<br>
+ }<br>
+<br>
+ const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());<br>
+ const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());<br>
+<br>
+ if (Qd == Qm) {<br>
+ return Error(Operands[3]->getStartLoc(),<br>
+ Twine("destination vector register and vector ") +<br>
+ (QmIsPointer ? "pointer" : "offset") +<br>
+ " register can't be identical");<br>
+ }<br>
+ return false;<br>
+ }<br>
+<br>
case ARM::SBFX:<br>
case ARM::t2SBFX:<br>
case ARM::UBFX:<br>
@@ -10042,9 +10243,23 @@ unsigned ARMAsmParser::checkTargetMatchP<br>
for (unsigned I = 0; I < MCID.NumOperands; ++I)<br>
if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {<br>
// rGPRRegClass excludes PC, and also excluded SP before ARMv8<br>
- if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())<br>
+ const auto &Op = Inst.getOperand(I);<br>
+ if (!Op.isReg()) {<br>
+ // This can happen in awkward cases with tied operands, e.g. a<br>
+ // writeback load/store with a complex addressing mode in<br>
+ // which there's an output operand corresponding to the<br>
+ // updated written-back base register: the Tablegen-generated<br>
+ // AsmMatcher will have written a placeholder operand to that<br>
+ // slot in the form of an immediate 0, because it can't<br>
+ // generate the register part of the complex addressing-mode<br>
+ // operand ahead of time.<br>
+ continue;<br>
+ }<br>
+<br>
+ unsigned Reg = Op.getReg();<br>
+ if ((Reg == ARM::SP) && !hasV8Ops())<br>
return Match_RequiresV8;<br>
- else if (Inst.getOperand(I).getReg() == ARM::PC)<br>
+ else if (Reg == ARM::PC)<br>
return Match_InvalidOperand;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Jun 25 04:24:18 2019<br>
@@ -332,6 +332,11 @@ static DecodeStatus DecodeTBLInstruction<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
+static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,<br>
+ uint64_t Address, const void *Decoder);<br>
+template<int shift><br>
+static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,<br>
+ uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,<br>
@@ -428,8 +433,17 @@ static DecodeStatus DecodeT2AddrModeImm0<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
+template<int shift><br>
+static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder);<br>
+template<int shift><br>
+static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder);<br>
+template<int shift, int WriteBack><br>
+static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,<br>
uint64_t Address, const void *Decoder);<br>
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,<br>
@@ -509,6 +523,15 @@ template<bool Writeback><br>
static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,<br>
uint64_t Address,<br>
const void *Decoder);<br>
+template<int shift><br>
+static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder);<br>
+template<int shift><br>
+static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder);<br>
+template<int shift><br>
+static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder);<br>
template<unsigned MinLog, unsigned MaxLog><br>
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,<br>
uint64_t Address,<br>
@@ -4138,6 +4161,21 @@ static DecodeStatus DecodeT2Imm8(MCInst<br>
return MCDisassembler::Success;<br>
}<br>
<br>
+template<int shift><br>
+static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ int imm = Val & 0x7F;<br>
+ if (Val == 0)<br>
+ imm = INT32_MIN;<br>
+ else if (!(Val & 0x80))<br>
+ imm *= -1;<br>
+ if (imm != INT32_MIN)<br>
+ imm <<= shift;<br>
+ Inst.addOperand(MCOperand::createImm(imm));<br>
+<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
DecodeStatus S = MCDisassembler::Success;<br>
@@ -4184,6 +4222,42 @@ static DecodeStatus DecodeT2AddrModeImm8<br>
return S;<br>
}<br>
<br>
+template<int shift><br>
+static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address,<br>
+ const void *Decoder) {<br>
+ DecodeStatus S = MCDisassembler::Success;<br>
+<br>
+ unsigned Rn = fieldFromInstruction(Val, 8, 3);<br>
+ unsigned imm = fieldFromInstruction(Val, 0, 8);<br>
+<br>
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ return S;<br>
+}<br>
+<br>
+template<int shift, int WriteBack><br>
+static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address,<br>
+ const void *Decoder) {<br>
+ DecodeStatus S = MCDisassembler::Success;<br>
+<br>
+ unsigned Rn = fieldFromInstruction(Val, 8, 4);<br>
+ unsigned imm = fieldFromInstruction(Val, 0, 8);<br>
+ if (WriteBack) {<br>
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+ } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ return S;<br>
+}<br>
+<br>
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,<br>
uint64_t Address, const void *Decoder) {<br>
DecodeStatus S = MCDisassembler::Success;<br>
@@ -4331,6 +4405,43 @@ static DecodeStatus DecodePostIdxReg(MCI<br>
return S;<br>
}<br>
<br>
+static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ DecodeStatus S = MCDisassembler::Success;<br>
+ unsigned Rn = fieldFromInstruction(Insn, 3, 4);<br>
+ unsigned Qm = fieldFromInstruction(Insn, 0, 3);<br>
+<br>
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ return S;<br>
+}<br>
+<br>
+template<int shift><br>
+static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ DecodeStatus S = MCDisassembler::Success;<br>
+ unsigned Qm = fieldFromInstruction(Insn, 8, 3);<br>
+ int imm = fieldFromInstruction(Insn, 0, 7);<br>
+<br>
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ if(!fieldFromInstruction(Insn, 7, 1)) {<br>
+ if (imm == 0)<br>
+ imm = INT32_MIN; // indicate -0<br>
+ else<br>
+ imm *= -1;<br>
+ }<br>
+ if (imm != INT32_MIN)<br>
+ imm <<= shift;<br>
+ Inst.addOperand(MCOperand::createImm(imm));<br>
+<br>
+ return S;<br>
+}<br>
+<br>
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,<br>
uint64_t Address, const void *Decoder) {<br>
// Val is passed in as S:J1:J2:imm10H:imm10L:'0'<br>
@@ -6175,6 +6286,52 @@ static DecodeStatus DecodeVSTRVLDR_SYSRE<br>
return S;<br>
}<br>
<br>
+static inline DecodeStatus DecodeMVE_MEM_pre(<br>
+ MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,<br>
+ unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {<br>
+ DecodeStatus S = MCDisassembler::Success;<br>
+<br>
+ unsigned Qd = fieldFromInstruction(Val, 13, 3);<br>
+ unsigned addr = fieldFromInstruction(Val, 0, 7) |<br>
+ (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);<br>
+<br>
+ if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+ if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ return S;<br>
+}<br>
+<br>
+template <int shift><br>
+static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,<br>
+ fieldFromInstruction(Val, 16, 3),<br>
+ DecodetGPRRegisterClass,<br>
+ DecodeTAddrModeImm7<shift>);<br>
+}<br>
+<br>
+template <int shift><br>
+static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,<br>
+ fieldFromInstruction(Val, 16, 4),<br>
+ DecoderGPRRegisterClass,<br>
+ DecodeT2AddrModeImm7<shift,1>);<br>
+}<br>
+<br>
+template <int shift><br>
+static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,<br>
+ fieldFromInstruction(Val, 17, 3),<br>
+ DecodeMQPRRegisterClass,<br>
+ DecodeMveAddrModeQ<shift>);<br>
+}<br>
+<br>
template<unsigned MinLog, unsigned MaxLog><br>
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,<br>
uint64_t Address,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h Tue Jun 25 04:24:18 2019<br>
@@ -30,7 +30,8 @@ namespace ARM_AM {<br>
lsl,<br>
lsr,<br>
ror,<br>
- rrx<br>
+ rrx,<br>
+ uxtw<br>
};<br>
<br>
enum AddrOpc {<br>
@@ -48,6 +49,7 @@ namespace ARM_AM {<br>
case ARM_AM::lsr: return "lsr";<br>
case ARM_AM::ror: return "ror";<br>
case ARM_AM::rrx: return "rrx";<br>
+ case ARM_AM::uxtw: return "uxtw";<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Tue Jun 25 04:24:18 2019<br>
@@ -203,6 +203,8 @@ namespace ARMII {<br>
AddrMode5FP16 = 17, // i8 * 2<br>
AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst<br>
AddrModeT2_i7s4 = 19, // i7 * 4<br>
+ AddrModeT2_i7s2 = 20, // i7 * 2<br>
+ AddrModeT2_i7 = 21, // i7 * 1<br>
};<br>
<br>
inline static const char *AddrModeToString(AddrMode addrmode) {<br>
@@ -227,6 +229,8 @@ namespace ARMII {<br>
case AddrMode_i12: return "AddrMode_i12";<br>
case AddrModeT2_ldrex:return "AddrModeT2_ldrex";<br>
case AddrModeT2_i7s4: return "AddrModeT2_i7s4";<br>
+ case AddrModeT2_i7s2: return "AddrModeT2_i7s2";<br>
+ case AddrModeT2_i7: return "AddrModeT2_i7";<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp Tue Jun 25 04:24:18 2019<br>
@@ -603,6 +603,40 @@ void ARMInstPrinter::printPostIdxImm8s4O<br>
<< markup(">");<br>
}<br>
<br>
+template<int shift><br>
+void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,<br>
+ const MCSubtargetInfo &STI,<br>
+ raw_ostream &O) {<br>
+ const MCOperand &MO1 = MI->getOperand(OpNum);<br>
+ const MCOperand &MO2 = MI->getOperand(OpNum + 1);<br>
+<br>
+ O << markup("<mem:") << "[";<br>
+ printRegName(O, MO1.getReg());<br>
+ O << ", ";<br>
+ printRegName(O, MO2.getReg());<br>
+<br>
+ if (shift > 0)<br>
+ printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);<br>
+<br>
+ O << "]" << markup(">");<br>
+}<br>
+<br>
+void ARMInstPrinter::printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,<br>
+ const MCSubtargetInfo &STI,<br>
+ raw_ostream &O) {<br>
+ const MCOperand &MO1 = MI->getOperand(OpNum);<br>
+ const MCOperand &MO2 = MI->getOperand(OpNum + 1);<br>
+<br>
+ O << markup("<mem:") << "[";<br>
+ printRegName(O, MO1.getReg());<br>
+<br>
+ int64_t Imm = MO2.getImm();<br>
+ if (Imm != 0)<br>
+ O << ", " << markup("<imm:") << '#' << Imm << markup(">");<br>
+<br>
+ O << "]" << markup(">");<br>
+}<br>
+<br>
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,<br>
const MCSubtargetInfo &STI,<br>
raw_ostream &O) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h Tue Jun 25 04:24:18 2019<br>
@@ -255,6 +255,11 @@ public:<br>
raw_ostream &O);<br>
void printVPTMask(const MCInst *MI, unsigned OpNum,<br>
const MCSubtargetInfo &STI, raw_ostream &O);<br>
+ template<int shift><br>
+ void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,<br>
+ const MCSubtargetInfo &STI, raw_ostream &O);<br>
+ void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,<br>
+ const MCSubtargetInfo &STI, raw_ostream &O);<br>
void printExpandedImmOperand(const MCInst *MI, unsigned OpNum,<br>
const MCSubtargetInfo &STI, raw_ostream &O);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Jun 25 04:24:18 2019<br>
@@ -208,6 +208,19 @@ public:<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
const MCSubtargetInfo &STI) const;<br>
<br>
+ /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'<br>
+ /// operand.<br>
+ uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const;<br>
+<br>
+ /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'<br>
+ /// operand.<br>
+ template<int shift><br>
+ uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const;<br>
+<br>
/// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'<br>
/// operand as needed by load/store instructions.<br>
uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,<br>
@@ -238,8 +251,10 @@ public:<br>
case ARM_AM::asr: return 2;<br>
case ARM_AM::ror:<br>
case ARM_AM::rrx: return 3;<br>
+ case ARM_AM::uxtw:<br>
+ default:<br>
+ llvm_unreachable("Invalid ShiftOpc!");<br>
}<br>
- llvm_unreachable("Invalid ShiftOpc!");<br>
}<br>
<br>
/// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.<br>
@@ -338,7 +353,8 @@ public:<br>
unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
const MCSubtargetInfo &STI) const;<br>
- unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,<br>
+ template<unsigned Bits, unsigned Shift><br>
+ unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
const MCSubtargetInfo &STI) const;<br>
unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,<br>
@@ -1040,6 +1056,58 @@ getT2ScaledImmOpValue(const MCInst &MI,<br>
Binary |= (1U << Bits);<br>
return Binary;<br>
}<br>
+<br>
+/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'<br>
+/// operand.<br>
+uint32_t ARMMCCodeEmitter::<br>
+getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const {<br>
+ // {6-3} Rn<br>
+ // {2-0} Qm<br>
+ const MCOperand &M0 = MI.getOperand(OpIdx);<br>
+ const MCOperand &M1 = MI.getOperand(OpIdx + 1);<br>
+<br>
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());<br>
+ unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());<br>
+<br>
+ assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");<br>
+<br>
+ return (Rn << 3) | Qm;<br>
+}<br>
+<br>
+/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'<br>
+/// operand.<br>
+template<int shift><br>
+uint32_t ARMMCCodeEmitter::<br>
+getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const {<br>
+ // {10-8} Qm<br>
+ // {7-0} Imm<br>
+ const MCOperand &M0 = MI.getOperand(OpIdx);<br>
+ const MCOperand &M1 = MI.getOperand(OpIdx + 1);<br>
+<br>
+ unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());<br>
+ int32_t Imm = M1.getImm();<br>
+<br>
+ bool isAdd = Imm >= 0;<br>
+<br>
+ Imm >>= shift;<br>
+<br>
+ if (!isAdd)<br>
+ Imm = -(uint32_t)Imm;<br>
+<br>
+ Imm &= 0x7f;<br>
+<br>
+ if (isAdd)<br>
+ Imm |= 0x80;<br>
+<br>
+ assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");<br>
+<br>
+ return (Qm << 8) | Imm;<br>
+}<br>
+<br>
/// getT2AddrModeImm8s4OpValue - Return encoding info for<br>
/// 'reg +/- imm8<<2' operand.<br>
uint32_t ARMMCCodeEmitter::<br>
@@ -1540,25 +1608,26 @@ getT2AddrModeSORegOpValue(const MCInst &<br>
return Value;<br>
}<br>
<br>
+template<unsigned Bits, unsigned Shift><br>
unsigned ARMMCCodeEmitter::<br>
-getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,<br>
- SmallVectorImpl<MCFixup> &Fixups,<br>
- const MCSubtargetInfo &STI) const {<br>
+getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,<br>
+ SmallVectorImpl<MCFixup> &Fixups,<br>
+ const MCSubtargetInfo &STI) const {<br>
const MCOperand &MO1 = MI.getOperand(OpNum);<br>
const MCOperand &MO2 = MI.getOperand(OpNum+1);<br>
<br>
// FIXME: Needs fixup support.<br>
unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());<br>
<br>
- // Even though the immediate is 8 bits long, we need 9 bits in order<br>
+ // If the immediate is B bits long, we need B+1 bits in order<br>
// to represent the (inverse of the) sign bit.<br>
- Value <<= 9;<br>
- int32_t tmp = (int32_t)MO2.getImm();<br>
+ Value <<= (Bits + 1);<br>
+ int32_t tmp = (int32_t)MO2.getImm() >> Shift;<br>
if (tmp < 0)<br>
tmp = abs(tmp);<br>
else<br>
- Value |= 256; // Set the ADD bit<br>
- Value |= tmp & 255;<br>
+ Value |= (1U << Bits); // Set the ADD bit<br>
+ Value |= tmp & ((1U << Bits) - 1);<br>
return Value;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=364291&r1=364290&r2=364291&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=364291&r1=364290&r2=364291&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Jun 25 04:24:18 2019<br>
@@ -610,17 +610,23 @@ bool llvm::rewriteT2FrameIndex(MachineIn<br>
Offset = -Offset;<br>
isSub = true;<br>
}<br>
- } else if (AddrMode == ARMII::AddrModeT2_i7s4) {<br>
+ } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||<br>
+ AddrMode == ARMII::AddrModeT2_i7s2 ||<br>
+ AddrMode == ARMII::AddrModeT2_i7) {<br>
Offset += MI.getOperand(FrameRegIdx + 1).getImm();<br>
- NumBits = 9; // 7 bits scaled by 4<br>
- unsigned OffsetMask = 0x3;<br>
+ unsigned OffsetMask;<br>
+ switch (AddrMode) {<br>
+ case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;<br>
+ case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;<br>
+ default: NumBits = 7; OffsetMask = 0x0; break;<br>
+ }<br>
// MCInst operand expects already scaled value.<br>
Scale = 1;<br>
assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");<br>
(void)OffsetMask; // squash unused-variable warning at -NDEBUG<br>
} else if (AddrMode == ARMII::AddrModeT2_i8s4) {<br>
Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;<br>
- NumBits = 10; // 8 bits scaled by 4<br>
+ NumBits = 8 + 2;<br>
// MCInst operand expects already scaled value.<br>
Scale = 1;<br>
assert((Offset & 3) == 0 && "Can't encode this offset!");<br>
<br>
Added: llvm/trunk/test/MC/ARM/mve-load-store.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-load-store.s?rev=364291&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-load-store.s?rev=364291&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/mve-load-store.s (added)<br>
+++ llvm/trunk/test/MC/ARM/mve-load-store.s Tue Jun 25 04:24:18 2019<br>
@@ -0,0 +1,1944 @@<br>
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \<br>
+# RUN: | FileCheck --check-prefix=CHECK %s<br>
+# RUN: FileCheck --check-prefix=ERROR < %t %s<br>
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t<br>
+# RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r0]<br>
+<br>
+# CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q1, [r0]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r11]<br>
+<br>
+# CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q3, [r11]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r8, #56]<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q5, [r4], #-25<br>
+<br>
+# CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q5, [r10], #-25<br>
+<br>
+# CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q5, [sp, #-25]<br>
+<br>
+# CHECK: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q5, [sp, #-127]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r0, #128]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r0, #-128]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r0], #128<br>
+<br>
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q0, [r0]<br>
+<br>
+# CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q1, [r0]<br>
+<br>
+# CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q0, [r11]<br>
+<br>
+# CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q3, [r11]<br>
+<br>
+# CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q0, [r8, #56]<br>
+<br>
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q5, [r4], #-25<br>
+<br>
+# CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q5, [r10], #-25<br>
+<br>
+# CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q5, [sp, #-25]<br>
+<br>
+# CHECK: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q5, [sp, #127]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q0, [r0, #128]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q0, [r0, #-128]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q0, [r0], #128<br>
+<br>
+# CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q0, [r0]<br>
+<br>
+# CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q1, [r0]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q0, [r7]<br>
+<br>
+# CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q3, [r7]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q0, [r2, #56]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q5, [r4], #-1<br>
+<br>
+# CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q5, [r3], #-25<br>
+<br>
+# CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q5, [r6, #-25]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q5, [r6, #-64]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q0, [r0]<br>
+<br>
+# CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q1, [r0]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q0, [r7]<br>
+<br>
+# CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q3, [r7]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q0, [r2, #56]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q5, [r4], #-25<br>
+<br>
+# CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q5, [r3], #-25<br>
+<br>
+# CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q5, [r6, #-25]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q5, [r6, #-64]<br>
+<br>
+# CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q0, [r0]<br>
+<br>
+# CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q1, [r0]<br>
+<br>
+# CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q0, [r7]<br>
+<br>
+# CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q3, [r7]<br>
+<br>
+# CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q0, [r5, #56]<br>
+<br>
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q5, [r4], #-25<br>
+<br>
+# CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q5, [r3], #-25<br>
+<br>
+# CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q5, [r2, #-25]<br>
+<br>
+# CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q5, [r2, #-64]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q0, [r0]<br>
+<br>
+# CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q1, [r0]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q0, [r7]<br>
+<br>
+# CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q3, [r7]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q0, [r2, #56]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q5, [r4], #-25<br>
+<br>
+# CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q5, [r3], #-25<br>
+<br>
+# CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q5, [r6, #-25]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q5, [r6, #-64]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q0, [r0]<br>
+<br>
+# CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q1, [r0]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q0, [r7]<br>
+<br>
+# CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q3, [r7]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q0, [r2, #56]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q5, [r4], #-25<br>
+<br>
+# CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q5, [r3], #-25<br>
+<br>
+# CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q5, [r6, #-25]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q5, [r6, #-64]<br>
+<br>
+# CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q0, [r0]<br>
+<br>
+# CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q1, [r0]<br>
+<br>
+# CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q0, [r7]<br>
+<br>
+# CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q3, [r7]<br>
+<br>
+# CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q0, [r5, #56]<br>
+<br>
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q5, [r4], #-25<br>
+<br>
+# CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q5, [r3], #-25<br>
+<br>
+# CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q5, [r2, #-25]<br>
+<br>
+# CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q5, [r2, #-64]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r0]<br>
+<br>
+# CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q1, [r0]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r11]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q3, [r11]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r8, #56]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [r4], #-26<br>
+<br>
+# CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [r10], #-26<br>
+<br>
+# CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [sp, #-26]<br>
+<br>
+# CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [sp, #-64]<br>
+<br>
+# CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [sp, #-254]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q5, [r10], #254<br>
+<br>
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r0]<br>
+<br>
+# CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q1, [r0]<br>
+<br>
+# CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r11]<br>
+<br>
+# CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q3, [r11]<br>
+<br>
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r8, #56]<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [r4], #-26<br>
+<br>
+# CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [r10], #-26<br>
+<br>
+# CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [sp, #-26]<br>
+<br>
+# CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [sp, #-64]<br>
+<br>
+# CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [sp, #-254]<br>
+<br>
+# CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q5, [r10], #254<br>
+<br>
+# CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r0]<br>
+<br>
+# CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q1, [r0]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r7]<br>
+<br>
+# CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q3, [r7]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r2, #56]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r4], #-26<br>
+<br>
+# CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r3], #-26<br>
+<br>
+# CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r6, #-26]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r6, #-64]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r6, #-254]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q5, [r4, #254]!<br>
+<br>
+# CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r0]<br>
+<br>
+# CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q1, [r0]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r7]<br>
+<br>
+# CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q3, [r7]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r2, #56]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r4], #-26<br>
+<br>
+# CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r3], #-26<br>
+<br>
+# CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r6, #-26]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r6, #-64]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r6, #-254]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q5, [r4, #254]!<br>
+<br>
+# CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q0, [r0]<br>
+<br>
+# CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q1, [r0]<br>
+<br>
+# CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q0, [r7]<br>
+<br>
+# CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q3, [r7]<br>
+<br>
+# CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q0, [r5, #56]<br>
+<br>
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r4], #-26<br>
+<br>
+# CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r3], #-26<br>
+<br>
+# CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r2, #-26]<br>
+<br>
+# CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r2, #-64]<br>
+<br>
+# CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r2, #-254]<br>
+<br>
+# CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q5, [r4, #254]!<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r0]<br>
+<br>
+# CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q1, [r0]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r11]<br>
+<br>
+# CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q3, [r11]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q4, [r4, #56]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r8, #56]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [r4], #-28<br>
+<br>
+# CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [r10], #-28<br>
+<br>
+# CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [sp, #-28]<br>
+<br>
+# CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [sp, #-64]<br>
+<br>
+# CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [sp, #-508]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q5, [r4, #508]!<br>
+<br>
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [r0]<br>
+<br>
+# CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q1, [r0]<br>
+<br>
+# CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [r11]<br>
+<br>
+# CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q3, [r11]<br>
+<br>
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [r8, #56]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [r4], #-28<br>
+<br>
+# CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [r10], #-28<br>
+<br>
+# CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [sp, #-28]<br>
+<br>
+# CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [sp, #-64]<br>
+<br>
+# CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [sp, #-508]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [r4, #508]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q0, [r8]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r8]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [sp, #-64]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [sp, #-3]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q5, [sp, #512]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q3, [r10, q1]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q3, [r9, q1]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q3, [sp, q1]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q3, [r0, q1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u8 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u16 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s16 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.u32 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s32 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r0, q0, uxtw #1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u32 q0, [r0, q0, uxtw #1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s32 q0, [r0, q0, uxtw #1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r0, q0, uxtw #2]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [r0, q0]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [r0, q0, uxtw #3]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.u16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [sp, q1, uxtw #2]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [sp, q1, uxtw #3]<br>
+<br>
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q3, [r10, q1]<br>
+<br>
+# CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.8 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q3, [sp, q1]<br>
+<br>
+# CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.16 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.32 q3, [r8, q3, uxtw #1]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [sp, q1, uxtw #2]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q3, [r0, q3]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q0, [sp, q1, uxtw #3]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q9, [sp, q1, uxtw #2]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q3, [pc, q1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q0, [r0, q1, uxtw #1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [r0, q1, uxtw #1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q0, [r0, q1, uxtw #2]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [r0, q1, uxtw #2]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [r0, q1, uxtw #1]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.16 q0, [r0, q1, uxtw #2]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.32 q0, [r11, q1, uxtw #1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q0, [q1]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1]!<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #4]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #-4]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #508]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #-508]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #264]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #4]!<br>
+<br>
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q0, [q1]<br>
+<br>
+# CHECK: vstrw.32 q1, [q1] @ encoding: [0x82,0xfd,0x00,0x3e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q1, [q1]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1]!<br>
+<br>
+# CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q7]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1, #4]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1, #-4]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1, #508]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1, #-508]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q7, [q1, #264]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q8, [q1]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.32 q4, [q1, #3]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #512]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector pointer register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q1, [q1, #264]<br>
+<br>
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q0, [q1]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1]!<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #8]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #-8]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #1016]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #-1016]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #264]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #624]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #264]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q7, [q1, #-1016]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector pointer register can't be identical<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q6, [q6]<br>
+<br>
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q0, [q1]<br>
+<br>
+# CHECK: vstrd.64 q1, [q1] @ encoding: [0x82,0xfd,0x00,0x3f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q1, [q1]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q7]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #8]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #-8]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #1016]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #-1016]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #264]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #624]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #264]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.u64 q8, [q1]!<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q7, [q1, #1024]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q4, [q1, #3]<br>
+<br>
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.64 q4, [q1, #4]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s8 q0, [r0]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.8 q0, [r0]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s8 q0, [r8, #56]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.8 q0, [r8, #56]<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q0, [r0]<br>
+<br>
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.s8 q0, [r0]<br>
+<br>
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.s8 q4, [r4, #56]<br>
+<br>
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.s8 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s16 q0, [r0]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.f16 q0, [r0]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.16 q0, [r0]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s16 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.f16 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.16 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.f16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.u16 q0, [r0]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.s16 q0, [r0]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.f16 q0, [r0]<br>
+<br>
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.u16 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.s16 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.f16 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.u16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.s16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.f16 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q0, [r0]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q0, [r0]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q0, [r0]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q0, [r4, #56]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q0, [r0]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q0, [r0]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q0, [r0]<br>
+<br>
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q0, [r4, #56]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q5, [r4, #56]!<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.s8 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrb.8 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s16 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.f16 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.16 q3, [r0, q1]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.s16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.f16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrh.16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.s64 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.f64 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.64 q0, [r0, q1]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.s64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.f64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.u8 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrb.s8 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.u16 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.s16 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.f16 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.u16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.s16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrh.f16 q0, [r0, q1, uxtw #1]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q0, [r0, q1]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q0, [r0, q1, uxtw #2]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.u64 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.s64 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.f64 q3, [r0, q1]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.u64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.s64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.f64 q0, [r0, q1, uxtw #3]<br>
+<br>
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q0, [q1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q0, [q1]<br>
+<br>
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q0, [q1]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q7, [q1]!<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q7, [q1]!<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q7, [q1]!<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q7, [q1, #4]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q7, [q1, #4]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.32 q7, [q1, #4]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.s32 q7, [q1, #4]!<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.f32 q7, [q1, #4]!<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrw.u32 q7, [q1, #4]!<br>
+<br>
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q0, [q1]<br>
+<br>
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q0, [q1]<br>
+<br>
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q0, [q1]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q7, [q1]!<br>
+<br>
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q7, [q1]!<br>
+<br>
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q7, [q1]!<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q7, [q1, #508]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q7, [q1, #508]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q7, [q1, #508]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.u32 q7, [q1, #264]!<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.s32 q7, [q1, #264]!<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrw.f32 q7, [q1, #264]!<br>
+<br>
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.s64 q0, [q1]<br>
+<br>
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.f64 q0, [q1]<br>
+<br>
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.64 q0, [q1]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.s64 q7, [q1]!<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.f64 q7, [q1]!<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.64 q7, [q1]!<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.s64 q7, [q1, #8]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.f64 q7, [q1, #8]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.64 q7, [q1, #8]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.s64 q7, [q1, #-1016]!<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.f64 q7, [q1, #-1016]!<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vldrd.64 q7, [q1, #-1016]!<br>
+<br>
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.u64 q0, [q1]<br>
+<br>
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.s64 q0, [q1]<br>
+<br>
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.f64 q0, [q1]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.u64 q7, [q1]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.s64 q7, [q1]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.f64 q7, [q1]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.u64 q7, [q1, #1016]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.s64 q7, [q1, #1016]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.f64 q7, [q1, #1016]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.u64 q7, [q1, #-8]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.s64 q7, [q1, #-8]!<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]<br>
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction<br>
+vstrd.f64 q7, [q1, #-8]!<br>
+<br>
+vpste<br>
+vstrwt.f32 q7, [q1, #264]!<br>
+vldrde.64 q7, [q1, #8]<br>
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]<br>
+# CHECK: vstrwt.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]<br>
+# CHECK: vldrde.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]<br>
<br>
Propchange: llvm/trunk/test/MC/ARM/mve-load-store.s<br>
------------------------------------------------------------------------------<br>
svn:eol-style = native<br>
<br>
Propchange: llvm/trunk/test/MC/ARM/mve-load-store.s<br>
------------------------------------------------------------------------------<br>
svn:keywords = Rev Date Author URL Id<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt?rev=364291&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt?rev=364291&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt Tue Jun 25 04:24:18 2019<br>
@@ -0,0 +1,1378 @@<br>
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s<br>
+# RUN: FileCheck --check-prefix=ERROR < %t %s<br>
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t<br>
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x00,0x1e]<br>
+<br>
+# CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x00,0x3e]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9b,0xed,0x00,0x1e]<br>
+<br>
+# CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9b,0xed,0x00,0x7e]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x38,0x1e]<br>
+<br>
+# CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x38,0x9e]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xed,0x38,0x1e]<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x38,0xbe]<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x38,0xbe]<br>
+<br>
+# CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xec,0x19,0xbe]<br>
+<br>
+# CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3a,0xec,0x19,0xbe]<br>
+<br>
+# CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0x19,0xbe]<br>
+<br>
+# CHECK: vldrb.u8 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x40,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0x40,0xbe]<br>
+<br>
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x00,0x1e]<br>
+<br>
+# CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x00,0x3e]<br>
+<br>
+# CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8b,0xed,0x00,0x1e]<br>
+<br>
+# CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8b,0xed,0x00,0x7e]<br>
+<br>
+# CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x38,0x1e]<br>
+<br>
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x38,0x9e]<br>
+<br>
+# CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x88,0xed,0x38,0x1e]<br>
+<br>
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x38,0xbe]<br>
+<br>
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x38,0xbe]<br>
+<br>
+# CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x24,0xec,0x19,0xbe]<br>
+<br>
+# CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x2a,0xec,0x19,0xbe]<br>
+<br>
+# CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0x19,0xbe]<br>
+<br>
+# CHECK: vstrb.8 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x40,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0x40,0xbe]<br>
+<br>
+# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding<br>
+[0xad,0xec,0x00,0x1e]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfd,0x80,0x0e]<br>
+<br>
+# CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfd,0x80,0x2e]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xfd,0x80,0x0e]<br>
+<br>
+# CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xfd,0x80,0x6e]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xfd,0xb8,0x0e]<br>
+<br>
+# CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xfd,0xb8,0x8e]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0xb8,0x0e]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xfd,0xb8,0xae]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xfd,0xb8,0xae]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xfc,0x99,0xae]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x33,0xfc,0x99,0xae]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xfd,0x99,0xae]<br>
+<br>
+# CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xfd,0xc0,0xae]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x80,0x0e]<br>
+<br>
+# CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x80,0x2e]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xed,0x80,0x0e]<br>
+<br>
+# CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xed,0x80,0x6e]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0xb8,0x0e]<br>
+<br>
+# CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0xb8,0x8e]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xed,0xb8,0x0e]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0xb8,0xae]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0xb8,0xae]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xec,0x99,0xae]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x33,0xec,0x99,0xae]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xed,0x99,0xae]<br>
+<br>
+# CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xed,0xc0,0xae]<br>
+<br>
+# CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x80,0x0e]<br>
+<br>
+# CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x80,0x2e]<br>
+<br>
+# CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x87,0xed,0x80,0x0e]<br>
+<br>
+# CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x87,0xed,0x80,0x6e]<br>
+<br>
+# CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0xb8,0x0e]<br>
+<br>
+# CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0xb8,0x8e]<br>
+<br>
+# CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x85,0xed,0xb8,0x0e]<br>
+<br>
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0xb8,0xae]<br>
+<br>
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0xb8,0xae]<br>
+<br>
+# CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x24,0xec,0x99,0xae]<br>
+<br>
+# CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x23,0xec,0x99,0xae]<br>
+<br>
+# CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xed,0x99,0xae]<br>
+<br>
+# CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xed,0xc0,0xae]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfd,0x00,0x0f]<br>
+<br>
+# CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfd,0x00,0x2f]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xfd,0x00,0x0f]<br>
+<br>
+# CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xfd,0x00,0x6f]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xfd,0x38,0x0f]<br>
+<br>
+# CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xfd,0x38,0x8f]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x38,0x0f]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xfd,0x38,0xaf]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xfd,0x38,0xaf]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xfc,0x19,0xaf]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x33,0xfc,0x19,0xaf]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xfd,0x19,0xaf]<br>
+<br>
+# CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xfd,0x40,0xaf]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x97,0xed,0x00,0x6f]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x38,0x0f]<br>
+<br>
+# CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x38,0x8f]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xed,0x38,0x0f]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x38,0xaf]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x38,0xaf]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xec,0x19,0xaf]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x33,0xec,0x19,0xaf]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xed,0x19,0xaf]<br>
+<br>
+# CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x16,0xed,0x40,0xaf]<br>
+<br>
+# CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x87,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x87,0xed,0x00,0x6f]<br>
+<br>
+# CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x38,0x0f]<br>
+<br>
+# CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x38,0x8f]<br>
+<br>
+# CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x85,0xed,0x38,0x0f]<br>
+<br>
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x38,0xaf]<br>
+<br>
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x38,0xaf]<br>
+<br>
+# CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x24,0xec,0x19,0xaf]<br>
+<br>
+# CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x23,0xec,0x19,0xaf]<br>
+<br>
+# CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xed,0x19,0xaf]<br>
+<br>
+# CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xed,0x40,0xaf]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x80,0x1e]<br>
+<br>
+# CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x80,0x3e]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9b,0xed,0x80,0x1e]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9b,0xed,0x80,0x7e]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x9c,0x1e]<br>
+<br>
+# CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x9c,0x9e]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xed,0x9c,0x1e]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x9c,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x9c,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xec,0x8d,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3a,0xec,0x8d,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0x8d,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0xa0,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0xff,0xbe]<br>
+<br>
+# CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xba,0xec,0xff,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x80,0x1e]<br>
+<br>
+# CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x80,0x3e]<br>
+<br>
+# CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8b,0xed,0x80,0x1e]<br>
+<br>
+# CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8b,0xed,0x80,0x7e]<br>
+<br>
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x9c,0x1e]<br>
+<br>
+# CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x9c,0x9e]<br>
+<br>
+# CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x88,0xed,0x9c,0x1e]<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x9c,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x9c,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x24,0xec,0x8d,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x2a,0xec,0x8d,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0x8d,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0xa0,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0xff,0xbe]<br>
+<br>
+# CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xaa,0xec,0xff,0xbe]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xfd,0x00,0x0f]<br>
+<br>
+# CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xfd,0x00,0x2f]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9f,0xfd,0x00,0x0f]<br>
+<br>
+# CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9f,0xfd,0x00,0x6f]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9c,0xfd,0x1c,0x0f]<br>
+<br>
+# CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9c,0xfd,0x1c,0x8f]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9a,0xfd,0x1c,0x0f]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbc,0xfd,0x1c,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbc,0xfd,0x1c,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3c,0xfc,0x0d,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3b,0xfc,0x0d,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1e,0xfd,0x0d,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1e,0xfd,0x20,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1e,0xfd,0x7f,0xaf]<br>
+<br>
+# CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbc,0xfd,0x7f,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9f,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9f,0xed,0x00,0x6f]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9c,0xed,0x1c,0x0f]<br>
+<br>
+# CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9c,0xed,0x1c,0x8f]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9a,0xed,0x1c,0x0f]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbc,0xed,0x1c,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbc,0xed,0x1c,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3c,0xec,0x0d,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3b,0xec,0x0d,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1e,0xed,0x0d,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1e,0xed,0x20,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1e,0xed,0x7f,0xaf]<br>
+<br>
+# CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbc,0xed,0x7f,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x88,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x88,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8f,0xed,0x00,0x0f]<br>
+<br>
+# CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8f,0xed,0x00,0x6f]<br>
+<br>
+# CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8c,0xed,0x1c,0x0f]<br>
+<br>
+# CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8c,0xed,0x1c,0x8f]<br>
+<br>
+# CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8d,0xed,0x1c,0x0f]<br>
+<br>
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xac,0xed,0x1c,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xac,0xed,0x1c,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x2c,0xec,0x0d,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x2b,0xec,0x0d,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0a,0xed,0x0d,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0a,0xed,0x20,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0a,0xed,0x7f,0xaf]<br>
+<br>
+# CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xac,0xed,0x7f,0xaf]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x00,0x1f]<br>
+<br>
+# CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xed,0x00,0x3f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9b,0xed,0x00,0x1f]<br>
+<br>
+# CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9b,0xed,0x00,0x7f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x0e,0x1f]<br>
+<br>
+# CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x94,0xed,0x0e,0x9f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xed,0x0e,0x1f]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x0e,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x0e,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x34,0xec,0x07,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x3a,0xec,0x07,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0x07,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0x10,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x1d,0xed,0x7f,0xbf]<br>
+<br>
+# CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb4,0xed,0x7f,0xbf]<br>
+<br>
+# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xbd,0xed,0x7f,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x00,0x1f]<br>
+<br>
+# CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xed,0x00,0x3f]<br>
+<br>
+# CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8b,0xed,0x00,0x1f]<br>
+<br>
+# CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8b,0xed,0x00,0x7f]<br>
+<br>
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x0e,0x1f]<br>
+<br>
+# CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x84,0xed,0x0e,0x9f]<br>
+<br>
+# CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x88,0xed,0x0e,0x1f]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x0e,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x0e,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x24,0xec,0x07,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x2a,0xec,0x07,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0x07,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0x10,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x0d,0xed,0x7f,0xbf]<br>
+<br>
+# CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa4,0xed,0x7f,0xbf]<br>
+<br>
+# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xad,0xed,0x7f,0xbf]<br>
+<br>
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x02,0x0e]<br>
+<br>
+# CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9a,0xfc,0x02,0x6e]<br>
+<br>
+# CHECK: vldrb.u8 q3, [r0, q3] @ encoding: [0x90,0xfc,0x06,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x06,0x6e]<br>
+<br>
+# CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x82,0x0e]<br>
+<br>
+# CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x99,0xfc,0x82,0x6e]<br>
+<br>
+# CHECK: vldrb.u16 q3, [r0, q3] @ encoding: [0x90,0xfc,0x86,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x86,0x6e]<br>
+<br>
+# CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x82,0x0e]<br>
+<br>
+# CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9d,0xec,0x82,0x6e]<br>
+<br>
+# CHECK: vldrb.s16 q3, [r0, q3] @ encoding: [0x90,0xec,0x86,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x86,0x6e]<br>
+<br>
+# CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x02,0x0f]<br>
+<br>
+# CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x02,0x6f]<br>
+<br>
+# CHECK: vldrb.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x06,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x06,0x6f]<br>
+<br>
+# CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x02,0x0f]<br>
+<br>
+# CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x02,0x6f]<br>
+<br>
+# CHECK: vldrb.s32 q3, [r0, q3] @ encoding: [0x90,0xec,0x06,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x06,0x6f]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x92,0x0e]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x92,0x6e]<br>
+<br>
+# CHECK: vldrh.u16 q3, [r0, q3] @ encoding: [0x90,0xfc,0x96,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x96,0x6e]<br>
+<br>
+# CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x12,0x0f]<br>
+<br>
+# CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x12,0x6f]<br>
+<br>
+# CHECK: vldrh.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x16,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x16,0x6f]<br>
+<br>
+# CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x12,0x0f]<br>
+<br>
+# CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x12,0x6f]<br>
+<br>
+# CHECK: vldrh.s32 q3, [r0, q3] @ encoding: [0x90,0xec,0x16,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xec,0x16,0x6f]<br>
+<br>
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x93,0x0e]<br>
+<br>
+# CHECK: vldrh.u32 q3, [r8, q3, uxtw #1] @ encoding: [0x98,0xfc,0x17,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x98,0xfc,0x17,0x6f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x42,0x0f]<br>
+<br>
+# CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x42,0x6f]<br>
+<br>
+# CHECK: vldrw.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x46,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x46,0x6f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0x43,0x0f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9d,0xfc,0x43,0x0f]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0xd2,0x0f]<br>
+<br>
+# CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0xd2,0x6f]<br>
+<br>
+# CHECK: vldrd.u64 q3, [r0, q3] @ encoding: [0x90,0xfc,0xd6,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0xd6,0x6f]<br>
+<br>
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x90,0xfc,0xd3,0x0f]<br>
+<br>
+# CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9d,0xfc,0xd3,0x0f]<br>
+<br>
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x02,0x0e]<br>
+<br>
+# CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8a,0xec,0x02,0x6e]<br>
+<br>
+# CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x06,0x6e]<br>
+<br>
+# CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x82,0x0e]<br>
+<br>
+# CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8d,0xec,0x82,0x6e]<br>
+<br>
+# CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x86,0x6e]<br>
+<br>
+# CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x02,0x0f]<br>
+<br>
+# CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x02,0x6f]<br>
+<br>
+# CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x06,0x6f]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x92,0x0e]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x92,0x6e]<br>
+<br>
+# CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x96,0x6e]<br>
+<br>
+# CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x12,0x0f]<br>
+<br>
+# CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x12,0x6f]<br>
+<br>
+# CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x16,0x6f]<br>
+<br>
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x93,0x0e]<br>
+<br>
+# CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x88,0xec,0x17,0x6f]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x42,0x0f]<br>
+<br>
+# CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x42,0x6f]<br>
+<br>
+# CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x46,0x6f]<br>
+<br>
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0x43,0x0f]<br>
+<br>
+# CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8d,0xec,0x43,0x0f]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0xd2,0x0f]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0xd2,0x6f]<br>
+<br>
+# CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0xd6,0x6f]<br>
+<br>
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x80,0xec,0xd3,0x0f]<br>
+<br>
+# CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8d,0xec,0xd3,0x0f]<br>
+<br>
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x00,0x1e]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x00,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb2,0xfd,0x00,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q7] @ encoding: [0x9e,0xfd,0x00,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9e,0xfd,0x00,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x01,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x12,0xfd,0x01,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x7f,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x12,0xfd,0x7f,0xfe]<br>
+<br>
+# CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x42,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x00,0x1e]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x00,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa2,0xfd,0x00,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8e,0xfd,0x00,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x01,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xfd,0x01,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x7f,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xfd,0x7f,0xfe]<br>
+<br>
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa2,0xfd,0x42,0xfe]<br>
+<br>
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x00,0x1f]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x00,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xb2,0xfd,0x00,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q7] @ encoding: [0x9e,0xfd,0x00,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x9e,0xfd,0x00,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x01,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x12,0xfd,0x01,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x7f,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x12,0xfd,0x7f,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x21,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x4e,0xff]<br>
+<br>
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x92,0xfd,0x21,0xff]<br>
+<br>
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x00,0x1f]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x00,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0xa2,0xfd,0x00,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x8e,0xfd,0x00,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x01,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x22,0xfd,0x01,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x7f,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x02,0xfd,0x7f,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x21,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x4e,0xff]<br>
+<br>
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]<br>
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding<br>
+[0x82,0xfd,0x21,0xff]<br>
+<br>
+# CHECK: vldrb.u8 q1, [r2] @ encoding: [0x92,0xed,0x00,0x3e]<br>
+[0x92,0xed,0x00,0x3e]<br>
+<br>
+# CHECK: vldrb.u8 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x3e]<br>
+[0x12,0xed,0x00,0x3e]<br>
+<br>
+# CHECK: vldrb.u16 q1, [r2] @ encoding: [0x92,0xfd,0x80,0x2e]<br>
+[0x92,0xfd,0x80,0x2e]<br>
+<br>
+# CHECK: vldrb.u16 q1, [r2, #-0] @ encoding: [0x12,0xfd,0x80,0x2e]<br>
+[0x12,0xfd,0x80,0x2e]<br>
+<br>
+# CHECK: vldrb.s16 q1, [r2] @ encoding: [0x92,0xed,0x80,0x2e]<br>
+[0x92,0xed,0x80,0x2e]<br>
+<br>
+# CHECK: vldrb.s16 q1, [r2, #-0] @ encoding: [0x12,0xed,0x80,0x2e]<br>
+[0x12,0xed,0x80,0x2e]<br>
+<br>
+# CHECK: vldrb.u32 q1, [r2] @ encoding: [0x92,0xfd,0x00,0x2f]<br>
+[0x92,0xfd,0x00,0x2f]<br>
+<br>
+# CHECK: vldrb.u32 q1, [r2, #-0] @ encoding: [0x12,0xfd,0x00,0x2f]<br>
+[0x12,0xfd,0x00,0x2f]<br>
+<br>
+# CHECK: vldrb.s32 q1, [r2] @ encoding: [0x92,0xed,0x00,0x2f]<br>
+[0x92,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vldrb.s32 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x2f]<br>
+[0x12,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vldrh.u16 q1, [r2] @ encoding: [0x92,0xed,0x80,0x3e]<br>
+[0x92,0xed,0x80,0x3e]<br>
+<br>
+# CHECK: vldrh.u16 q1, [r2, #-0] @ encoding: [0x12,0xed,0x80,0x3e]<br>
+[0x12,0xed,0x80,0x3e]<br>
+<br>
+# CHECK: vldrh.u32 q1, [r2] @ encoding: [0x9a,0xfd,0x00,0x2f]<br>
+[0x9a,0xfd,0x00,0x2f]<br>
+<br>
+# CHECK: vldrh.u32 q1, [r2, #-0] @ encoding: [0x1a,0xfd,0x00,0x2f]<br>
+[0x1a,0xfd,0x00,0x2f]<br>
+<br>
+# CHECK: vldrh.s32 q1, [r2] @ encoding: [0x9a,0xed,0x00,0x2f]<br>
+[0x9a,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vldrh.s32 q1, [r2, #-0] @ encoding: [0x1a,0xed,0x00,0x2f]<br>
+[0x1a,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vldrw.u32 q1, [r2] @ encoding: [0x92,0xed,0x00,0x3f]<br>
+[0x92,0xed,0x00,0x3f]<br>
+<br>
+# CHECK: vldrw.u32 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x3f]<br>
+[0x12,0xed,0x00,0x3f]<br>
+<br>
+# CHECK: vldrw.u32 q1, [q2] @ encoding: [0x94,0xfd,0x00,0x3e]<br>
+[0x94,0xfd,0x00,0x3e]<br>
+<br>
+# CHECK: vldrw.u32 q1, [q2, #-0] @ encoding: [0x14,0xfd,0x00,0x3e]<br>
+[0x14,0xfd,0x00,0x3e]<br>
+<br>
+# CHECK: vldrd.u64 q1, [q2] @ encoding: [0x94,0xfd,0x00,0x3f]<br>
+[0x94,0xfd,0x00,0x3f]<br>
+<br>
+# CHECK: vldrd.u64 q1, [q2, #-0] @ encoding: [0x14,0xfd,0x00,0x3f]<br>
+[0x14,0xfd,0x00,0x3f]<br>
+<br>
+# CHECK: vstrb.8 q1, [r2] @ encoding: [0x82,0xed,0x00,0x3e]<br>
+[0x82,0xed,0x00,0x3e]<br>
+<br>
+# CHECK: vstrb.8 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x3e]<br>
+[0x02,0xed,0x00,0x3e]<br>
+<br>
+# CHECK: vstrb.16 q1, [r2] @ encoding: [0x82,0xed,0x80,0x2e]<br>
+[0x82,0xed,0x80,0x2e]<br>
+<br>
+# CHECK: vstrb.16 q1, [r2, #-0] @ encoding: [0x02,0xed,0x80,0x2e]<br>
+[0x02,0xed,0x80,0x2e]<br>
+<br>
+# CHECK: vstrb.32 q1, [r2] @ encoding: [0x82,0xed,0x00,0x2f]<br>
+[0x82,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vstrb.32 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x2f]<br>
+[0x02,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vstrh.16 q1, [r2] @ encoding: [0x82,0xed,0x80,0x3e]<br>
+[0x82,0xed,0x80,0x3e]<br>
+<br>
+# CHECK: vstrh.16 q1, [r2, #-0] @ encoding: [0x02,0xed,0x80,0x3e]<br>
+[0x02,0xed,0x80,0x3e]<br>
+<br>
+# CHECK: vstrh.32 q1, [r2] @ encoding: [0x8a,0xed,0x00,0x2f]<br>
+[0x8a,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vstrh.32 q1, [r2, #-0] @ encoding: [0x0a,0xed,0x00,0x2f]<br>
+[0x0a,0xed,0x00,0x2f]<br>
+<br>
+# CHECK: vstrw.32 q1, [r2] @ encoding: [0x82,0xed,0x00,0x3f]<br>
+[0x82,0xed,0x00,0x3f]<br>
+<br>
+# CHECK: vstrw.32 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x3f]<br>
+[0x02,0xed,0x00,0x3f]<br>
+<br>
+# CHECK: vstrw.32 q1, [q2] @ encoding: [0x84,0xfd,0x00,0x3e]<br>
+[0x84,0xfd,0x00,0x3e]<br>
+<br>
+# CHECK: vstrw.32 q1, [q2, #-0] @ encoding: [0x04,0xfd,0x00,0x3e]<br>
+[0x04,0xfd,0x00,0x3e]<br>
+<br>
+# CHECK: vstrd.64 q1, [q2] @ encoding: [0x84,0xfd,0x00,0x3f]<br>
+[0x84,0xfd,0x00,0x3f]<br>
+<br>
+# CHECK: vstrd.64 q1, [q2, #-0] @ encoding: [0x04,0xfd,0x00,0x3f]<br>
+[0x04,0xfd,0x00,0x3f]<br>
+<br>
<br>
Propchange: llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt<br>
------------------------------------------------------------------------------<br>
svn:eol-style = native<br>
<br>
Propchange: llvm/trunk/test/MC/Disassembler/ARM/mve-load-store.txt<br>
------------------------------------------------------------------------------<br>
svn:keywords = Rev Date Author URL Id<br>
<br>
<br>
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</blockquote></div>