<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Thanks for letting me know, I'll look into it. I'm not sure why I didn't get any emails from the bots. <br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Jun 18, 2019, at 15:19, Jordan Rupprecht <<a href="mailto:rupprecht@google.com" class="">rupprecht@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hi Daniel,<div class=""><br class=""><div class="">Looks like this broke a lot of buildbots. I reverted in r363747 to keep things green. See <a href="http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/203/steps/build%20stage%201/logs/stdio" class="">http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/203/steps/build%20stage%201/logs/stdio</a> for an example.</div></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Jun 18, 2019 at 2:52 PM Daniel Sanders via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: dsanders<br class="">
Date: Tue Jun 18 14:56:04 2019<br class="">
New Revision: 363744<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=363744&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=363744&view=rev</a><br class="">
Log:<br class="">
[tblgen][disasm] Allow multiple encodings to disassemble to the same instruction<br class="">
<br class="">
Summary:<br class="">
Add an AdditionalEncoding class which can be used to define additional encodings<br class="">
for a given instruction. This causes the disassembler to add an additional<br class="">
encoding to its matching tables that map to the specified instruction.<br class="">
<br class="">
Usage:<br class="">
def ADD1 : Instruction {<br class="">
bits<8> Reg;<br class="">
bits<32> Inst;<br class="">
<br class="">
let Size = 4;<br class="">
let Inst{0-7} = Reg;<br class="">
let Inst{8-14} = 0;<br class="">
let Inst{15} = 1; // Continuation bit<br class="">
let Inst{16-31} = 0;<br class="">
...<br class="">
}<br class="">
def : AdditionalEncoding<ADD1> {<br class="">
bits<8> Reg;<br class="">
bits<16> Inst; // You can also have bits<32> and it will still be a 16-bit encoding<br class="">
let Size = 2;<br class="">
let Inst{0-3} = 0;<br class="">
let Inst{4-7} = Reg;<br class="">
let Inst{8-15} = 0;<br class="">
...<br class="">
}<br class="">
with those definitions, llvm-mc will successfully disassemble both of these:<br class="">
0x01 0x00<br class="">
0x10 0x80 0x00 0x00<br class="">
to:<br class="">
ADD1 r1<br class="">
<br class="">
Depends on D52366<br class="">
<br class="">
Reviewers: bogner, charukcs<br class="">
<br class="">
Reviewed By: bogner<br class="">
<br class="">
Subscribers: nlguillemot, nhaehnle, llvm-commits<br class="">
<br class="">
Tags: #llvm<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D52369" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/D52369</a><br class="">
<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/Target/Target.td<br class="">
llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/Target/Target.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=363744&r1=363743&r2=363744&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=363744&r1=363743&r2=363744&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/Target/Target.td (original)<br class="">
+++ llvm/trunk/include/llvm/Target/Target.td Tue Jun 18 14:56:04 2019<br class="">
@@ -398,11 +398,49 @@ include "llvm/Target/TargetSchedule.td"<br class="">
<br class="">
class Predicate; // Forward def<br class="">
<br class="">
+class InstructionEncoding {<br class="">
+ // Size of encoded instruction.<br class="">
+ int Size;<br class="">
+<br class="">
+ // The "namespace" in which this instruction exists, on targets like ARM<br class="">
+ // which multiple ISA namespaces exist.<br class="">
+ string DecoderNamespace = "";<br class="">
+<br class="">
+ // List of predicates which will be turned into isel matching code.<br class="">
+ list<Predicate> Predicates = [];<br class="">
+<br class="">
+ string DecoderMethod = "";<br class="">
+<br class="">
+ // Is the instruction decoder method able to completely determine if the<br class="">
+ // given instruction is valid or not. If the TableGen definition of the<br class="">
+ // instruction specifies bitpattern A??B where A and B are static bits, the<br class="">
+ // hasCompleteDecoder flag says whether the decoder method fully handles the<br class="">
+ // ?? space, i.e. if it is a final arbiter for the instruction validity.<br class="">
+ // If not then the decoder attempts to continue decoding when the decoder<br class="">
+ // method fails.<br class="">
+ //<br class="">
+ // This allows to handle situations where the encoding is not fully<br class="">
+ // orthogonal. Example:<br class="">
+ // * InstA with bitpattern 0b0000????,<br class="">
+ // * InstB with bitpattern 0b000000?? but the associated decoder method<br class="">
+ // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.<br class="">
+ //<br class="">
+ // The decoder tries to decode a bitpattern that matches both InstA and<br class="">
+ // InstB bitpatterns first as InstB (because it is the most specific<br class="">
+ // encoding). In the default case (hasCompleteDecoder = 1), when<br class="">
+ // DecodeInstB() returns Fail the bitpattern gets rejected. By setting<br class="">
+ // hasCompleteDecoder = 0 in InstB, the decoder is informed that<br class="">
+ // DecodeInstB() is not able to determine if all possible values of ?? are<br class="">
+ // valid or not. If DecodeInstB() returns Fail the decoder will attempt to<br class="">
+ // decode the bitpattern as InstA too.<br class="">
+ bit hasCompleteDecoder = 1;<br class="">
+}<br class="">
+<br class="">
//===----------------------------------------------------------------------===//<br class="">
// Instruction set description - These classes correspond to the C++ classes in<br class="">
// the Target/TargetInstrInfo.h file.<br class="">
//<br class="">
-class Instruction {<br class="">
+class Instruction : InstructionEncoding {<br class="">
string Namespace = "";<br class="">
<br class="">
dag OutOperandList; // An dag containing the MI def operand list.<br class="">
@@ -427,10 +465,6 @@ class Instruction {<br class="">
// from the opcode.<br class="">
int Size = 0;<br class="">
<br class="">
- // DecoderNamespace - The "namespace" in which this instruction exists, on<br class="">
- // targets like ARM which multiple ISA namespaces exist.<br class="">
- string DecoderNamespace = "";<br class="">
-<br class="">
// Code size, for instruction selection.<br class="">
// FIXME: What does this actually mean?<br class="">
int CodeSize = 0;<br class="">
@@ -532,31 +566,6 @@ class Instruction {<br class="">
string DisableEncoding = "";<br class="">
<br class="">
string PostEncoderMethod = "";<br class="">
- string DecoderMethod = "";<br class="">
-<br class="">
- // Is the instruction decoder method able to completely determine if the<br class="">
- // given instruction is valid or not. If the TableGen definition of the<br class="">
- // instruction specifies bitpattern A??B where A and B are static bits, the<br class="">
- // hasCompleteDecoder flag says whether the decoder method fully handles the<br class="">
- // ?? space, i.e. if it is a final arbiter for the instruction validity.<br class="">
- // If not then the decoder attempts to continue decoding when the decoder<br class="">
- // method fails.<br class="">
- //<br class="">
- // This allows to handle situations where the encoding is not fully<br class="">
- // orthogonal. Example:<br class="">
- // * InstA with bitpattern 0b0000????,<br class="">
- // * InstB with bitpattern 0b000000?? but the associated decoder method<br class="">
- // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.<br class="">
- //<br class="">
- // The decoder tries to decode a bitpattern that matches both InstA and<br class="">
- // InstB bitpatterns first as InstB (because it is the most specific<br class="">
- // encoding). In the default case (hasCompleteDecoder = 1), when<br class="">
- // DecodeInstB() returns Fail the bitpattern gets rejected. By setting<br class="">
- // hasCompleteDecoder = 0 in InstB, the decoder is informed that<br class="">
- // DecodeInstB() is not able to determine if all possible values of ?? are<br class="">
- // valid or not. If DecodeInstB() returns Fail the decoder will attempt to<br class="">
- // decode the bitpattern as InstA too.<br class="">
- bit hasCompleteDecoder = 1;<br class="">
<br class="">
/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.<br class="">
bits<64> TSFlags = 0;<br class="">
@@ -593,6 +602,13 @@ class Instruction {<br class="">
bit FastISelShouldIgnore = 0;<br class="">
}<br class="">
<br class="">
+/// Defines an additional encoding that disassembles to the given instruction<br class="">
+/// Like Instruction, the Inst and SoftFail fields are omitted to allow targets<br class="">
+// to specify their size.<br class="">
+class AdditionalEncoding<Instruction I> : InstructionEncoding {<br class="">
+ Instruction AliasOf = I;<br class="">
+}<br class="">
+<br class="">
/// PseudoInstExpansion - Expansion information for a pseudo-instruction.<br class="">
/// Which instruction it expands to and how the operands map from the<br class="">
/// pseudo.<br class="">
<br class="">
Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=363744&r1=363743&r2=363744&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=363744&r1=363743&r2=363744&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)<br class="">
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Tue Jun 18 14:56:04 2019<br class="">
@@ -16,9 +16,10 @@<br class="">
#include "llvm/ADT/APInt.h"<br class="">
#include "llvm/ADT/ArrayRef.h"<br class="">
#include "llvm/ADT/CachedHashString.h"<br class="">
-#include "llvm/ADT/SmallString.h"<br class="">
-#include "llvm/ADT/SetVector.h"<br class="">
#include "llvm/ADT/STLExtras.h"<br class="">
+#include "llvm/ADT/SetVector.h"<br class="">
+#include "llvm/ADT/SmallString.h"<br class="">
+#include "llvm/ADT/Statistic.h"<br class="">
#include "llvm/ADT/StringExtras.h"<br class="">
#include "llvm/ADT/StringRef.h"<br class="">
#include "llvm/MC/MCFixedLenDisassembler.h"<br class="">
@@ -47,6 +48,12 @@ using namespace llvm;<br class="">
<br class="">
namespace {<br class="">
<br class="">
+STATISTIC(NumEncodings, "Number of encodings considered");<br class="">
+STATISTIC(NumEncodingsLackingDisasm, "Number of encodings without disassembler info");<br class="">
+STATISTIC(NumInstructions, "Number of instructions considered");<br class="">
+STATISTIC(NumEncodingsSupported, "Number of encodings supported");<br class="">
+STATISTIC(NumEncodingsOmitted, "Number of encodings omitted");<br class="">
+<br class="">
struct EncodingField {<br class="">
unsigned Base, Width, Offset;<br class="">
EncodingField(unsigned B, unsigned W, unsigned O)<br class="">
@@ -94,6 +101,15 @@ struct EncodingAndInst {<br class="">
: EncodingDef(EncodingDef), Inst(Inst) {}<br class="">
};<br class="">
<br class="">
+struct EncodingIDAndOpcode {<br class="">
+ unsigned EncodingID;<br class="">
+ unsigned Opcode;<br class="">
+<br class="">
+ EncodingIDAndOpcode() : EncodingID(0), Opcode(0) {}<br class="">
+ EncodingIDAndOpcode(unsigned EncodingID, unsigned Opcode)<br class="">
+ : EncodingID(EncodingID), Opcode(Opcode) {}<br class="">
+};<br class="">
+<br class="">
raw_ostream &operator<<(raw_ostream &OS, const EncodingAndInst &Value) {<br class="">
if (Value.EncodingDef != Value.Inst->TheDef)<br class="">
OS << Value.EncodingDef->getName() << ":";<br class="">
@@ -102,6 +118,7 @@ raw_ostream &operator<<(raw_ostream &OS,<br class="">
}<br class="">
<br class="">
class FixedLenDecoderEmitter {<br class="">
+ RecordKeeper &RK;<br class="">
std::vector<EncodingAndInst> NumberedEncodings;<br class="">
<br class="">
public:<br class="">
@@ -113,7 +130,7 @@ public:<br class="">
std::string ROK = "MCDisassembler::Success",<br class="">
std::string RFail = "MCDisassembler::Fail",<br class="">
std::string L = "")<br class="">
- : Target(R), PredicateNamespace(std::move(PredicateNamespace)),<br class="">
+ : RK(R), Target(R), PredicateNamespace(std::move(PredicateNamespace)),<br class="">
GuardPrefix(std::move(GPrefix)), GuardPostfix(std::move(GPostfix)),<br class="">
ReturnOK(std::move(ROK)), ReturnFail(std::move(RFail)),<br class="">
Locals(std::move(L)) {}<br class="">
@@ -251,10 +268,11 @@ protected:<br class="">
bool Mixed; // a mixed region contains both set and unset bits<br class="">
<br class="">
// Map of well-known segment value to the set of uid's with that value.<br class="">
- std::map<uint64_t, std::vector<unsigned>> FilteredInstructions;<br class="">
+ std::map<uint64_t, std::vector<EncodingIDAndOpcode>><br class="">
+ FilteredInstructions;<br class="">
<br class="">
// Set of uid's with non-constant segment values.<br class="">
- std::vector<unsigned> VariableInstructions;<br class="">
+ std::vector<EncodingIDAndOpcode> VariableInstructions;<br class="">
<br class="">
// Map of well-known segment value to its delegate.<br class="">
std::map<unsigned, std::unique_ptr<const FilterChooser>> FilterChooserMap;<br class="">
@@ -263,7 +281,7 @@ protected:<br class="">
unsigned NumFiltered;<br class="">
<br class="">
// Keeps track of the last opcode in the filtered bucket.<br class="">
- unsigned LastOpcFiltered;<br class="">
+ EncodingIDAndOpcode LastOpcFiltered;<br class="">
<br class="">
public:<br class="">
Filter(Filter &&f);<br class="">
@@ -273,7 +291,7 @@ public:<br class="">
<br class="">
unsigned getNumFiltered() const { return NumFiltered; }<br class="">
<br class="">
- unsigned getSingletonOpc() const {<br class="">
+ EncodingIDAndOpcode getSingletonOpc() const {<br class="">
assert(NumFiltered == 1);<br class="">
return LastOpcFiltered;<br class="">
}<br class="">
@@ -337,10 +355,12 @@ protected:<br class="">
friend class Filter;<br class="">
<br class="">
// Vector of codegen instructions to choose our filter.<br class="">
- ArrayRef<EncodingAndInst> AllInstructions;<br class="">
+ ArrayRef<const EncodingAndInst> AllInstructions;<br class="">
<br class="">
// Vector of uid's for this filter chooser to work on.<br class="">
- const std::vector<unsigned> &Opcodes;<br class="">
+ // The first member of the pair is the opcode id being decoded, the second is<br class="">
+ // the opcode id that should be emitted.<br class="">
+ const std::vector<EncodingIDAndOpcode> &Opcodes;<br class="">
<br class="">
// Lookup table for the operand decoding of instructions.<br class="">
const std::map<unsigned, std::vector<OperandInfo>> &Operands;<br class="">
@@ -365,8 +385,8 @@ protected:<br class="">
const FixedLenDecoderEmitter *Emitter;<br class="">
<br class="">
public:<br class="">
- FilterChooser(ArrayRef<EncodingAndInst> Insts,<br class="">
- const std::vector<unsigned> &IDs,<br class="">
+ FilterChooser(ArrayRef<const EncodingAndInst> Insts,<br class="">
+ const std::vector<EncodingIDAndOpcode> &IDs,<br class="">
const std::map<unsigned, std::vector<OperandInfo>> &Ops,<br class="">
unsigned BW, const FixedLenDecoderEmitter *E)<br class="">
: AllInstructions(Insts), Opcodes(IDs), Operands(Ops),<br class="">
@@ -375,8 +395,8 @@ public:<br class="">
doFilter();<br class="">
}<br class="">
<br class="">
- FilterChooser(ArrayRef<EncodingAndInst> Insts,<br class="">
- const std::vector<unsigned> &IDs,<br class="">
+ FilterChooser(ArrayRef<const EncodingAndInst> Insts,<br class="">
+ const std::vector<EncodingIDAndOpcode> &IDs,<br class="">
const std::map<unsigned, std::vector<OperandInfo>> &Ops,<br class="">
const std::vector<bit_value_t> &ParentFilterBitValues,<br class="">
const FilterChooser &parent)<br class="">
@@ -412,6 +432,15 @@ protected:<br class="">
}<br class="">
}<br class="">
<br class="">
+ // Emit the name of the encoding/instruction pair.<br class="">
+ void emitNameWithID(raw_ostream &OS, unsigned Opcode) const {<br class="">
+ const Record *EncodingDef = AllInstructions[Opcode].EncodingDef;<br class="">
+ const Record *InstDef = AllInstructions[Opcode].Inst->TheDef;<br class="">
+ if (EncodingDef != InstDef)<br class="">
+ OS << EncodingDef->getName() << ":";<br class="">
+ OS << InstDef->getName();<br class="">
+ }<br class="">
+<br class="">
// Populates the field of the insn given the start position and the number of<br class="">
// consecutive bits to scan for.<br class="">
//<br class="">
@@ -462,7 +491,7 @@ protected:<br class="">
<br class="">
// Emits table entries to decode the singleton.<br class="">
void emitSingletonTableEntry(DecoderTableInfo &TableInfo,<br class="">
- unsigned Opc) const;<br class="">
+ EncodingIDAndOpcode Opc) const;<br class="">
<br class="">
// Emits code to decode the singleton, and then to decode the rest.<br class="">
void emitSingletonTableEntry(DecoderTableInfo &TableInfo,<br class="">
@@ -523,13 +552,13 @@ Filter::Filter(FilterChooser &owner, uns<br class="">
assert(StartBit + NumBits - 1 < Owner->BitWidth);<br class="">
<br class="">
NumFiltered = 0;<br class="">
- LastOpcFiltered = 0;<br class="">
+ LastOpcFiltered = {0, 0};<br class="">
<br class="">
for (unsigned i = 0, e = Owner->Opcodes.size(); i != e; ++i) {<br class="">
insn_t Insn;<br class="">
<br class="">
// Populates the insn given the uid.<br class="">
- Owner->insnWithID(Insn, Owner->Opcodes[i]);<br class="">
+ Owner->insnWithID(Insn, Owner->Opcodes[i].EncodingID);<br class="">
<br class="">
uint64_t Field;<br class="">
// Scans the segment for possibly well-specified encoding bits.<br class="">
@@ -1025,7 +1054,7 @@ unsigned FilterChooser::getIslands(std::<br class="">
// 1: Water (the bit value does not affect decoding)<br class="">
// 2: Island (well-known bit value needed for decoding)<br class="">
int State = 0;<br class="">
- int Val = -1;<br class="">
+ int64_t Val = -1;<br class="">
<br class="">
for (unsigned i = 0; i < BitWidth; ++i) {<br class="">
Val = Value(Insn[i]);<br class="">
@@ -1313,12 +1342,12 @@ void FilterChooser::emitSoftFailTableEnt<br class="">
<br class="">
// Emits table entries to decode the singleton.<br class="">
void FilterChooser::emitSingletonTableEntry(DecoderTableInfo &TableInfo,<br class="">
- unsigned Opc) const {<br class="">
+ EncodingIDAndOpcode Opc) const {<br class="">
std::vector<unsigned> StartBits;<br class="">
std::vector<unsigned> EndBits;<br class="">
std::vector<uint64_t> FieldVals;<br class="">
insn_t Insn;<br class="">
- insnWithID(Insn, Opc);<br class="">
+ insnWithID(Insn, Opc.EncodingID);<br class="">
<br class="">
// Look for islands of undecoded bits of the singleton.<br class="">
getIslands(StartBits, EndBits, FieldVals, Insn);<br class="">
@@ -1326,7 +1355,7 @@ void FilterChooser::emitSingletonTableEn<br class="">
unsigned Size = StartBits.size();<br class="">
<br class="">
// Emit the predicate table entry if one is needed.<br class="">
- emitPredicateTableEntry(TableInfo, Opc);<br class="">
+ emitPredicateTableEntry(TableInfo, Opc.EncodingID);<br class="">
<br class="">
// Check any additional encoding fields needed.<br class="">
for (unsigned I = Size; I != 0; --I) {<br class="">
@@ -1350,10 +1379,11 @@ void FilterChooser::emitSingletonTableEn<br class="">
}<br class="">
<br class="">
// Check for soft failure of the match.<br class="">
- emitSoftFailTableEntry(TableInfo, Opc);<br class="">
+ emitSoftFailTableEntry(TableInfo, Opc.EncodingID);<br class="">
<br class="">
bool HasCompleteDecoder;<br class="">
- unsigned DIdx = getDecoderIndex(TableInfo.Decoders, Opc, HasCompleteDecoder);<br class="">
+ unsigned DIdx =<br class="">
+ getDecoderIndex(TableInfo.Decoders, Opc.EncodingID, HasCompleteDecoder);<br class="">
<br class="">
// Produce OPC_Decode or OPC_TryDecode opcode based on the information<br class="">
// whether the instruction decoder is complete or not. If it is complete<br class="">
@@ -1366,8 +1396,9 @@ void FilterChooser::emitSingletonTableEn<br class="">
// can decode it.<br class="">
TableInfo.Table.push_back(HasCompleteDecoder ? MCD::OPC_Decode :<br class="">
MCD::OPC_TryDecode);<br class="">
+ NumEncodingsSupported++;<br class="">
uint8_t Buffer[16], *p;<br class="">
- encodeULEB128(Opc, Buffer);<br class="">
+ encodeULEB128(Opc.Opcode, Buffer);<br class="">
for (p = Buffer; *p >= 128 ; ++p)<br class="">
TableInfo.Table.push_back(*p);<br class="">
TableInfo.Table.push_back(*p);<br class="">
@@ -1393,7 +1424,7 @@ void FilterChooser::emitSingletonTableEn<br class="">
// Emits table entries to decode the singleton, and then to decode the rest.<br class="">
void FilterChooser::emitSingletonTableEntry(DecoderTableInfo &TableInfo,<br class="">
const Filter &Best) const {<br class="">
- unsigned Opc = Best.getSingletonOpc();<br class="">
+ EncodingIDAndOpcode Opc = Best.getSingletonOpc();<br class="">
<br class="">
// complex singletons need predicate checks from the first singleton<br class="">
// to refer forward to the variable filterchooser that follows.<br class="">
@@ -1453,7 +1484,7 @@ bool FilterChooser::filterProcessor(bool<br class="">
std::vector<uint64_t> FieldVals;<br class="">
insn_t Insn;<br class="">
<br class="">
- insnWithID(Insn, Opcodes[i]);<br class="">
+ insnWithID(Insn, Opcodes[i].EncodingID);<br class="">
<br class="">
// Look for islands of undecoded bits of any instruction.<br class="">
if (getIslands(StartBits, EndBits, FieldVals, Insn) > 0) {<br class="">
@@ -1497,7 +1528,7 @@ bool FilterChooser::filterProcessor(bool<br class="">
for (unsigned InsnIndex = 0; InsnIndex < numInstructions; ++InsnIndex) {<br class="">
insn_t insn;<br class="">
<br class="">
- insnWithID(insn, Opcodes[InsnIndex]);<br class="">
+ insnWithID(insn, Opcodes[InsnIndex].EncodingID);<br class="">
<br class="">
for (BitIndex = 0; BitIndex < BitWidth; ++BitIndex) {<br class="">
switch (bitAttrs[BitIndex]) {<br class="">
@@ -1716,9 +1747,12 @@ void FilterChooser::emitTableEntries(Dec<br class="">
dumpStack(errs(), "\t\t");<br class="">
<br class="">
for (unsigned i = 0; i < Opcodes.size(); ++i) {<br class="">
- errs() << '\t' << AllInstructions[Opcodes[i]] << " ";<br class="">
- dumpBits(errs(),<br class="">
- getBitsField(*AllInstructions[Opcodes[i]].EncodingDef, "Inst"));<br class="">
+ errs() << '\t';<br class="">
+ emitNameWithID(errs(), Opcodes[i].EncodingID);<br class="">
+ errs() << " ";<br class="">
+ dumpBits(<br class="">
+ errs(),<br class="">
+ getBitsField(*AllInstructions[Opcodes[i].EncodingID].EncodingDef, "Inst"));<br class="">
errs() << '\n';<br class="">
}<br class="">
}<br class="">
@@ -1750,24 +1784,25 @@ static std::string findOperandDecoderMet<br class="">
return Decoder;<br class="">
}<br class="">
<br class="">
-static bool populateInstruction(CodeGenTarget &Target,<br class="">
- const CodeGenInstruction &CGI, unsigned Opc,<br class="">
- std::map<unsigned, std::vector<OperandInfo>> &Operands){<br class="">
+static bool<br class="">
+populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,<br class="">
+ const CodeGenInstruction &CGI, unsigned Opc,<br class="">
+ std::map<unsigned, std::vector<OperandInfo>> &Operands) {<br class="">
const Record &Def = *CGI.TheDef;<br class="">
// If all the bit positions are not specified; do not decode this instruction.<br class="">
// We are bound to fail! For proper disassembly, the well-known encoding bits<br class="">
// of the instruction must be fully specified.<br class="">
<br class="">
- BitsInit &Bits = getBitsField(Def, "Inst");<br class="">
+ BitsInit &Bits = getBitsField(EncodingDef, "Inst");<br class="">
if (Bits.allInComplete()) return false;<br class="">
<br class="">
std::vector<OperandInfo> InsnOperands;<br class="">
<br class="">
// If the instruction has specified a custom decoding hook, use that instead<br class="">
// of trying to auto-generate the decoder.<br class="">
- StringRef InstDecoder = Def.getValueAsString("DecoderMethod");<br class="">
+ StringRef InstDecoder = EncodingDef.getValueAsString("DecoderMethod");<br class="">
if (InstDecoder != "") {<br class="">
- bool HasCompleteInstDecoder = Def.getValueAsBit("hasCompleteDecoder");<br class="">
+ bool HasCompleteInstDecoder = EncodingDef.getValueAsBit("hasCompleteDecoder");<br class="">
InsnOperands.push_back(OperandInfo(InstDecoder, HasCompleteInstDecoder));<br class="">
Operands[Opc] = InsnOperands;<br class="">
return true;<br class="">
@@ -2143,7 +2178,7 @@ static void emitDecodeInstruction(format<br class="">
<< " const FeatureBitset& Bits = STI.getFeatureBits();\n"<br class="">
<< "\n"<br class="">
<< " const uint8_t *Ptr = DecodeTable;\n"<br class="">
- << " uint32_t CurFieldValue = 0;\n"<br class="">
+ << " InsnType CurFieldValue = 0;\n"<br class="">
<< " DecodeStatus S = MCDisassembler::Success;\n"<br class="">
<< " while (true) {\n"<br class="">
<< " ptrdiff_t Loc = Ptr - DecodeTable;\n"<br class="">
@@ -2188,7 +2223,7 @@ static void emitDecodeInstruction(format<br class="">
<< " unsigned Len = *++Ptr;\n"<br class="">
<< " InsnType FieldValue = fieldFromInstruction(insn, Start, Len);\n"<br class="">
<< " // Decode the field value.\n"<br class="">
- << " uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);\n"<br class="">
+ << " InsnType ExpectedValue = decodeULEB128(++Ptr, &Len);\n"<br class="">
<< " Ptr += Len;\n"<br class="">
<< " // NumToSkip is a plain 24-bit integer.\n"<br class="">
<< " unsigned NumToSkip = *Ptr++;\n"<br class="">
@@ -2335,37 +2370,52 @@ void FixedLenDecoderEmitter::run(raw_ost<br class="">
// Parameterize the decoders based on namespace and instruction width.<br class="">
const auto &NumberedInstructions = Target.getInstructionsByEnumValue();<br class="">
NumberedEncodings.reserve(NumberedInstructions.size());<br class="">
- for (const auto &NumberedInstruction : NumberedInstructions)<br class="">
+ DenseMap<Record *, unsigned> IndexOfInstruction;<br class="">
+ for (const auto &NumberedInstruction : NumberedInstructions) {<br class="">
+ IndexOfInstruction[NumberedInstruction->TheDef] = NumberedEncodings.size();<br class="">
NumberedEncodings.emplace_back(NumberedInstruction->TheDef, NumberedInstruction);<br class="">
+ }<br class="">
+ for (const auto &NumberedAlias : RK.getAllDerivedDefinitions("AdditionalEncoding"))<br class="">
+ NumberedEncodings.emplace_back(<br class="">
+ NumberedAlias,<br class="">
+ &Target.getInstruction(NumberedAlias->getValueAsDef("AliasOf")));<br class="">
<br class="">
- std::map<std::pair<std::string, unsigned>,<br class="">
- std::vector<unsigned>> OpcMap;<br class="">
+ std::map<std::pair<std::string, unsigned>, std::vector<EncodingIDAndOpcode>><br class="">
+ OpcMap;<br class="">
std::map<unsigned, std::vector<OperandInfo>> Operands;<br class="">
<br class="">
for (unsigned i = 0; i < NumberedEncodings.size(); ++i) {<br class="">
+ const Record *EncodingDef = NumberedEncodings[i].EncodingDef;<br class="">
const CodeGenInstruction *Inst = NumberedEncodings[i].Inst;<br class="">
const Record *Def = Inst->TheDef;<br class="">
- unsigned Size = Def->getValueAsInt("Size");<br class="">
+ unsigned Size = EncodingDef->getValueAsInt("Size");<br class="">
if (Def->getValueAsString("Namespace") == "TargetOpcode" ||<br class="">
Def->getValueAsBit("isPseudo") ||<br class="">
Def->getValueAsBit("isAsmParserOnly") ||<br class="">
- Def->getValueAsBit("isCodeGenOnly"))<br class="">
+ Def->getValueAsBit("isCodeGenOnly")) {<br class="">
+ NumEncodingsLackingDisasm++;<br class="">
continue;<br class="">
+ }<br class="">
+<br class="">
+ if (i < NumberedInstructions.size())<br class="">
+ NumInstructions++;<br class="">
+ NumEncodings++;<br class="">
<br class="">
- StringRef DecoderNamespace = Def->getValueAsString("DecoderNamespace");<br class="">
+ StringRef DecoderNamespace = EncodingDef->getValueAsString("DecoderNamespace");<br class="">
<br class="">
if (Size) {<br class="">
- if (populateInstruction(Target, *Inst, i, Operands)) {<br class="">
- OpcMap[std::make_pair(DecoderNamespace, Size)].push_back(i);<br class="">
- }<br class="">
+ if (populateInstruction(Target, *EncodingDef, *Inst, i, Operands)) {<br class="">
+ OpcMap[std::make_pair(DecoderNamespace, Size)].emplace_back(i, IndexOfInstruction.find(Def)->second);<br class="">
+ } else<br class="">
+ NumEncodingsOmitted++;<br class="">
}<br class="">
}<br class="">
<br class="">
DecoderTableInfo TableInfo;<br class="">
for (const auto &Opc : OpcMap) {<br class="">
// Emit the decoder for this namespace+width combination.<br class="">
- ArrayRef<EncodingAndInst> NumberedEncodingsRef(NumberedEncodings.data(),<br class="">
- NumberedEncodings.size());<br class="">
+ ArrayRef<const EncodingAndInst> NumberedEncodingsRef(<br class="">
+ NumberedEncodings.data(), NumberedEncodings.size());<br class="">
FilterChooser FC(NumberedEncodingsRef, Opc.second, Operands,<br class="">
8 * Opc.first.second, this);<br class="">
<br class="">
<br class="">
<br class="">
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