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<div>r363416 adds a use of it, until the rest is approved.</div>
<div>That said, everything is approved except for a single line change in the <a href="https://reviews.llvm.org/D63205">
https://reviews.llvm.org/D63205</a></div>
<div><br>
</div>
<div><span>
<pre>-- <br></pre>
<div style="width: 71ch;">Stas</div>
</span></div>
<div><br>
</div>
<div>-----Original Message-----</div>
<div><b>From</b>: Mikael Holmén <<a href="mailto:Mikael%20%3d%3fISO-8859-1%3fQ%3fHolm%3dE9n%3f%3d%20%3cmikael.holmen@ericsson.com%3e">mikael.holmen@ericsson.com</a>></div>
<div><b>To</b>: "Mekhanoshin, Stanislav" <<a href="mailto:%22Mekhanoshin,%20Stanislav%22%20%3cStanislav.Mekhanoshin@amd.com%3e">Stanislav.Mekhanoshin@amd.com</a>>, llvm-commits@lists.llvm.org <<a href="mailto:%22llvm-commits@lists.llvm.org%22%20%3cllvm-commits@lists.llvm.org%3e">llvm-commits@lists.llvm.org</a>></div>
<div><b>Subject</b>: Re: [llvm] r363299 - [AMDGPU] gfx1010 base changes for wave32</div>
<div><b>Date</b>: Fri, 14 Jun 2019 06:34:32 +0000</div>
<div><br>
</div>
<pre>[CAUTION: External Email]</pre>
<pre><br></pre>
<pre>Hi,</pre>
<pre><br></pre>
<pre>Ok, so they're about to be used then.</pre>
<pre><br></pre>
<pre>Then I'll ignore this and hope for those patches to be submitted soon. :)</pre>
<pre><br></pre>
<pre>Thanks,</pre>
<pre>Mikael</pre>
<pre><br></pre>
<pre>On 2019-06-14 08:29, Mekhanoshin, Stanislav wrote:</pre>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<pre>Sorry about that. It has to be used here: </pre>
<a href="https://reviews.llvm.org/D63204">
<pre>https://reviews.llvm.org/D63204</pre>
</a>
<pre><br></pre>
<pre>Which in turn waits for this: </pre>
<a href="https://reviews.llvm.org/D63205">
<pre>https://reviews.llvm.org/D63205</pre>
</a>
<pre><br></pre>
<pre><br></pre>
<pre>I really apologize, this is a long stack of dependencies in the chain. I have missed the warning as clang doesn't issue one.</pre>
<pre><br></pre>
<pre>Stas</pre>
<pre>--- Original message ---</pre>
<pre>From: Mikael Holmén </pre>
<a href="mailto:mikael.holmen@ericsson.com">
<pre>mikael.holmen@ericsson.com</pre>
</a>
<pre><br></pre>
<pre>Sent: June 13, 2019 23:13:12</pre>
<pre>To: Mekhanoshin, Stanislav </pre>
<a href="mailto:Stanislav.Mekhanoshin@amd.com">
<pre>Stanislav.Mekhanoshin@amd.com</pre>
</a>
<pre>, </pre>
<a href="mailto:llvm-commits@lists.llvm.org">
<pre>llvm-commits@lists.llvm.org</pre>
</a>
<pre><br></pre>
<pre>Subject: Re: [llvm] r363299 - [AMDGPU] gfx1010 base changes for wave32</pre>
<pre><br></pre>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<pre>[CAUTION: External Email]</pre>
<pre><br></pre>
<pre>Hi,</pre>
<pre><br></pre>
<pre>gcc (7.4) warns on unused functions with this patch:</pre>
<pre><br></pre>
<pre>../lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:5417:1: error:</pre>
<pre>'llvm::OperandMatchResultTy</pre>
<pre>{anonymous}::AMDGPUAsmParser::parseBoolReg(llvm::OperandVector&)'</pre>
<pre>defined but not used [-Werror=unused-function]</pre>
<pre> AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {</pre>
<pre> ^~~~~~~~~~~~~~~</pre>
<pre>../lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1493:6: error: 'bool</pre>
<pre>{anonymous}::AMDGPUOperand::isBoolReg() const' defined but not used</pre>
<pre>[-Werror=unused-function]</pre>
<pre> bool AMDGPUOperand::isBoolReg() const {</pre>
<pre> ^~~~~~~~~~~~~</pre>
<pre><br></pre>
<pre>Are you about to use parseBoolReg(OperandVector &Operands) and</pre>
<pre>isBoolReg() in upcomming patches or can they be removed so we get a</pre>
<pre>warning free build also with gcc?</pre>
<pre><br></pre>
<pre>Regards,</pre>
<pre>Mikael</pre>
<pre><br></pre>
<pre>On 2019-06-13 21:18, Stanislav Mekhanoshin via llvm-commits wrote:</pre>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<pre>Author: rampitec</pre>
<pre>Date: Thu Jun 13 12:18:29 2019</pre>
<pre>New Revision: 363299</pre>
<pre><br></pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project?rev=363299&view=rev">
<pre>http://llvm.org/viewvc/llvm-project?rev=363299&view=rev</pre>
</a>
<pre><br></pre>
<pre>Log:</pre>
<pre>[AMDGPU] gfx1010 base changes for wave32</pre>
<pre><br></pre>
<pre>Differential Revision: </pre>
<a href="https://reviews.llvm.org/D63293">
<pre>https://reviews.llvm.org/D63293</pre>
</a>
<pre><br></pre>
<pre><br></pre>
<pre>Modified:</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/SIInstructions.td</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td</pre>
<pre>llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -69,9 +69,11 @@ class PredicateControl {</pre>
<pre>Predicate SubtargetPredicate = TruePredicate;</pre>
<pre>list<Predicate> AssemblerPredicates = [];</pre>
<pre>Predicate AssemblerPredicate = TruePredicate;</pre>
<pre>+ Predicate WaveSizePredicate = TruePredicate;</pre>
<pre>list<Predicate> OtherPredicates = [];</pre>
<pre>list<Predicate> Predicates = !listconcat([SubtargetPredicate,</pre>
<pre>- AssemblerPredicate],</pre>
<pre>+ AssemblerPredicate,</pre>
<pre>+ WaveSizePredicate],</pre>
<pre> AssemblerPredicates,</pre>
<pre> OtherPredicates);</pre>
<pre>}</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -94,6 +94,16 @@ GCNSubtarget::initializeSubtargetDepende</pre>
<pre><br></pre>
<pre>FullFS += "+enable-prt-strict-null,"; // This is overridden by a disable in FS</pre>
<pre><br></pre>
<pre>+ // Disable mutually exclusive bits.</pre>
<pre>+ if (FS.find_lower("+wavefrontsize") != StringRef::npos) {</pre>
<pre>+ if (FS.find_lower("wavefrontsize16") == StringRef::npos)</pre>
<pre>+ FullFS += "-wavefrontsize16,";</pre>
<pre>+ if (FS.find_lower("wavefrontsize32") == StringRef::npos)</pre>
<pre>+ FullFS += "-wavefrontsize32,";</pre>
<pre>+ if (FS.find_lower("wavefrontsize64") == StringRef::npos)</pre>
<pre>+ FullFS += "-wavefrontsize64,";</pre>
<pre>+ }</pre>
<pre>+</pre>
<pre>FullFS += FS;</pre>
<pre><br></pre>
<pre>ParseSubtargetFeatures(GPU, FullFS);</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -375,6 +375,8 @@ public:</pre>
<pre>return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+ bool isBoolReg() const;</pre>
<pre>+</pre>
<pre>bool isSCSrcF16() const {</pre>
<pre>return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);</pre>
<pre>}</pre>
<pre>@@ -616,6 +618,10 @@ public:</pre>
<pre><br></pre>
<pre>void addRegOperands(MCInst &Inst, unsigned N) const;</pre>
<pre><br></pre>
<pre>+ void addBoolRegOperands(MCInst &Inst, unsigned N) const {</pre>
<pre>+ addRegOperands(Inst, N);</pre>
<pre>+ }</pre>
<pre>+</pre>
<pre>void addRegOrImmOperands(MCInst &Inst, unsigned N) const {</pre>
<pre>if (isRegKind())</pre>
<pre>addRegOperands(Inst, N);</pre>
<pre>@@ -881,6 +887,8 @@ private:</pre>
<pre>/// \param VCCUsed [in] Whether VCC special SGPR is reserved.</pre>
<pre>/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.</pre>
<pre>/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.</pre>
<pre>+ /// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel</pre>
<pre>+ /// descriptor field, if valid.</pre>
<pre>/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.</pre>
<pre>/// \param VGPRRange [in] Token range, used for VGPR diagnostics.</pre>
<pre>/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.</pre>
<pre>@@ -889,9 +897,10 @@ private:</pre>
<pre>/// \param SGPRBlocks [out] Result SGPR block count.</pre>
<pre>bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,</pre>
<pre> bool FlatScrUsed, bool XNACKUsed,</pre>
<pre>- unsigned NextFreeVGPR, SMRange VGPRRange,</pre>
<pre>- unsigned NextFreeSGPR, SMRange SGPRRange,</pre>
<pre>- unsigned &VGPRBlocks, unsigned &SGPRBlocks);</pre>
<pre>+ Optional<bool> EnableWavefrontSize32, unsigned NextFreeVGPR,</pre>
<pre>+ SMRange VGPRRange, unsigned NextFreeSGPR,</pre>
<pre>+ SMRange SGPRRange, unsigned &VGPRBlocks,</pre>
<pre>+ unsigned &SGPRBlocks);</pre>
<pre>bool ParseDirectiveAMDGCNTarget();</pre>
<pre>bool ParseDirectiveAMDHSAKernel();</pre>
<pre>bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);</pre>
<pre>@@ -1159,6 +1168,7 @@ private:</pre>
<pre>bool validateMIMGDim(const MCInst &Inst);</pre>
<pre>bool validateLdsDirect(const MCInst &Inst);</pre>
<pre>bool validateOpSel(const MCInst &Inst);</pre>
<pre>+ bool validateVccOperand(unsigned Reg) const;</pre>
<pre>bool validateVOP3Literal(const MCInst &Inst) const;</pre>
<pre>bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);</pre>
<pre>bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;</pre>
<pre>@@ -1190,6 +1200,7 @@ public:</pre>
<pre>OperandMatchResultTy parseInterpSlot(OperandVector &Operands);</pre>
<pre>OperandMatchResultTy parseInterpAttr(OperandVector &Operands);</pre>
<pre>OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);</pre>
<pre>+ OperandMatchResultTy parseBoolReg(OperandVector &Operands);</pre>
<pre><br></pre>
<pre>bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,</pre>
<pre> const unsigned MinVal,</pre>
<pre>@@ -1479,6 +1490,11 @@ bool AMDGPUOperand::isSDWAInt32Operand()</pre>
<pre>return isSDWAOperand(MVT::i32);</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+bool AMDGPUOperand::isBoolReg() const {</pre>
<pre>+ return AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?</pre>
<pre>+ isSCSrcB64() : isSCSrcB32();</pre>
<pre>+}</pre>
<pre>+</pre>
<pre>uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const</pre>
<pre>{</pre>
<pre>assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());</pre>
<pre>@@ -3030,6 +3046,13 @@ bool AMDGPUAsmParser::validateOpSel(cons</pre>
<pre>return true;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+// Check if VCC register matches wavefront size</pre>
<pre>+bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {</pre>
<pre>+ auto FB = getFeatureBits();</pre>
<pre>+ return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) ||</pre>
<pre>+ (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);</pre>
<pre>+}</pre>
<pre>+</pre>
<pre>// VOP3 literal is only allowed in GFX10+ and only one can be used</pre>
<pre>bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const {</pre>
<pre>unsigned Opcode = Inst.getOpcode();</pre>
<pre>@@ -3267,9 +3290,9 @@ bool AMDGPUAsmParser::OutOfRangeError(SM</pre>
<pre><br></pre>
<pre>bool AMDGPUAsmParser::calculateGPRBlocks(</pre>
<pre>const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,</pre>
<pre>- bool XNACKUsed, unsigned NextFreeVGPR, SMRange VGPRRange,</pre>
<pre>- unsigned NextFreeSGPR, SMRange SGPRRange, unsigned &VGPRBlocks,</pre>
<pre>- unsigned &SGPRBlocks) {</pre>
<pre>+ bool XNACKUsed, Optional<bool> EnableWavefrontSize32, unsigned NextFreeVGPR,</pre>
<pre>+ SMRange VGPRRange, unsigned NextFreeSGPR, SMRange SGPRRange,</pre>
<pre>+ unsigned &VGPRBlocks, unsigned &SGPRBlocks) {</pre>
<pre>// TODO(scott.linder): These calculations are duplicated from</pre>
<pre>// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.</pre>
<pre>IsaVersion Version = getIsaVersion(getSTI().getCPU());</pre>
<pre>@@ -3298,7 +3321,8 @@ bool AMDGPUAsmParser::calculateGPRBlocks</pre>
<pre>NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>- VGPRBlocks = IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs);</pre>
<pre>+ VGPRBlocks =</pre>
<pre>+ IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);</pre>
<pre>SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);</pre>
<pre><br></pre>
<pre>return false;</pre>
<pre>@@ -3329,6 +3353,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDH</pre>
<pre>bool ReserveVCC = true;</pre>
<pre>bool ReserveFlatScr = true;</pre>
<pre>bool ReserveXNACK = hasXNACK();</pre>
<pre>+ Optional<bool> EnableWavefrontSize32;</pre>
<pre><br></pre>
<pre>while (true) {</pre>
<pre>while (getLexer().is(AsmToken::EndOfStatement))</pre>
<pre>@@ -3547,8 +3572,9 @@ bool AMDGPUAsmParser::ParseDirectiveAMDH</pre>
<pre>unsigned VGPRBlocks;</pre>
<pre>unsigned SGPRBlocks;</pre>
<pre>if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,</pre>
<pre>- ReserveXNACK, NextFreeVGPR, VGPRRange, NextFreeSGPR,</pre>
<pre>- SGPRRange, VGPRBlocks, SGPRBlocks))</pre>
<pre>+ ReserveXNACK, EnableWavefrontSize32, NextFreeVGPR,</pre>
<pre>+ VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,</pre>
<pre>+ SGPRBlocks))</pre>
<pre>return true;</pre>
<pre><br></pre>
<pre>if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH>(</pre>
<pre>@@ -5384,6 +5410,15 @@ AMDGPUAsmParser::parseSOppBrTarget(Opera</pre>
<pre>}</pre>
<pre><br></pre>
<pre>//===----------------------------------------------------------------------===//</pre>
<pre>+// Boolean holding registers</pre>
<pre>+//===----------------------------------------------------------------------===//</pre>
<pre>+</pre>
<pre>+OperandMatchResultTy</pre>
<pre>+AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {</pre>
<pre>+ return parseReg(Operands);</pre>
<pre>+}</pre>
<pre>+</pre>
<pre>+//===----------------------------------------------------------------------===//</pre>
<pre>// mubuf</pre>
<pre>//===----------------------------------------------------------------------===//</pre>
<pre><br></pre>
<pre>@@ -6294,7 +6329,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Ins</pre>
<pre>}</pre>
<pre>AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);</pre>
<pre>// Add the register arguments</pre>
<pre>- if (Op.isReg() && Op.getReg() == AMDGPU::VCC) {</pre>
<pre>+ if (Op.isReg() && validateVccOperand(Op.getReg())) {</pre>
<pre>// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.</pre>
<pre>// Skip it.</pre>
<pre>continue;</pre>
<pre>@@ -6437,7 +6472,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &In</pre>
<pre><br></pre>
<pre>for (unsigned E = Operands.size(); I != E; ++I) {</pre>
<pre>AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);</pre>
<pre>- if (skipVcc && !skippedVcc && Op.isReg() && Op.getReg() == AMDGPU::VCC) {</pre>
<pre>+ if (skipVcc && !skippedVcc && Op.isReg() &&</pre>
<pre>+ (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) {</pre>
<pre>// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.</pre>
<pre>// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)</pre>
<pre>// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -442,6 +442,7 @@ void AMDGPUInstPrinter::printVOPDst(cons</pre>
<pre><br></pre>
<pre>printOperand(MI, OpNo, STI, O);</pre>
<pre><br></pre>
<pre>+ // Print default vcc/vcc_lo operand.</pre>
<pre>switch (MI->getOpcode()) {</pre>
<pre>default: break;</pre>
<pre><br></pre>
<pre>@@ -589,7 +590,8 @@ void AMDGPUInstPrinter::printDefaultVccO</pre>
<pre> raw_ostream &O) {</pre>
<pre>if (OpNo > 0)</pre>
<pre>O << ", ";</pre>
<pre>- printRegOperand(AMDGPU::VCC, O, MRI);</pre>
<pre>+ printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?</pre>
<pre>+ AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);</pre>
<pre>if (OpNo == 0)</pre>
<pre>O << ", ";</pre>
<pre>}</pre>
<pre>@@ -597,6 +599,7 @@ void AMDGPUInstPrinter::printDefaultVccO</pre>
<pre>void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,</pre>
<pre> const MCSubtargetInfo &STI,</pre>
<pre> raw_ostream &O) {</pre>
<pre>+ // Print default vcc/vcc_lo operand of VOPC.</pre>
<pre>const MCInstrDesc &Desc = MII.get(MI->getOpcode());</pre>
<pre>if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&</pre>
<pre>(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||</pre>
<pre>@@ -680,6 +683,7 @@ void AMDGPUInstPrinter::printOperand(con</pre>
<pre>O << "/*INV_OP*/";</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+ // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.</pre>
<pre>switch (MI->getOpcode()) {</pre>
<pre>default: break;</pre>
<pre><br></pre>
<pre>@@ -749,6 +753,7 @@ void AMDGPUInstPrinter::printOperandAndI</pre>
<pre>if (InputModifiers & SISrcMods::SEXT)</pre>
<pre>O << ')';</pre>
<pre><br></pre>
<pre>+ // Print default vcc/vcc_lo operand of VOP2b.</pre>
<pre>switch (MI->getOpcode()) {</pre>
<pre>default: break;</pre>
<pre><br></pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -389,7 +389,7 @@ SIMCCodeEmitter::getSDWAVopcDstEncoding(</pre>
<pre>const MCOperand &MO = MI.getOperand(OpNo);</pre>
<pre><br></pre>
<pre>unsigned Reg = MO.getReg();</pre>
<pre>- if (Reg != AMDGPU::VCC) {</pre>
<pre>+ if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {</pre>
<pre>RegEnc |= MRI.getEncodingValue(Reg);</pre>
<pre>RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;</pre>
<pre>RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -6,6 +6,11 @@</pre>
<pre>//</pre>
<pre>//===----------------------------------------------------------------------===//</pre>
<pre><br></pre>
<pre>+def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,</pre>
<pre>+ AssemblerPredicate <"FeatureWavefrontSize32">;</pre>
<pre>+def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,</pre>
<pre>+ AssemblerPredicate <"FeatureWavefrontSize64">;</pre>
<pre>+</pre>
<pre>def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;</pre>
<pre><br></pre>
<pre>class GCNPredicateControl : PredicateControl {</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -188,9 +188,18 @@ class WrapTerminatorInst<SOP_Pseudo base</pre>
<pre>let CodeSize = base_inst.CodeSize;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+let WaveSizePredicate = isWave64 in {</pre>
<pre>def S_MOV_B64_term : WrapTerminatorInst<S_MOV_B64>;</pre>
<pre>def S_XOR_B64_term : WrapTerminatorInst<S_XOR_B64>;</pre>
<pre>def S_ANDN2_B64_term : WrapTerminatorInst<S_ANDN2_B64>;</pre>
<pre>+}</pre>
<pre>+</pre>
<pre>+let WaveSizePredicate = isWave32 in {</pre>
<pre>+def S_MOV_B32_term : WrapTerminatorInst<S_MOV_B32>;</pre>
<pre>+def S_XOR_B32_term : WrapTerminatorInst<S_XOR_B32>;</pre>
<pre>+def S_OR_B32_term : WrapTerminatorInst<S_OR_B32>;</pre>
<pre>+def S_ANDN2_B32_term : WrapTerminatorInst<S_ANDN2_B32>;</pre>
<pre>+}</pre>
<pre><br></pre>
<pre>def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),</pre>
<pre>[(int_amdgcn_wave_barrier)]> {</pre>
<pre>@@ -343,6 +352,15 @@ def SI_INIT_EXEC : SPseudoInstSI <</pre>
<pre>let Defs = [EXEC];</pre>
<pre>let usesCustomInserter = 1;</pre>
<pre>let isAsCheapAsAMove = 1;</pre>
<pre>+ let WaveSizePredicate = isWave64;</pre>
<pre>+}</pre>
<pre>+</pre>
<pre>+def SI_INIT_EXEC_LO : SPseudoInstSI <</pre>
<pre>+ (outs), (ins i32imm:$src), []> {</pre>
<pre>+ let Defs = [EXEC_LO];</pre>
<pre>+ let usesCustomInserter = 1;</pre>
<pre>+ let isAsCheapAsAMove = 1;</pre>
<pre>+ let WaveSizePredicate = isWave32;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>def SI_INIT_EXEC_FROM_INPUT : SPseudoInstSI <</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -275,6 +275,21 @@ let SubtargetPredicate = isGFX9Plus in {</pre>
<pre>} // End SubtargetPredicate = isGFX9Plus</pre>
<pre><br></pre>
<pre>let SubtargetPredicate = isGFX10Plus in {</pre>
<pre>+ let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {</pre>
<pre>+ def S_AND_SAVEEXEC_B32 : SOP1_32<"s_and_saveexec_b32">;</pre>
<pre>+ def S_OR_SAVEEXEC_B32 : SOP1_32<"s_or_saveexec_b32">;</pre>
<pre>+ def S_XOR_SAVEEXEC_B32 : SOP1_32<"s_xor_saveexec_b32">;</pre>
<pre>+ def S_ANDN2_SAVEEXEC_B32 : SOP1_32<"s_andn2_saveexec_b32">;</pre>
<pre>+ def S_ORN2_SAVEEXEC_B32 : SOP1_32<"s_orn2_saveexec_b32">;</pre>
<pre>+ def S_NAND_SAVEEXEC_B32 : SOP1_32<"s_nand_saveexec_b32">;</pre>
<pre>+ def S_NOR_SAVEEXEC_B32 : SOP1_32<"s_nor_saveexec_b32">;</pre>
<pre>+ def S_XNOR_SAVEEXEC_B32 : SOP1_32<"s_xnor_saveexec_b32">;</pre>
<pre>+ def S_ANDN1_SAVEEXEC_B32 : SOP1_32<"s_andn1_saveexec_b32">;</pre>
<pre>+ def S_ORN1_SAVEEXEC_B32 : SOP1_32<"s_orn1_saveexec_b32">;</pre>
<pre>+ def S_ANDN1_WREXEC_B32 : SOP1_32<"s_andn1_wrexec_b32">;</pre>
<pre>+ def S_ANDN2_WREXEC_B32 : SOP1_32<"s_andn2_wrexec_b32">;</pre>
<pre>+ } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC]</pre>
<pre>+</pre>
<pre>let Uses = [M0] in {</pre>
<pre>def S_MOVRELSD_2_B32 : SOP1_32<"s_movrelsd_2_b32">;</pre>
<pre>} // End Uses = [M0]</pre>
<pre>@@ -782,6 +797,9 @@ let SubtargetPredicate = isGFX10Plus in</pre>
<pre>let has_sdst = 0;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+ def S_SUBVECTOR_LOOP_BEGIN : SOPK_32_BR<"s_subvector_loop_begin">;</pre>
<pre>+ def S_SUBVECTOR_LOOP_END : SOPK_32_BR<"s_subvector_loop_end">;</pre>
<pre>+</pre>
<pre>def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">;</pre>
<pre>def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">;</pre>
<pre>def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">;</pre>
<pre>@@ -1215,6 +1233,18 @@ defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_</pre>
<pre>defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>;</pre>
<pre>defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>;</pre>
<pre>defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>;</pre>
<pre>+defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03c>;</pre>
<pre>+defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03d>;</pre>
<pre>+defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03e>;</pre>
<pre>+defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03f>;</pre>
<pre>+defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x040>;</pre>
<pre>+defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x041>;</pre>
<pre>+defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x042>;</pre>
<pre>+defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x043>;</pre>
<pre>+defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x044>;</pre>
<pre>+defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x045>;</pre>
<pre>+defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10<0x046>;</pre>
<pre>+defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10<0x047>;</pre>
<pre>defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>;</pre>
<pre><br></pre>
<pre>//===----------------------------------------------------------------------===//</pre>
<pre>@@ -1382,6 +1412,8 @@ defm S_WAITCNT_VSCNT : SOPK_Real3</pre>
<pre>defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>;</pre>
<pre>defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>;</pre>
<pre>defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>;</pre>
<pre>+defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>;</pre>
<pre>+defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>;</pre>
<pre><br></pre>
<pre>//===----------------------------------------------------------------------===//</pre>
<pre>// SOPK - GFX6, GFX7.</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -380,12 +380,17 @@ unsigned getNumSGPRBlocks(const MCSubtar</pre>
<pre>return NumSGPRs / getSGPREncodingGranule(STI) - 1;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>-unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI) {</pre>
<pre>- return 4;</pre>
<pre>+unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,</pre>
<pre>+ Optional<bool> EnableWavefrontSize32) {</pre>
<pre>+ bool IsWave32 = EnableWavefrontSize32 ?</pre>
<pre>+ *EnableWavefrontSize32 :</pre>
<pre>+ STI->getFeatureBits().test(FeatureWavefrontSize32);</pre>
<pre>+ return IsWave32 ? 8 : 4;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>-unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI) {</pre>
<pre>- return getVGPRAllocGranule(STI);</pre>
<pre>+unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,</pre>
<pre>+ Optional<bool> EnableWavefrontSize32) {</pre>
<pre>+ return getVGPRAllocGranule(STI, EnableWavefrontSize32);</pre>
<pre>}</pre>
<pre><br></pre>
<pre>unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {</pre>
<pre>@@ -416,10 +421,12 @@ unsigned getMaxNumVGPRs(const MCSubtarge</pre>
<pre>return std::min(MaxNumVGPRs, AddressableNumVGPRs);</pre>
<pre>}</pre>
<pre><br></pre>
<pre>-unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs) {</pre>
<pre>- NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(STI));</pre>
<pre>+unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,</pre>
<pre>+ Optional<bool> EnableWavefrontSize32) {</pre>
<pre>+ NumVGPRs = alignTo(std::max(1u, NumVGPRs),</pre>
<pre>+ getVGPREncodingGranule(STI, EnableWavefrontSize32));</pre>
<pre>// VGPRBlocks is actual number of VGPR blocks minus 1.</pre>
<pre>- return NumVGPRs / getVGPREncodingGranule(STI) - 1;</pre>
<pre>+ return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>} // end namespace IsaInfo</pre>
<pre>@@ -437,7 +444,6 @@ void initDefaultAMDKernelCodeT(amd_kerne</pre>
<pre>Header.amd_machine_version_minor = Version.Minor;</pre>
<pre>Header.amd_machine_version_stepping = Version.Stepping;</pre>
<pre>Header.kernel_code_entry_byte_offset = sizeof(Header);</pre>
<pre>- // wavefront_size is specified as a power of 2: 2^6 = 64 threads.</pre>
<pre>Header.wavefront_size = 6;</pre>
<pre><br></pre>
<pre>// If the code object does not support indirect functions, then the value must</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -150,10 +150,18 @@ unsigned getNumExtraSGPRs(const MCSubtar</pre>
<pre>unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);</pre>
<pre><br></pre>
<pre>/// \returns VGPR allocation granularity for given subtarget \p STI.</pre>
<pre>-unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI);</pre>
<pre>+///</pre>
<pre>+/// For subtargets which support it, \p EnableWavefrontSize32 should match</pre>
<pre>+/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.</pre>
<pre>+unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,</pre>
<pre>+ Optional<bool> EnableWavefrontSize32 = None);</pre>
<pre><br></pre>
<pre>/// \returns VGPR encoding granularity for given subtarget \p STI.</pre>
<pre>-unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI);</pre>
<pre>+///</pre>
<pre>+/// For subtargets which support it, \p EnableWavefrontSize32 should match</pre>
<pre>+/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.</pre>
<pre>+unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,</pre>
<pre>+ Optional<bool> EnableWavefrontSize32 = None);</pre>
<pre><br></pre>
<pre>/// \returns Total number of VGPRs for given subtarget \p STI.</pre>
<pre>unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);</pre>
<pre>@@ -171,7 +179,11 @@ unsigned getMaxNumVGPRs(const MCSubtarge</pre>
<pre><br></pre>
<pre>/// \returns Number of VGPR blocks needed for given subtarget \p STI when</pre>
<pre>/// \p NumVGPRs are used.</pre>
<pre>-unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);</pre>
<pre>+///</pre>
<pre>+/// For subtargets which support it, \p EnableWavefrontSize32 should match the</pre>
<pre>+/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.</pre>
<pre>+unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,</pre>
<pre>+ Optional<bool> EnableWavefrontSize32 = None);</pre>
<pre><br></pre>
<pre>} // end namespace IsaInfo</pre>
<pre><br></pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -199,7 +199,12 @@ class VOP2bInstAlias <VOP2_Pseudo ps, In</pre>
<pre>}</pre>
<pre><br></pre>
<pre>multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {</pre>
<pre>+ let WaveSizePredicate = isWave32 in {</pre>
<pre>+ def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;</pre>
<pre>+ }</pre>
<pre>+ let WaveSizePredicate = isWave64 in {</pre>
<pre>def : VOP2bInstAlias<ps, inst, OpName, "vcc">;</pre>
<pre>+ }</pre>
<pre>}</pre>
<pre><br></pre>
<pre>multiclass VOP2eInst <string opName,</pre>
<pre>@@ -234,7 +239,12 @@ class VOP2eInstAlias <VOP2_Pseudo ps, In</pre>
<pre>}</pre>
<pre><br></pre>
<pre>multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {</pre>
<pre>+ let WaveSizePredicate = isWave32 in {</pre>
<pre>+ def : VOP2eInstAlias<ps, inst, "vcc_lo">;</pre>
<pre>+ }</pre>
<pre>+ let WaveSizePredicate = isWave64 in {</pre>
<pre>def : VOP2eInstAlias<ps, inst, "vcc">;</pre>
<pre>+ }</pre>
<pre>}</pre>
<pre><br></pre>
<pre>class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {</pre>
<pre>@@ -953,6 +963,30 @@ let AssemblerPredicate = isGFX10Plus, De</pre>
<pre> let DecoderNamespace = "DPP8";</pre>
<pre>}</pre>
<pre><br></pre>
<pre>+ let WaveSizePredicate = isWave32 in {</pre>
<pre>+ def _sdwa_w32_gfx10 :</pre>
<pre>+ Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,</pre>
<pre>+ VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {</pre>
<pre>+ VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");</pre>
<pre>+ let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);</pre>
<pre>+ let isAsmParserOnly = 1;</pre>
<pre>+ let DecoderNamespace = "SDWA10";</pre>
<pre>+ }</pre>
<pre>+ def _dpp_w32_gfx10 :</pre>
<pre>+ VOP2_DPP16<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {</pre>
<pre>+ string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;</pre>
<pre>+ let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);</pre>
<pre>+ let isAsmParserOnly = 1;</pre>
<pre>+ }</pre>
<pre>+ def _dpp8_w32_gfx10 :</pre>
<pre>+ VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {</pre>
<pre>+ string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;</pre>
<pre>+ let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);</pre>
<pre>+ let isAsmParserOnly = 1;</pre>
<pre>+ }</pre>
<pre>+ } // End WaveSizePredicate = isWave32</pre>
<pre>+</pre>
<pre>+ let WaveSizePredicate = isWave64 in {</pre>
<pre>def _sdwa_w64_gfx10 :</pre>
<pre> Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,</pre>
<pre> VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {</pre>
<pre>@@ -973,6 +1007,7 @@ let AssemblerPredicate = isGFX10Plus, De</pre>
<pre> let AsmString = asmName # AsmDPP8;</pre>
<pre> let isAsmParserOnly = 1;</pre>
<pre> }</pre>
<pre>+ } // End WaveSizePredicate = isWave64</pre>
<pre>}</pre>
<pre><br></pre>
<pre>//===----------------------------- VOP3Only -----------------------------===//</pre>
<pre><br></pre>
<pre>Modified: llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td</pre>
<pre>URL: </pre>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td?rev=363299&r1=363298&r2=363299&view=diff">
<pre>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</pre>
</a>
<pre><br></pre>
<pre>==============================================================================</pre>
<pre>--- llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td (original)</pre>
<pre>+++ llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td Thu Jun 13 12:18:29 2019</pre>
<pre>@@ -165,9 +165,16 @@ class VOPCInstAlias <VOP3_Pseudo ps, Ins</pre>
<pre>multiclass VOPCInstAliases <string OpName, string Arch> {</pre>
<pre>def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),</pre>
<pre> !cast<Instruction>(OpName#"_e32_"#Arch)>;</pre>
<pre>+ let WaveSizePredicate = isWave32 in {</pre>
<pre>+ def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),</pre>
<pre>+ !cast<Instruction>(OpName#"_e32_"#Arch),</pre>
<pre>+ "vcc_lo, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;</pre>
<pre>+ }</pre>
<pre>+ let WaveSizePredicate = isWave64 in {</pre>
<pre>def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),</pre>
<pre> !cast<Instruction>(OpName#"_e32_"#Arch),</pre>
<pre> "vcc, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;</pre>
<pre>+ }</pre>
<pre>}</pre>
<pre><br></pre>
<pre>multiclass VOPCXInstAliases <string OpName, string Arch> {</pre>
<pre>@@ -740,10 +747,17 @@ defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16</pre>
<pre>// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()</pre>
<pre>// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.</pre>
<pre>multiclass ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {</pre>
<pre>+ let WaveSizePredicate = isWave64 in</pre>
<pre>def : GCNPat <</pre>
<pre>(i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),</pre>
<pre>(i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))</pre>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<pre>;</pre>
</blockquote>
<pre>+</pre>
<pre>+ let WaveSizePredicate = isWave32 in</pre>
<pre>+ def : GCNPat <</pre>
<pre>+ (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),</pre>
<pre>+ (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32))</pre>
<pre>+ >;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>;</pre>
<pre>@@ -780,12 +794,21 @@ defm : ICMP_Pattern <COND_SLT, V_CMP_LT_</pre>
<pre>defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;</pre>
<pre><br></pre>
<pre>multiclass FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {</pre>
<pre>+ let WaveSizePredicate = isWave64 in</pre>
<pre>def : GCNPat <</pre>
<pre>(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),</pre>
<pre> (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),</pre>
<pre>(i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,</pre>
<pre> DSTCLAMP.NONE), SReg_64))</pre>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<pre>;</pre>
</blockquote>
<pre>+</pre>
<pre>+ let WaveSizePredicate = isWave32 in</pre>
<pre>+ def : GCNPat <</pre>
<pre>+ (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),</pre>
<pre>+ (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),</pre>
<pre>+ (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,</pre>
<pre>+ DSTCLAMP.NONE), SReg_32))</pre>
<pre>+ >;</pre>
<pre>}</pre>
<pre><br></pre>
<pre>defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;</pre>
<pre><br></pre>
<pre><br></pre>
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