<div dir="ltr">This breaks the build for me: <div>ninja: Entering directory `/usr/local/google/home/kcc/llvm-build' [7/7] Building AMDGPUGenDAGISel.inc...<br>FAILED: lib/Target/AMDGPU/AMDGPUGenDAGISel.inc<br>cd /usr/local/google/home/kcc/llvm-build && /usr/local/google/home/kcc/llvm-build/bin/llvm-tblgen -gen-dag-isel -I /usr/local/google/home/kcc/llvm/llvm/lib/Target/AMDGPU -I /usr/local/google/home/kcc/llvm/llvm/include -I /usr/local/google/home/kcc/llvm/llvm/lib/Target /usr/local/google/home/kcc/llvm/llvm/lib/Target/AMDGPU/AMDGPU.td -o lib/Target/AMDGPU/AMDGPUGenDAGISel.inc -d lib/Target/AMDGPU/AMDGPUGenDAGISel.inc.d<br>Type set is empty for each HW mode:<br>possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).<br>anonymous_3351: (AMDGPUsetcc:{ *:[] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (cond:{ *:[Other] })<<P:Predicate_COND_EQ>>)<br>UNREACHABLE executed at /usr/local/google/home/kcc/llvm/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:821!<br><div><br></div></div><div><br></div><div><br></div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jun 13, 2019 at 12:15 PM Stanislav Mekhanoshin via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: rampitec<br>
Date: Thu Jun 13 12:18:29 2019<br>
New Revision: 363299<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=363299&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=363299&view=rev</a><br>
Log:<br>
[AMDGPU] gfx1010 base changes for wave32<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D63293" rel="noreferrer" target="_blank">https://reviews.llvm.org/D63293</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp<br>
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td<br>
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h<br>
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td<br>
llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Thu Jun 13 12:18:29 2019<br>
@@ -69,9 +69,11 @@ class PredicateControl {<br>
Predicate SubtargetPredicate = TruePredicate;<br>
list<Predicate> AssemblerPredicates = [];<br>
Predicate AssemblerPredicate = TruePredicate;<br>
+ Predicate WaveSizePredicate = TruePredicate;<br>
list<Predicate> OtherPredicates = [];<br>
list<Predicate> Predicates = !listconcat([SubtargetPredicate,<br>
- AssemblerPredicate],<br>
+ AssemblerPredicate,<br>
+ WaveSizePredicate],<br>
AssemblerPredicates,<br>
OtherPredicates);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Thu Jun 13 12:18:29 2019<br>
@@ -94,6 +94,16 @@ GCNSubtarget::initializeSubtargetDepende<br>
<br>
FullFS += "+enable-prt-strict-null,"; // This is overridden by a disable in FS<br>
<br>
+ // Disable mutually exclusive bits.<br>
+ if (FS.find_lower("+wavefrontsize") != StringRef::npos) {<br>
+ if (FS.find_lower("wavefrontsize16") == StringRef::npos)<br>
+ FullFS += "-wavefrontsize16,";<br>
+ if (FS.find_lower("wavefrontsize32") == StringRef::npos)<br>
+ FullFS += "-wavefrontsize32,";<br>
+ if (FS.find_lower("wavefrontsize64") == StringRef::npos)<br>
+ FullFS += "-wavefrontsize64,";<br>
+ }<br>
+<br>
FullFS += FS;<br>
<br>
ParseSubtargetFeatures(GPU, FullFS);<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Thu Jun 13 12:18:29 2019<br>
@@ -375,6 +375,8 @@ public:<br>
return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);<br>
}<br>
<br>
+ bool isBoolReg() const;<br>
+<br>
bool isSCSrcF16() const {<br>
return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);<br>
}<br>
@@ -616,6 +618,10 @@ public:<br>
<br>
void addRegOperands(MCInst &Inst, unsigned N) const;<br>
<br>
+ void addBoolRegOperands(MCInst &Inst, unsigned N) const {<br>
+ addRegOperands(Inst, N);<br>
+ }<br>
+<br>
void addRegOrImmOperands(MCInst &Inst, unsigned N) const {<br>
if (isRegKind())<br>
addRegOperands(Inst, N);<br>
@@ -881,6 +887,8 @@ private:<br>
/// \param VCCUsed [in] Whether VCC special SGPR is reserved.<br>
/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.<br>
/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.<br>
+ /// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel<br>
+ /// descriptor field, if valid.<br>
/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.<br>
/// \param VGPRRange [in] Token range, used for VGPR diagnostics.<br>
/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.<br>
@@ -889,9 +897,10 @@ private:<br>
/// \param SGPRBlocks [out] Result SGPR block count.<br>
bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,<br>
bool FlatScrUsed, bool XNACKUsed,<br>
- unsigned NextFreeVGPR, SMRange VGPRRange,<br>
- unsigned NextFreeSGPR, SMRange SGPRRange,<br>
- unsigned &VGPRBlocks, unsigned &SGPRBlocks);<br>
+ Optional<bool> EnableWavefrontSize32, unsigned NextFreeVGPR,<br>
+ SMRange VGPRRange, unsigned NextFreeSGPR,<br>
+ SMRange SGPRRange, unsigned &VGPRBlocks,<br>
+ unsigned &SGPRBlocks);<br>
bool ParseDirectiveAMDGCNTarget();<br>
bool ParseDirectiveAMDHSAKernel();<br>
bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);<br>
@@ -1159,6 +1168,7 @@ private:<br>
bool validateMIMGDim(const MCInst &Inst);<br>
bool validateLdsDirect(const MCInst &Inst);<br>
bool validateOpSel(const MCInst &Inst);<br>
+ bool validateVccOperand(unsigned Reg) const;<br>
bool validateVOP3Literal(const MCInst &Inst) const;<br>
bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);<br>
bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;<br>
@@ -1190,6 +1200,7 @@ public:<br>
OperandMatchResultTy parseInterpSlot(OperandVector &Operands);<br>
OperandMatchResultTy parseInterpAttr(OperandVector &Operands);<br>
OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);<br>
+ OperandMatchResultTy parseBoolReg(OperandVector &Operands);<br>
<br>
bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,<br>
const unsigned MinVal,<br>
@@ -1479,6 +1490,11 @@ bool AMDGPUOperand::isSDWAInt32Operand()<br>
return isSDWAOperand(MVT::i32);<br>
}<br>
<br>
+bool AMDGPUOperand::isBoolReg() const {<br>
+ return AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?<br>
+ isSCSrcB64() : isSCSrcB32();<br>
+}<br>
+<br>
uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const<br>
{<br>
assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());<br>
@@ -3030,6 +3046,13 @@ bool AMDGPUAsmParser::validateOpSel(cons<br>
return true;<br>
}<br>
<br>
+// Check if VCC register matches wavefront size<br>
+bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {<br>
+ auto FB = getFeatureBits();<br>
+ return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) ||<br>
+ (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);<br>
+}<br>
+<br>
// VOP3 literal is only allowed in GFX10+ and only one can be used<br>
bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const {<br>
unsigned Opcode = Inst.getOpcode();<br>
@@ -3267,9 +3290,9 @@ bool AMDGPUAsmParser::OutOfRangeError(SM<br>
<br>
bool AMDGPUAsmParser::calculateGPRBlocks(<br>
const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,<br>
- bool XNACKUsed, unsigned NextFreeVGPR, SMRange VGPRRange,<br>
- unsigned NextFreeSGPR, SMRange SGPRRange, unsigned &VGPRBlocks,<br>
- unsigned &SGPRBlocks) {<br>
+ bool XNACKUsed, Optional<bool> EnableWavefrontSize32, unsigned NextFreeVGPR,<br>
+ SMRange VGPRRange, unsigned NextFreeSGPR, SMRange SGPRRange,<br>
+ unsigned &VGPRBlocks, unsigned &SGPRBlocks) {<br>
// TODO(scott.linder): These calculations are duplicated from<br>
// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.<br>
IsaVersion Version = getIsaVersion(getSTI().getCPU());<br>
@@ -3298,7 +3321,8 @@ bool AMDGPUAsmParser::calculateGPRBlocks<br>
NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;<br>
}<br>
<br>
- VGPRBlocks = IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs);<br>
+ VGPRBlocks =<br>
+ IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);<br>
SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);<br>
<br>
return false;<br>
@@ -3329,6 +3353,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDH<br>
bool ReserveVCC = true;<br>
bool ReserveFlatScr = true;<br>
bool ReserveXNACK = hasXNACK();<br>
+ Optional<bool> EnableWavefrontSize32;<br>
<br>
while (true) {<br>
while (getLexer().is(AsmToken::EndOfStatement))<br>
@@ -3547,8 +3572,9 @@ bool AMDGPUAsmParser::ParseDirectiveAMDH<br>
unsigned VGPRBlocks;<br>
unsigned SGPRBlocks;<br>
if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,<br>
- ReserveXNACK, NextFreeVGPR, VGPRRange, NextFreeSGPR,<br>
- SGPRRange, VGPRBlocks, SGPRBlocks))<br>
+ ReserveXNACK, EnableWavefrontSize32, NextFreeVGPR,<br>
+ VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,<br>
+ SGPRBlocks))<br>
return true;<br>
<br>
if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH>(<br>
@@ -5384,6 +5410,15 @@ AMDGPUAsmParser::parseSOppBrTarget(Opera<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
+// Boolean holding registers<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+OperandMatchResultTy<br>
+AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {<br>
+ return parseReg(Operands);<br>
+}<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
// mubuf<br>
//===----------------------------------------------------------------------===//<br>
<br>
@@ -6294,7 +6329,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Ins<br>
}<br>
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);<br>
// Add the register arguments<br>
- if (Op.isReg() && Op.getReg() == AMDGPU::VCC) {<br>
+ if (Op.isReg() && validateVccOperand(Op.getReg())) {<br>
// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.<br>
// Skip it.<br>
continue;<br>
@@ -6437,7 +6472,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &In<br>
<br>
for (unsigned E = Operands.size(); I != E; ++I) {<br>
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);<br>
- if (skipVcc && !skippedVcc && Op.isReg() && Op.getReg() == AMDGPU::VCC) {<br>
+ if (skipVcc && !skippedVcc && Op.isReg() &&<br>
+ (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) {<br>
// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.<br>
// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)<br>
// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp Thu Jun 13 12:18:29 2019<br>
@@ -442,6 +442,7 @@ void AMDGPUInstPrinter::printVOPDst(cons<br>
<br>
printOperand(MI, OpNo, STI, O);<br>
<br>
+ // Print default vcc/vcc_lo operand.<br>
switch (MI->getOpcode()) {<br>
default: break;<br>
<br>
@@ -589,7 +590,8 @@ void AMDGPUInstPrinter::printDefaultVccO<br>
raw_ostream &O) {<br>
if (OpNo > 0)<br>
O << ", ";<br>
- printRegOperand(AMDGPU::VCC, O, MRI);<br>
+ printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?<br>
+ AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);<br>
if (OpNo == 0)<br>
O << ", ";<br>
}<br>
@@ -597,6 +599,7 @@ void AMDGPUInstPrinter::printDefaultVccO<br>
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,<br>
const MCSubtargetInfo &STI,<br>
raw_ostream &O) {<br>
+ // Print default vcc/vcc_lo operand of VOPC.<br>
const MCInstrDesc &Desc = MII.get(MI->getOpcode());<br>
if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&<br>
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||<br>
@@ -680,6 +683,7 @@ void AMDGPUInstPrinter::printOperand(con<br>
O << "/*INV_OP*/";<br>
}<br>
<br>
+ // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.<br>
switch (MI->getOpcode()) {<br>
default: break;<br>
<br>
@@ -749,6 +753,7 @@ void AMDGPUInstPrinter::printOperandAndI<br>
if (InputModifiers & SISrcMods::SEXT)<br>
O << ')';<br>
<br>
+ // Print default vcc/vcc_lo operand of VOP2b.<br>
switch (MI->getOpcode()) {<br>
default: break;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp Thu Jun 13 12:18:29 2019<br>
@@ -389,7 +389,7 @@ SIMCCodeEmitter::getSDWAVopcDstEncoding(<br>
const MCOperand &MO = MI.getOperand(OpNo);<br>
<br>
unsigned Reg = MO.getReg();<br>
- if (Reg != AMDGPU::VCC) {<br>
+ if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {<br>
RegEnc |= MRI.getEncodingValue(Reg);<br>
RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;<br>
RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Thu Jun 13 12:18:29 2019<br>
@@ -6,6 +6,11 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
+def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,<br>
+ AssemblerPredicate <"FeatureWavefrontSize32">;<br>
+def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,<br>
+ AssemblerPredicate <"FeatureWavefrontSize64">;<br>
+<br>
def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;<br>
<br>
class GCNPredicateControl : PredicateControl {<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Thu Jun 13 12:18:29 2019<br>
@@ -188,9 +188,18 @@ class WrapTerminatorInst<SOP_Pseudo base<br>
let CodeSize = base_inst.CodeSize;<br>
}<br>
<br>
+let WaveSizePredicate = isWave64 in {<br>
def S_MOV_B64_term : WrapTerminatorInst<S_MOV_B64>;<br>
def S_XOR_B64_term : WrapTerminatorInst<S_XOR_B64>;<br>
def S_ANDN2_B64_term : WrapTerminatorInst<S_ANDN2_B64>;<br>
+}<br>
+<br>
+let WaveSizePredicate = isWave32 in {<br>
+def S_MOV_B32_term : WrapTerminatorInst<S_MOV_B32>;<br>
+def S_XOR_B32_term : WrapTerminatorInst<S_XOR_B32>;<br>
+def S_OR_B32_term : WrapTerminatorInst<S_OR_B32>;<br>
+def S_ANDN2_B32_term : WrapTerminatorInst<S_ANDN2_B32>;<br>
+}<br>
<br>
def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),<br>
[(int_amdgcn_wave_barrier)]> {<br>
@@ -343,6 +352,15 @@ def SI_INIT_EXEC : SPseudoInstSI <<br>
let Defs = [EXEC];<br>
let usesCustomInserter = 1;<br>
let isAsCheapAsAMove = 1;<br>
+ let WaveSizePredicate = isWave64;<br>
+}<br>
+<br>
+def SI_INIT_EXEC_LO : SPseudoInstSI <<br>
+ (outs), (ins i32imm:$src), []> {<br>
+ let Defs = [EXEC_LO];<br>
+ let usesCustomInserter = 1;<br>
+ let isAsCheapAsAMove = 1;<br>
+ let WaveSizePredicate = isWave32;<br>
}<br>
<br>
def SI_INIT_EXEC_FROM_INPUT : SPseudoInstSI <<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td Thu Jun 13 12:18:29 2019<br>
@@ -275,6 +275,21 @@ let SubtargetPredicate = isGFX9Plus in {<br>
} // End SubtargetPredicate = isGFX9Plus<br>
<br>
let SubtargetPredicate = isGFX10Plus in {<br>
+ let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {<br>
+ def S_AND_SAVEEXEC_B32 : SOP1_32<"s_and_saveexec_b32">;<br>
+ def S_OR_SAVEEXEC_B32 : SOP1_32<"s_or_saveexec_b32">;<br>
+ def S_XOR_SAVEEXEC_B32 : SOP1_32<"s_xor_saveexec_b32">;<br>
+ def S_ANDN2_SAVEEXEC_B32 : SOP1_32<"s_andn2_saveexec_b32">;<br>
+ def S_ORN2_SAVEEXEC_B32 : SOP1_32<"s_orn2_saveexec_b32">;<br>
+ def S_NAND_SAVEEXEC_B32 : SOP1_32<"s_nand_saveexec_b32">;<br>
+ def S_NOR_SAVEEXEC_B32 : SOP1_32<"s_nor_saveexec_b32">;<br>
+ def S_XNOR_SAVEEXEC_B32 : SOP1_32<"s_xnor_saveexec_b32">;<br>
+ def S_ANDN1_SAVEEXEC_B32 : SOP1_32<"s_andn1_saveexec_b32">;<br>
+ def S_ORN1_SAVEEXEC_B32 : SOP1_32<"s_orn1_saveexec_b32">;<br>
+ def S_ANDN1_WREXEC_B32 : SOP1_32<"s_andn1_wrexec_b32">;<br>
+ def S_ANDN2_WREXEC_B32 : SOP1_32<"s_andn2_wrexec_b32">;<br>
+ } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC]<br>
+<br>
let Uses = [M0] in {<br>
def S_MOVRELSD_2_B32 : SOP1_32<"s_movrelsd_2_b32">;<br>
} // End Uses = [M0]<br>
@@ -782,6 +797,9 @@ let SubtargetPredicate = isGFX10Plus in<br>
let has_sdst = 0;<br>
}<br>
<br>
+ def S_SUBVECTOR_LOOP_BEGIN : SOPK_32_BR<"s_subvector_loop_begin">;<br>
+ def S_SUBVECTOR_LOOP_END : SOPK_32_BR<"s_subvector_loop_end">;<br>
+<br>
def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">;<br>
def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">;<br>
def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">;<br>
@@ -1215,6 +1233,18 @@ defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_<br>
defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>;<br>
defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>;<br>
defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>;<br>
+defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03c>;<br>
+defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03d>;<br>
+defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03e>;<br>
+defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03f>;<br>
+defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x040>;<br>
+defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x041>;<br>
+defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x042>;<br>
+defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x043>;<br>
+defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x044>;<br>
+defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x045>;<br>
+defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10<0x046>;<br>
+defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10<0x047>;<br>
defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
@@ -1382,6 +1412,8 @@ defm S_WAITCNT_VSCNT : SOPK_Real3<br>
defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>;<br>
defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>;<br>
defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>;<br>
+defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>;<br>
+defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// SOPK - GFX6, GFX7.<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Thu Jun 13 12:18:29 2019<br>
@@ -380,12 +380,17 @@ unsigned getNumSGPRBlocks(const MCSubtar<br>
return NumSGPRs / getSGPREncodingGranule(STI) - 1;<br>
}<br>
<br>
-unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI) {<br>
- return 4;<br>
+unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,<br>
+ Optional<bool> EnableWavefrontSize32) {<br>
+ bool IsWave32 = EnableWavefrontSize32 ?<br>
+ *EnableWavefrontSize32 :<br>
+ STI->getFeatureBits().test(FeatureWavefrontSize32);<br>
+ return IsWave32 ? 8 : 4;<br>
}<br>
<br>
-unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI) {<br>
- return getVGPRAllocGranule(STI);<br>
+unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,<br>
+ Optional<bool> EnableWavefrontSize32) {<br>
+ return getVGPRAllocGranule(STI, EnableWavefrontSize32);<br>
}<br>
<br>
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {<br>
@@ -416,10 +421,12 @@ unsigned getMaxNumVGPRs(const MCSubtarge<br>
return std::min(MaxNumVGPRs, AddressableNumVGPRs);<br>
}<br>
<br>
-unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs) {<br>
- NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(STI));<br>
+unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,<br>
+ Optional<bool> EnableWavefrontSize32) {<br>
+ NumVGPRs = alignTo(std::max(1u, NumVGPRs),<br>
+ getVGPREncodingGranule(STI, EnableWavefrontSize32));<br>
// VGPRBlocks is actual number of VGPR blocks minus 1.<br>
- return NumVGPRs / getVGPREncodingGranule(STI) - 1;<br>
+ return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;<br>
}<br>
<br>
} // end namespace IsaInfo<br>
@@ -437,7 +444,6 @@ void initDefaultAMDKernelCodeT(amd_kerne<br>
Header.amd_machine_version_minor = Version.Minor;<br>
Header.amd_machine_version_stepping = Version.Stepping;<br>
Header.kernel_code_entry_byte_offset = sizeof(Header);<br>
- // wavefront_size is specified as a power of 2: 2^6 = 64 threads.<br>
Header.wavefront_size = 6;<br>
<br>
// If the code object does not support indirect functions, then the value must<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Thu Jun 13 12:18:29 2019<br>
@@ -150,10 +150,18 @@ unsigned getNumExtraSGPRs(const MCSubtar<br>
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);<br>
<br>
/// \returns VGPR allocation granularity for given subtarget \p STI.<br>
-unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI);<br>
+///<br>
+/// For subtargets which support it, \p EnableWavefrontSize32 should match<br>
+/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.<br>
+unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,<br>
+ Optional<bool> EnableWavefrontSize32 = None);<br>
<br>
/// \returns VGPR encoding granularity for given subtarget \p STI.<br>
-unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI);<br>
+///<br>
+/// For subtargets which support it, \p EnableWavefrontSize32 should match<br>
+/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.<br>
+unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,<br>
+ Optional<bool> EnableWavefrontSize32 = None);<br>
<br>
/// \returns Total number of VGPRs for given subtarget \p STI.<br>
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);<br>
@@ -171,7 +179,11 @@ unsigned getMaxNumVGPRs(const MCSubtarge<br>
<br>
/// \returns Number of VGPR blocks needed for given subtarget \p STI when<br>
/// \p NumVGPRs are used.<br>
-unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);<br>
+///<br>
+/// For subtargets which support it, \p EnableWavefrontSize32 should match the<br>
+/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.<br>
+unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,<br>
+ Optional<bool> EnableWavefrontSize32 = None);<br>
<br>
} // end namespace IsaInfo<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Thu Jun 13 12:18:29 2019<br>
@@ -199,7 +199,12 @@ class VOP2bInstAlias <VOP2_Pseudo ps, In<br>
}<br>
<br>
multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {<br>
+ let WaveSizePredicate = isWave32 in {<br>
+ def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;<br>
+ }<br>
+ let WaveSizePredicate = isWave64 in {<br>
def : VOP2bInstAlias<ps, inst, OpName, "vcc">;<br>
+ }<br>
}<br>
<br>
multiclass VOP2eInst <string opName,<br>
@@ -234,7 +239,12 @@ class VOP2eInstAlias <VOP2_Pseudo ps, In<br>
}<br>
<br>
multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {<br>
+ let WaveSizePredicate = isWave32 in {<br>
+ def : VOP2eInstAlias<ps, inst, "vcc_lo">;<br>
+ }<br>
+ let WaveSizePredicate = isWave64 in {<br>
def : VOP2eInstAlias<ps, inst, "vcc">;<br>
+ }<br>
}<br>
<br>
class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {<br>
@@ -953,6 +963,30 @@ let AssemblerPredicate = isGFX10Plus, De<br>
let DecoderNamespace = "DPP8";<br>
}<br>
<br>
+ let WaveSizePredicate = isWave32 in {<br>
+ def _sdwa_w32_gfx10 :<br>
+ Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,<br>
+ VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {<br>
+ VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");<br>
+ let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);<br>
+ let isAsmParserOnly = 1;<br>
+ let DecoderNamespace = "SDWA10";<br>
+ }<br>
+ def _dpp_w32_gfx10 :<br>
+ VOP2_DPP16<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {<br>
+ string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;<br>
+ let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);<br>
+ let isAsmParserOnly = 1;<br>
+ }<br>
+ def _dpp8_w32_gfx10 :<br>
+ VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {<br>
+ string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;<br>
+ let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);<br>
+ let isAsmParserOnly = 1;<br>
+ }<br>
+ } // End WaveSizePredicate = isWave32<br>
+<br>
+ let WaveSizePredicate = isWave64 in {<br>
def _sdwa_w64_gfx10 :<br>
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,<br>
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {<br>
@@ -973,6 +1007,7 @@ let AssemblerPredicate = isGFX10Plus, De<br>
let AsmString = asmName # AsmDPP8;<br>
let isAsmParserOnly = 1;<br>
}<br>
+ } // End WaveSizePredicate = isWave64<br>
}<br>
<br>
//===----------------------------- VOP3Only -----------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td?rev=363299&r1=363298&r2=363299&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td?rev=363299&r1=363298&r2=363299&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td Thu Jun 13 12:18:29 2019<br>
@@ -165,9 +165,16 @@ class VOPCInstAlias <VOP3_Pseudo ps, Ins<br>
multiclass VOPCInstAliases <string OpName, string Arch> {<br>
def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),<br>
!cast<Instruction>(OpName#"_e32_"#Arch)>;<br>
+ let WaveSizePredicate = isWave32 in {<br>
+ def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),<br>
+ !cast<Instruction>(OpName#"_e32_"#Arch),<br>
+ "vcc_lo, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;<br>
+ }<br>
+ let WaveSizePredicate = isWave64 in {<br>
def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),<br>
!cast<Instruction>(OpName#"_e32_"#Arch),<br>
"vcc, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;<br>
+ }<br>
}<br>
<br>
multiclass VOPCXInstAliases <string OpName, string Arch> {<br>
@@ -740,10 +747,17 @@ defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16<br>
// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()<br>
// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.<br>
multiclass ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {<br>
+ let WaveSizePredicate = isWave64 in<br>
def : GCNPat <<br>
(i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),<br>
(i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))<br>
>;<br>
+<br>
+ let WaveSizePredicate = isWave32 in<br>
+ def : GCNPat <<br>
+ (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),<br>
+ (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32))<br>
+ >;<br>
}<br>
<br>
defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>;<br>
@@ -780,12 +794,21 @@ defm : ICMP_Pattern <COND_SLT, V_CMP_LT_<br>
defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;<br>
<br>
multiclass FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {<br>
+ let WaveSizePredicate = isWave64 in<br>
def : GCNPat <<br>
(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),<br>
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),<br>
(i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,<br>
DSTCLAMP.NONE), SReg_64))<br>
>;<br>
+<br>
+ let WaveSizePredicate = isWave32 in<br>
+ def : GCNPat <<br>
+ (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),<br>
+ (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),<br>
+ (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,<br>
+ DSTCLAMP.NONE), SReg_32))<br>
+ >;<br>
}<br>
<br>
defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;<br>
<br>
<br>
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</blockquote></div>