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/* Font Definitions */
@font-face
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panose-1:2 1 6 0 3 1 1 1 1 1;}
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
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{font-family:"\@SimSun";
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/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman",serif;}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
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a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
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text-decoration:underline;}
span.EmailStyle17
{mso-style-type:personal-reply;
font-family:"Calibri",sans-serif;
color:#1F497D;}
.MsoChpDefault
{mso-style-type:export-only;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]-->
</head>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi David,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks for your advice! However, I have reverted this change. We found some unit tests failed due to this change, and Quentin also explained the reason why it
becoming reachable sometime. </span><a href="https://reviews.llvm.org/D62006">https://reviews.llvm.org/D62006</a><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Except that, I still prefer to the former code. It is friendly to people unfamiliar with this code for it implicitly showing RegisterBank has the same weight
as TargetRegisterClass. <o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Pengfei<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> David Blaikie [mailto:dblaikie@gmail.com]
<br>
<b>Sent:</b> Tuesday, June 4, 2019 3:39 AM<br>
<b>To:</b> Wang, Pengfei <pengfei.wang@intel.com><br>
<b>Cc:</b> llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm] r361912 - [X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Tue, May 28, 2019 at 7:17 PM Pengfei Wang via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Author: pengfei<br>
Date: Tue May 28 19:20:37 2019<br>
New Revision: 361912<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=361912&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=361912&view=rev</a><br>
Log:<br>
[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to<br>
avoid static check fail<br>
<br>
RegClassOrBank is an object of RegClassOrRegBank, which is defined as<br>
using llvm::RegClassOrRegBank = typedef PointerUnion<const<br>
TargetRegisterClass *, const RegisterBank *><br>
so control flow can not get here. Use ""llvm_unreachable" here to avoid<br>
"null pointer" confusion.<br>
<br>
Patch by Shengchen Kan (skan)<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D62006" target="_blank">
https://reviews.llvm.org/D62006</a><br>
<br>
Signed-off-by: pengfei <<a href="mailto:pengfei.wang@intel.com" target="_blank">pengfei.wang@intel.com</a>><br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361912&r1=361911&r2=361912&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361912&r1=361911&r2=361912&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue May 28 19:20:37 2019<br>
@@ -91,7 +91,9 @@ RegisterBankInfo::getRegBank(unsigned Re<br>
return RB;<br>
if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())<br>
return &getRegBankFromRegClass(*RC);<br>
- return nullptr;<br>
+<br>
+ llvm_unreachable("RegClassOrBank is either a const RegisterBank* or "<br>
+ "a const TargetRegisterClass*");<o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><br>
Could simplify this ^ further to:<br>
<br>
return &getRegBankFromRegClass(*RegClassOrBank.get<const TargetRegisterClass*>());<br>
<br>
(since the 'get' will assert the same way the unreachable would've - though if you prefer the more specific message you can provide with the unreachable, that's OK too)<o:p></o:p></p>
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<p class="MsoNormal"> }<br>
<br>
const TargetRegisterClass &<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361912&r1=361911&r2=361912&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361912&r1=361911&r2=361912&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Tue May 28 19:20:37 2019<br>
@@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRe<br>
assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&<br>
"Arguments and return value types must match");<br>
<br>
- const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);<br>
- if (!RegRB || RegRB->getID() != X86::GPRRegBankID)<br>
+ const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI);<br>
+ if (RegRB.getID() != X86::GPRRegBankID)<br>
return false;<br>
<br>
const static unsigned NumTypes = 4; // i8, i16, i32, i64<br>
@@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRe<br>
const DivRemEntry &TypeEntry = *OpEntryIt;<br>
const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];<br>
<br>
- const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);<br>
+ const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);<br>
if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||<br>
!RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||<br>
!RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {<br>
<br>
<br>
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