<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, May 28, 2019 at 7:17 PM Pengfei Wang via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: pengfei<br>
Date: Tue May 28 19:20:37 2019<br>
New Revision: 361912<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=361912&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=361912&view=rev</a><br>
Log:<br>
[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to<br>
avoid static check fail<br>
<br>
RegClassOrBank is an object of RegClassOrRegBank, which is defined as<br>
using llvm::RegClassOrRegBank = typedef PointerUnion<const<br>
TargetRegisterClass *, const RegisterBank *><br>
so control flow can not get here. Use ""llvm_unreachable" here to avoid<br>
"null pointer" confusion.<br>
<br>
Patch by Shengchen Kan (skan)<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D62006" rel="noreferrer" target="_blank">https://reviews.llvm.org/D62006</a><br>
<br>
Signed-off-by: pengfei <<a href="mailto:pengfei.wang@intel.com" target="_blank">pengfei.wang@intel.com</a>><br>
<br>
Modified:<br>
    llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp<br>
    llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361912&r1=361911&r2=361912&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361912&r1=361911&r2=361912&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue May 28 19:20:37 2019<br>
@@ -91,7 +91,9 @@ RegisterBankInfo::getRegBank(unsigned Re<br>
     return RB;<br>
   if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())<br>
     return &getRegBankFromRegClass(*RC);<br>
-  return nullptr;<br>
+<br>
+  llvm_unreachable("RegClassOrBank is either a const RegisterBank* or "<br>
+                   "a const TargetRegisterClass*");<br></blockquote><div><br>Could simplify this ^ further to:<br><br>return &getRegBankFromRegClass(*RegClassOrBank.get<const TargetRegisterClass*>());<br> <br>(since the 'get' will assert the same way the unreachable would've - though if you prefer the more specific message you can provide with the unreachable, that's OK too)<br><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
 }<br>
<br>
 const TargetRegisterClass &<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361912&r1=361911&r2=361912&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361912&r1=361911&r2=361912&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Tue May 28 19:20:37 2019<br>
@@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRe<br>
   assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&<br>
          "Arguments and return value types must match");<br>
<br>
-  const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);<br>
-  if (!RegRB || RegRB->getID() != X86::GPRRegBankID)<br>
+  const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI);<br>
+  if (RegRB.getID() != X86::GPRRegBankID)<br>
     return false;<br>
<br>
   const static unsigned NumTypes = 4; // i8, i16, i32, i64<br>
@@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRe<br>
   const DivRemEntry &TypeEntry = *OpEntryIt;<br>
   const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];<br>
<br>
-  const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);<br>
+  const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);<br>
   if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||<br>
       !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||<br>
       !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {<br>
<br>
<br>
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</blockquote></div></div>