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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks Craig! I will pay attention next time.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Pengfei<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Craig Topper [mailto:craig.topper@gmail.com]
<br>
<b>Sent:</b> Wednesday, May 29, 2019 10:56 AM<br>
<b>To:</b> Wang, Pengfei <pengfei.wang@intel.com><br>
<b>Cc:</b> llvm-commits@lists.llvm.org<br>
<b>Subject:</b> Re: [llvm] r361918 - Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Revert commit messages should use svn revision numbers not git commit hash.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">They should also include a reason for revert.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Tue, May 28, 2019 at 7:46 PM Pengfei Wang via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Author: pengfei<br>
Date: Tue May 28 19:49:59 2019<br>
New Revision: 361918<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=361918&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=361918&view=rev</a><br>
Log:<br>
Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"<br>
<br>
This reverts commit c1b3716614bc0a107e6f41a7d3d503baefad8a5b.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361918&r1=361917&r2=361918&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361918&r1=361917&r2=361918&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue May 28 19:49:59 2019<br>
@@ -91,9 +91,7 @@ RegisterBankInfo::getRegBank(unsigned Re<br>
return RB;<br>
if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())<br>
return &getRegBankFromRegClass(*RC);<br>
-<br>
- llvm_unreachable("RegClassOrBank is either a const RegisterBank* or "<br>
- "a const TargetRegisterClass*");<br>
+ return nullptr;<br>
}<br>
<br>
const TargetRegisterClass &<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361918&r1=361917&r2=361918&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361918&r1=361917&r2=361918&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Tue May 28 19:49:59 2019<br>
@@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRe<br>
assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&<br>
"Arguments and return value types must match");<br>
<br>
- const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI);<br>
- if (RegRB.getID() != X86::GPRRegBankID)<br>
+ const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);<br>
+ if (!RegRB || RegRB->getID() != X86::GPRRegBankID)<br>
return false;<br>
<br>
const static unsigned NumTypes = 4; // i8, i16, i32, i64<br>
@@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRe<br>
const DivRemEntry &TypeEntry = *OpEntryIt;<br>
const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];<br>
<br>
- const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);<br>
+ const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);<br>
if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||<br>
!RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||<br>
!RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {<br>
<br>
<br>
_______________________________________________<br>
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<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><o:p></o:p></p>
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<p class="MsoNormal">-- <o:p></o:p></p>
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<p class="MsoNormal">~Craig<o:p></o:p></p>
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