<div dir="ltr">Hi Simon,<div><br></div><div>This revision is causing a fatal error in the backend. I've reported the details and a reproducer in <a href="https://bugs.llvm.org/show_bug.cgi?id=41619">https://bugs.llvm.org/show_bug.cgi?id=41619</a></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Apr 22, 2019 at 7:02 AM Simon Pilgrim via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: rksimon<br>
Date: Mon Apr 22 07:04:35 2019<br>
New Revision: 358887<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=358887&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=358887&view=rev</a><br>
Log:<br>
[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling<br>
<br>
This patch adds support for BigBitWidth -> SmallBitWidth bitcasts, splitting the DemandedBits/Elts accordingly.<br>
<br>
The AMDGPU backend needed an extra (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1) combine to encourage BFE creation, I investigated putting this in DAGCombine but it caused a lot of noise on other targets - some improvements, some regressions.<br>
<br>
The X86 changes are all definite wins.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D60462" rel="noreferrer" target="_blank">https://reviews.llvm.org/D60462</a><br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp<br>
llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll<br>
llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll<br>
llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll<br>
llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll<br>
llvm/trunk/test/CodeGen/X86/masked_store.ll<br>
llvm/trunk/test/CodeGen/X86/movmsk-cmp.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Apr 22 07:04:35 2019<br>
@@ -1471,12 +1471,36 @@ bool TargetLowering::SimplifyDemandedBit<br>
if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,<br>
KnownSrcBits, TLO, Depth + 1))<br>
return true;<br>
+ } else if ((NumSrcEltBits % BitWidth) == 0 &&<br>
+ TLO.DAG.getDataLayout().isLittleEndian()) {<br>
+ unsigned Scale = NumSrcEltBits / BitWidth;<br>
+ unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;<br>
+ APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);<br>
+ APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);<br>
+ for (unsigned i = 0; i != NumElts; ++i)<br>
+ if (DemandedElts[i]) {<br>
+ unsigned Offset = (i % Scale) * BitWidth;<br>
+ DemandedSrcBits.insertBits(DemandedBits, Offset);<br>
+ DemandedSrcElts.setBit(i / Scale);<br>
+ }<br>
+<br>
+ if (SrcVT.isVector()) {<br>
+ APInt KnownSrcUndef, KnownSrcZero;<br>
+ if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,<br>
+ KnownSrcZero, TLO, Depth + 1))<br>
+ return true;<br>
+ }<br>
+<br>
+ KnownBits KnownSrcBits;<br>
+ if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,<br>
+ KnownSrcBits, TLO, Depth + 1))<br>
+ return true;<br>
}<br>
<br>
// If this is a bitcast, let computeKnownBits handle it. Only do this on a<br>
// recursive call where Known may be useful to the caller.<br>
if (Depth > 0) {<br>
- Known = TLO.DAG.computeKnownBits(Op, Depth);<br>
+ Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);<br>
return false;<br>
}<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Mon Apr 22 07:04:35 2019<br>
@@ -3147,30 +3147,44 @@ SDValue AMDGPUTargetLowering::performSra<br>
<br>
SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,<br>
DAGCombinerInfo &DCI) const {<br>
- if (N->getValueType(0) != MVT::i64)<br>
- return SDValue();<br>
-<br>
- const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));<br>
+ auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));<br>
if (!RHS)<br>
return SDValue();<br>
<br>
+ EVT VT = N->getValueType(0);<br>
+ SDValue LHS = N->getOperand(0);<br>
unsigned ShiftAmt = RHS->getZExtValue();<br>
+ SelectionDAG &DAG = DCI.DAG;<br>
+ SDLoc SL(N);<br>
+<br>
+ // fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)<br>
+ // this improves the ability to match BFE patterns in isel.<br>
+ if (LHS.getOpcode() == ISD::AND) {<br>
+ if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {<br>
+ if (Mask->getAPIntValue().isShiftedMask() &&<br>
+ Mask->getAPIntValue().countTrailingZeros() == ShiftAmt) {<br>
+ return DAG.getNode(<br>
+ ISD::AND, SL, VT,<br>
+ DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),<br>
+ DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ if (VT != MVT::i64)<br>
+ return SDValue();<br>
+<br>
if (ShiftAmt < 32)<br>
return SDValue();<br>
<br>
// srl i64:x, C for C >= 32<br>
// =><br>
// build_pair (srl hi_32(x), C - 32), 0<br>
-<br>
- SelectionDAG &DAG = DCI.DAG;<br>
- SDLoc SL(N);<br>
-<br>
SDValue One = DAG.getConstant(1, SL, MVT::i32);<br>
SDValue Zero = DAG.getConstant(0, SL, MVT::i32);<br>
<br>
- SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));<br>
- SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,<br>
- VecOp, One);<br>
+ SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS);<br>
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One);<br>
<br>
SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);<br>
SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/store-weird-sizes.ll Mon Apr 22 07:04:35 2019<br>
@@ -86,8 +86,8 @@ define amdgpu_kernel void @local_store_i<br>
; GFX9-NEXT: v_mov_b32_e32 v2, s2<br>
; GFX9-NEXT: ds_write_b16 v1, v2 offset:4<br>
; GFX9-NEXT: s_waitcnt vmcnt(0)<br>
-; GFX9-NEXT: v_and_b32_e32 v0, 0x7f0000, v0<br>
-; GFX9-NEXT: ds_write_b8_d16_hi v1, v0 offset:6<br>
+; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 7<br>
+; GFX9-NEXT: ds_write_b8 v1, v0 offset:6<br>
; GFX9-NEXT: ds_write_b32 v1, v3<br>
; GFX9-NEXT: s_endpgm<br>
store i55 %arg, i55 addrspace(3)* %ptr, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.ll Mon Apr 22 07:04:35 2019<br>
@@ -448,22 +448,6 @@ define void @bitcast_8i32_store(i8* %p,<br>
define void @bitcast_4i64_store(i4* %p, <4 x i64> %a0) {<br>
; SSE2-SSSE3-LABEL: bitcast_4i64_store:<br>
; SSE2-SSSE3: # %bb.0:<br>
-; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]<br>
-; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm1<br>
-; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm3<br>
-; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm4<br>
-; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm4<br>
-; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]<br>
-; SSE2-SSSE3-NEXT: pand %xmm3, %xmm1<br>
-; SSE2-SSSE3-NEXT: por %xmm4, %xmm1<br>
-; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm0<br>
-; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-SSSE3-NEXT: pcmpeqd %xmm0, %xmm3<br>
-; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm2<br>
-; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]<br>
-; SSE2-SSSE3-NEXT: pand %xmm3, %xmm0<br>
-; SSE2-SSSE3-NEXT: por %xmm2, %xmm0<br>
; SSE2-SSSE3-NEXT: packssdw %xmm1, %xmm0<br>
; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax<br>
; SSE2-SSSE3-NEXT: movb %al, (%rdi)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll Mon Apr 22 07:04:35 2019<br>
@@ -609,15 +609,13 @@ define void @bitcast_8i64_store(i8* %p,<br>
;<br>
; AVX1-LABEL: bitcast_8i64_store:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: movb %al, (%rdi)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/dagcombine-cse.ll Mon Apr 22 07:04:35 2019<br>
@@ -14,18 +14,11 @@ define i32 @t(i8* %ref_frame_ptr, i32 %r<br>
;<br>
; X64-LABEL: t:<br>
; X64: ## %bb.0: ## %entry<br>
-; X64-NEXT: ## kill: def $edx killed $edx def $rdx<br>
-; X64-NEXT: ## kill: def $esi killed $esi def $rsi<br>
; X64-NEXT: imull %ecx, %esi<br>
-; X64-NEXT: leal (%rsi,%rdx), %eax<br>
-; X64-NEXT: cltq<br>
+; X64-NEXT: addl %edx, %esi<br>
+; X64-NEXT: movslq %esi, %rax<br>
; X64-NEXT: movl (%rdi,%rax), %eax<br>
-; X64-NEXT: leal 4(%rsi,%rdx), %ecx<br>
-; X64-NEXT: movslq %ecx, %rcx<br>
-; X64-NEXT: movzwl (%rdi,%rcx), %ecx<br>
-; X64-NEXT: shlq $32, %rcx<br>
-; X64-NEXT: orq %rax, %rcx<br>
-; X64-NEXT: movq %rcx, %xmm0<br>
+; X64-NEXT: movq %rax, %xmm0<br>
; X64-NEXT: movd %xmm0, %eax<br>
; X64-NEXT: retq<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/masked_store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked_store.ll?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked_store.ll?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/masked_store.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/masked_store.ll Mon Apr 22 07:04:35 2019<br>
@@ -36,25 +36,21 @@ define void @store_v1f64_v1i64(<1 x i64><br>
define void @store_v2f64_v2i64(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %val) {<br>
; SSE2-LABEL: store_v2f64_v2i64:<br>
; SSE2: ## %bb.0:<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]<br>
-; SSE2-NEXT: pxor %xmm3, %xmm0<br>
-; SSE2-NEXT: movdqa %xmm3, %xmm2<br>
-; SSE2-NEXT: pcmpgtd %xmm0, %xmm2<br>
-; SSE2-NEXT: pcmpeqd %xmm3, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>
-; SSE2-NEXT: movdqa %xmm0, %xmm4<br>
-; SSE2-NEXT: pand %xmm2, %xmm4<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]<br>
-; SSE2-NEXT: por %xmm3, %xmm4<br>
-; SSE2-NEXT: movd %xmm4, %eax<br>
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]<br>
+; SSE2-NEXT: pxor %xmm2, %xmm0<br>
+; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
+; SSE2-NEXT: pcmpgtd %xmm0, %xmm3<br>
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm0<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]<br>
+; SSE2-NEXT: pand %xmm3, %xmm2<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]<br>
+; SSE2-NEXT: por %xmm2, %xmm0<br>
+; SSE2-NEXT: movd %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB1_2<br>
; SSE2-NEXT: ## %bb.1: ## %cond.store<br>
; SSE2-NEXT: movlpd %xmm1, (%rdi)<br>
; SSE2-NEXT: LBB1_2: ## %else<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm2, %xmm0<br>
-; SSE2-NEXT: por %xmm3, %xmm0<br>
; SSE2-NEXT: pextrw $4, %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB1_4<br>
@@ -117,20 +113,16 @@ define void @store_v4f64_v4i64(<4 x i64><br>
; SSE2-NEXT: movdqa %xmm4, %xmm5<br>
; SSE2-NEXT: pcmpgtd %xmm0, %xmm5<br>
; SSE2-NEXT: pcmpeqd %xmm4, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>
-; SSE2-NEXT: movdqa %xmm0, %xmm7<br>
-; SSE2-NEXT: pand %xmm5, %xmm7<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]<br>
-; SSE2-NEXT: por %xmm6, %xmm7<br>
-; SSE2-NEXT: movd %xmm7, %eax<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]<br>
+; SSE2-NEXT: pand %xmm5, %xmm6<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]<br>
+; SSE2-NEXT: por %xmm6, %xmm0<br>
+; SSE2-NEXT: movd %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB2_2<br>
; SSE2-NEXT: ## %bb.1: ## %cond.store<br>
; SSE2-NEXT: movlpd %xmm2, (%rdi)<br>
; SSE2-NEXT: LBB2_2: ## %else<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm5, %xmm0<br>
-; SSE2-NEXT: por %xmm6, %xmm0<br>
; SSE2-NEXT: pextrw $4, %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB2_4<br>
@@ -140,10 +132,9 @@ define void @store_v4f64_v4i64(<4 x i64><br>
; SSE2-NEXT: pxor %xmm4, %xmm1<br>
; SSE2-NEXT: movdqa %xmm4, %xmm0<br>
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]<br>
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1<br>
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]<br>
-; SSE2-NEXT: pand %xmm2, %xmm1<br>
+; SSE2-NEXT: pand %xmm0, %xmm1<br>
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>
; SSE2-NEXT: por %xmm1, %xmm0<br>
; SSE2-NEXT: pextrw $0, %xmm0, %eax<br>
@@ -863,25 +854,21 @@ define void @store_v16f32_v16i32(<16 x f<br>
define void @store_v2i64_v2i64(<2 x i64> %trigger, <2 x i64>* %addr, <2 x i64> %val) {<br>
; SSE2-LABEL: store_v2i64_v2i64:<br>
; SSE2: ## %bb.0:<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]<br>
-; SSE2-NEXT: pxor %xmm3, %xmm0<br>
-; SSE2-NEXT: movdqa %xmm3, %xmm2<br>
-; SSE2-NEXT: pcmpgtd %xmm0, %xmm2<br>
-; SSE2-NEXT: pcmpeqd %xmm3, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>
-; SSE2-NEXT: movdqa %xmm0, %xmm4<br>
-; SSE2-NEXT: pand %xmm2, %xmm4<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]<br>
-; SSE2-NEXT: por %xmm3, %xmm4<br>
-; SSE2-NEXT: movd %xmm4, %eax<br>
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]<br>
+; SSE2-NEXT: pxor %xmm2, %xmm0<br>
+; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
+; SSE2-NEXT: pcmpgtd %xmm0, %xmm3<br>
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm0<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]<br>
+; SSE2-NEXT: pand %xmm3, %xmm2<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]<br>
+; SSE2-NEXT: por %xmm2, %xmm0<br>
+; SSE2-NEXT: movd %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB7_2<br>
; SSE2-NEXT: ## %bb.1: ## %cond.store<br>
; SSE2-NEXT: movq %xmm1, (%rdi)<br>
; SSE2-NEXT: LBB7_2: ## %else<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm2, %xmm0<br>
-; SSE2-NEXT: por %xmm3, %xmm0<br>
; SSE2-NEXT: pextrw $4, %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB7_4<br>
@@ -950,20 +937,16 @@ define void @store_v4i64_v4i64(<4 x i64><br>
; SSE2-NEXT: movdqa %xmm4, %xmm5<br>
; SSE2-NEXT: pcmpgtd %xmm0, %xmm5<br>
; SSE2-NEXT: pcmpeqd %xmm4, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>
-; SSE2-NEXT: movdqa %xmm0, %xmm7<br>
-; SSE2-NEXT: pand %xmm5, %xmm7<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]<br>
-; SSE2-NEXT: por %xmm6, %xmm7<br>
-; SSE2-NEXT: movd %xmm7, %eax<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]<br>
+; SSE2-NEXT: pand %xmm5, %xmm6<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]<br>
+; SSE2-NEXT: por %xmm6, %xmm0<br>
+; SSE2-NEXT: movd %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB8_2<br>
; SSE2-NEXT: ## %bb.1: ## %cond.store<br>
; SSE2-NEXT: movq %xmm2, (%rdi)<br>
; SSE2-NEXT: LBB8_2: ## %else<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm5, %xmm0<br>
-; SSE2-NEXT: por %xmm6, %xmm0<br>
; SSE2-NEXT: pextrw $4, %xmm0, %eax<br>
; SSE2-NEXT: testb $1, %al<br>
; SSE2-NEXT: je LBB8_4<br>
@@ -974,10 +957,9 @@ define void @store_v4i64_v4i64(<4 x i64><br>
; SSE2-NEXT: pxor %xmm4, %xmm1<br>
; SSE2-NEXT: movdqa %xmm4, %xmm0<br>
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]<br>
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1<br>
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]<br>
-; SSE2-NEXT: pand %xmm2, %xmm1<br>
+; SSE2-NEXT: pand %xmm0, %xmm1<br>
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]<br>
; SSE2-NEXT: por %xmm1, %xmm0<br>
; SSE2-NEXT: pextrw $0, %xmm0, %eax<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/movmsk-cmp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movmsk-cmp.ll?rev=358887&r1=358886&r2=358887&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movmsk-cmp.ll?rev=358887&r1=358886&r2=358887&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/movmsk-cmp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/movmsk-cmp.ll Mon Apr 22 07:04:35 2019<br>
@@ -929,22 +929,6 @@ define i1 @allzeros_v16i32_sign(<16 x i3<br>
define i1 @allones_v4i64_sign(<4 x i64> %arg) {<br>
; SSE2-LABEL: allones_v4i64_sign:<br>
; SSE2: # %bb.0:<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]<br>
-; SSE2-NEXT: pxor %xmm2, %xmm1<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-NEXT: pcmpeqd %xmm1, %xmm3<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm4<br>
-; SSE2-NEXT: pcmpgtd %xmm1, %xmm4<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm3, %xmm1<br>
-; SSE2-NEXT: por %xmm4, %xmm1<br>
-; SSE2-NEXT: pxor %xmm2, %xmm0<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm3<br>
-; SSE2-NEXT: pcmpgtd %xmm0, %xmm2<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm3, %xmm0<br>
-; SSE2-NEXT: por %xmm2, %xmm0<br>
; SSE2-NEXT: packssdw %xmm1, %xmm0<br>
; SSE2-NEXT: movmskps %xmm0, %eax<br>
; SSE2-NEXT: cmpb $15, %al<br>
@@ -989,22 +973,6 @@ define i1 @allones_v4i64_sign(<4 x i64><br>
define i1 @allzeros_v4i64_sign(<4 x i64> %arg) {<br>
; SSE2-LABEL: allzeros_v4i64_sign:<br>
; SSE2: # %bb.0:<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]<br>
-; SSE2-NEXT: pxor %xmm2, %xmm1<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-NEXT: pcmpeqd %xmm1, %xmm3<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm4<br>
-; SSE2-NEXT: pcmpgtd %xmm1, %xmm4<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm3, %xmm1<br>
-; SSE2-NEXT: por %xmm4, %xmm1<br>
-; SSE2-NEXT: pxor %xmm2, %xmm0<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm3<br>
-; SSE2-NEXT: pcmpgtd %xmm0, %xmm2<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm3, %xmm0<br>
-; SSE2-NEXT: por %xmm2, %xmm0<br>
; SSE2-NEXT: packssdw %xmm1, %xmm0<br>
; SSE2-NEXT: movmskps %xmm0, %eax<br>
; SSE2-NEXT: testb %al, %al<br>
@@ -1095,15 +1063,13 @@ define i1 @allones_v8i64_sign(<8 x i64><br>
;<br>
; AVX1-LABEL: allones_v8i64_sign:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: cmpb $-1, %al<br>
@@ -1198,15 +1164,13 @@ define i1 @allzeros_v8i64_sign(<8 x i64><br>
;<br>
; AVX1-LABEL: allzeros_v8i64_sign:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: testb %al, %al<br>
@@ -2539,19 +2503,17 @@ define i1 @allones_v8i64_and1(<8 x i64><br>
;<br>
; AVX1-LABEL: allones_v8i64_and1:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpsllq $63, %xmm0, %xmm0<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: cmpb $-1, %al<br>
@@ -2615,19 +2577,17 @@ define i1 @allzeros_v8i64_and1(<8 x i64><br>
;<br>
; AVX1-LABEL: allzeros_v8i64_and1:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpsllq $63, %xmm0, %xmm0<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: testb %al, %al<br>
@@ -3962,19 +3922,17 @@ define i1 @allones_v8i64_and4(<8 x i64><br>
;<br>
; AVX1-LABEL: allones_v8i64_and4:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpsllq $61, %xmm0, %xmm0<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: cmpb $-1, %al<br>
@@ -4038,19 +3996,17 @@ define i1 @allzeros_v8i64_and4(<8 x i64><br>
;<br>
; AVX1-LABEL: allzeros_v8i64_and4:<br>
; AVX1: # %bb.0:<br>
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
-; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2<br>
-; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
-; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1<br>
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1<br>
-; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2<br>
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3<br>
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2<br>
; AVX1-NEXT: vpsllq $61, %xmm0, %xmm0<br>
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0<br>
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2<br>
+; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2<br>
+; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: vmovmskps %ymm0, %eax<br>
; AVX1-NEXT: testb %al, %al<br>
@@ -4170,22 +4126,6 @@ define i32 @movmskps(<4 x float> %x) {<br>
define i32 @movmskpd256(<4 x double> %x) {<br>
; SSE2-LABEL: movmskpd256:<br>
; SSE2: # %bb.0:<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]<br>
-; SSE2-NEXT: pxor %xmm2, %xmm1<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-NEXT: pcmpeqd %xmm1, %xmm3<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm4<br>
-; SSE2-NEXT: pcmpgtd %xmm1, %xmm4<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm3, %xmm1<br>
-; SSE2-NEXT: por %xmm4, %xmm1<br>
-; SSE2-NEXT: pxor %xmm2, %xmm0<br>
-; SSE2-NEXT: movdqa %xmm2, %xmm3<br>
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm3<br>
-; SSE2-NEXT: pcmpgtd %xmm0, %xmm2<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]<br>
-; SSE2-NEXT: pand %xmm3, %xmm0<br>
-; SSE2-NEXT: por %xmm2, %xmm0<br>
; SSE2-NEXT: packssdw %xmm1, %xmm0<br>
; SSE2-NEXT: movmskps %xmm0, %eax<br>
; SSE2-NEXT: retq<br>
<br>
<br>
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</blockquote></div>