<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div><br class=""><blockquote type="cite" class=""><div class=""><br style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><br class=""> bool operator<(const LiveInterval& other) const {<br class=""> const SlotIndex &thisIndex = beginIndex();<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=357032&r1=357031&r2=357032&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=357032&r1=357031&r2=357032&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Mar 26 14:27:15 2019<br class="">@@ -879,8 +879,53 @@ void LiveInterval::clearSubRanges() {<br class=""> SubRanges = nullptr;<br class="">}<br class=""><br class="">-void LiveInterval::refineSubRanges(BumpPtrAllocator &Allocator,<br class="">- LaneBitmask LaneMask, std::function<void(LiveInterval::SubRange&)> Apply) {<br class="">+/// For each VNI in \p SR, check whether or not that value defines part<br class="">+/// of the mask describe by \p LaneMask and if not, remove that value<br class="">+/// from \p SR.<br class="">+static void stripValuesNotDefiningMask(unsigned Reg, LiveInterval::SubRange &SR,<br class="">+ LaneBitmask LaneMask,<br class="">+ const SlotIndexes &Indexes,<br class="">+ const TargetRegisterInfo &TRI) {<br class="">+ // Phys reg should not be tracked at subreg level.<br class="">+ // Same for noreg (Reg == 0).<br class="">+ if (!TargetRegisterInfo::isVirtualRegister(Reg) || !Reg)<br class="">+ return;<br class="">+ // Remove the values that don't define those lanes.<br class="">+ SmallVector<VNInfo *, 8> ToBeRemoved;<br class="">+ for (VNInfo *VNI : SR.valnos) {<br class="">+ if (VNI->isUnused())<br class="">+ continue;<br class="">+ // PHI definitions don't have MI attached, so there is nothing<br class="">+ // we can use to strip the VNI.<br class="">+ if (VNI->isPHIDef())<br class="">+ continue;<br class="">+ const MachineInstr *MI = Indexes.getInstructionFromIndex(VNI->def);<br class="">+ assert(MI && "Cannot find the definition of a value");<br class="">+ bool hasDef = false;<br class="">+ for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {<br class="">+ if (!MOI->isReg() || !MOI->isDef())<br class="">+ continue;<br class="">+ if (MOI->getReg() != Reg)<br class="">+ continue;<br class="">+ if ((TRI.getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())<br class="">+ continue;<br class="">+ hasDef = true;<br class="">+ break;<br class="">+ }<br class="">+<br class="">+ if (!hasDef)<br class="">+ ToBeRemoved.push_back(VNI);<br class="">+ }<br class="">+ for (VNInfo *VNI : ToBeRemoved)<br class="">+ SR.removeValNo(VNI);<br class="">+<br class="">+ assert(!SR.empty() && "At least one value should be defined by this mask");<br class="">+}<br class="">+<br class="">+void LiveInterval::refineSubRanges(<br class="">+ BumpPtrAllocator &Allocator, LaneBitmask LaneMask,<br class="">+ std::function<void(LiveInterval::SubRange &)> Apply,<br class="">+ const SlotIndexes &Indexes, const TargetRegisterInfo &TRI) {<br class=""> LaneBitmask ToApply = LaneMask;<br class=""> for (SubRange &SR : subranges()) {<br class=""> LaneBitmask SRMask = SR.LaneMask;<br class="">@@ -898,6 +943,10 @@ void LiveInterval::refineSubRanges(BumpP<br class=""> SR.LaneMask = SRMask & ~Matching;<br class=""> // Create a new subrange for the matching part<br class=""> MatchingRange = createSubRangeFrom(Allocator, Matching, SR);<br class="">+ // Now that the subrange is split in half, make sure we<br class="">+ // only keep in the subranges the VNIs that touch the related half.<br class="">+ stripValuesNotDefiningMask(reg, *MatchingRange, Matching, Indexes, TRI);<br class="">+ stripValuesNotDefiningMask(reg, SR, SR.LaneMask, Indexes, TRI);<br class=""> }<br class=""> Apply(*MatchingRange);<br class=""> ToApply &= ~Matching;<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=357032&r1=357031&r2=357032&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=357032&r1=357031&r2=357032&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Tue Mar 26 14:27:15 2019<br class="">@@ -95,10 +95,11 @@ void LiveRangeCalc::calculate(LiveInterv<br class=""> }<br class=""><br class=""> LI.refineSubRanges(*Alloc, SubMask,<br class="">- [&MO, this](LiveInterval::SubRange &SR) {<br class="">- if (MO.isDef())<br class="">- createDeadDef(*Indexes, *Alloc, SR, MO);<br class="">- });<br class="">+ [&MO, this](LiveInterval::SubRange &SR) {<br class="">+ if (MO.isDef())<br class="">+ createDeadDef(*Indexes, *Alloc, SR, MO);<br class="">+ },<br class="">+ *Indexes, TRI);<br class=""> }<br class=""><br class=""> // Create the def in the main liverange. We do not have to do this if<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=357032&r1=357031&r2=357032&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=357032&r1=357031&r2=357032&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Mar 26 14:27:15 2019<br class="">@@ -924,23 +924,25 @@ RegisterCoalescer::removeCopyByCommuting<br class=""> }<br class=""> SlotIndex AIdx = CopyIdx.getRegSlot(true);<br class=""> LaneBitmask MaskA;<br class="">+ const SlotIndexes &Indexes = *LIS->getSlotIndexes();<br class=""> for (LiveInterval::SubRange &SA : IntA.subranges()) {<br class=""> VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);<br class=""> assert(ASubValNo != nullptr);<br class=""> MaskA |= SA.LaneMask;<br class=""><br class="">- IntB.refineSubRanges(Allocator, SA.LaneMask,<br class="">- [&Allocator,&SA,CopyIdx,ASubValNo,&ShrinkB]<br class="">- (LiveInterval::SubRange &SR) {<br class="">- VNInfo *BSubValNo = SR.empty()<br class="">- ? SR.getNextValue(CopyIdx, Allocator)<br class="">- : SR.getVNInfoAt(CopyIdx);<br class="">- assert(BSubValNo != nullptr);<br class="">- auto P = addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);<br class="">- ShrinkB |= P.second;<br class="">- if (P.first)<br class="">- BSubValNo->def = ASubValNo->def;<br class="">- });<br class="">+ IntB.refineSubRanges(<br class="">+ Allocator, SA.LaneMask,<br class="">+ [&Allocator, &SA, CopyIdx, ASubValNo,<br class="">+ &ShrinkB](LiveInterval::SubRange &SR) {<br class="">+ VNInfo *BSubValNo = SR.empty() ? SR.getNextValue(CopyIdx, Allocator)<br class="">+ : SR.getVNInfoAt(CopyIdx);<br class="">+ assert(BSubValNo != nullptr);<br class="">+ auto P = addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);<br class="">+ ShrinkB |= P.second;<br class="">+ if (P.first)<br class="">+ BSubValNo->def = ASubValNo->def;<br class="">+ },<br class="">+ Indexes, *TRI);<br class=""> }<br class=""> // Go over all subranges of IntB that have not been covered by IntA,<br class=""> // and delete the segments starting at CopyIdx. This can happen if<br class="">@@ -3262,16 +3264,18 @@ void RegisterCoalescer::mergeSubRangeInt<br class=""> LaneBitmask LaneMask,<br class=""> CoalescerPair &CP) {<br class=""> BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();<br class="">- LI.refineSubRanges(Allocator, LaneMask,<br class="">- [this,&Allocator,&ToMerge,&CP](LiveInterval::SubRange &SR) {<br class="">- if (SR.empty()) {<br class="">- SR.assign(ToMerge, Allocator);<br class="">- } else {<br class="">- // joinSubRegRange() destroys the merged range, so we need a copy.<br class="">- LiveRange RangeCopy(ToMerge, Allocator);<br class="">- joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);<br class="">- }<br class="">- });<br class="">+ LI.refineSubRanges(<br class="">+ Allocator, LaneMask,<br class="">+ [this, &Allocator, &ToMerge, &CP](LiveInterval::SubRange &SR) {<br class="">+ if (SR.empty()) {<br class="">+ SR.assign(ToMerge, Allocator);<br class="">+ } else {<br class="">+ // joinSubRegRange() destroys the merged range, so we need a copy.<br class="">+ LiveRange RangeCopy(ToMerge, Allocator);<br class="">+ joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);<br class="">+ }<br class="">+ },<br class="">+ *LIS->getSlotIndexes(), *TRI);<br class="">}<br class=""><br class="">bool RegisterCoalescer::isHighCostLiveInterval(LiveInterval &LI) {<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=357032&r1=357031&r2=357032&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=357032&r1=357031&r2=357032&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Mar 26 14:27:15 2019<br class="">@@ -520,17 +520,18 @@ SlotIndex SplitEditor::buildSingleSubReg<br class=""> .addReg(FromReg, 0, SubIdx);<br class=""><br class=""> BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();<br class="">+ SlotIndexes &Indexes = *LIS.getSlotIndexes();<br class=""> if (FirstCopy) {<br class="">- SlotIndexes &Indexes = *LIS.getSlotIndexes();<br class=""> Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();<br class=""> } else {<br class=""> CopyMI->bundleWithPred();<br class=""> }<br class=""> LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubIdx);<br class=""> DestLI.refineSubRanges(Allocator, LaneMask,<br class="">- [Def, &Allocator](LiveInterval::SubRange& SR) {<br class="">- SR.createDeadDef(Def, Allocator);<br class="">- });<br class="">+ [Def, &Allocator](LiveInterval::SubRange &SR) {<br class="">+ SR.createDeadDef(Def, Allocator);<br class="">+ },<br class="">+ Indexes, TRI);<br class=""> return Def;<br class="">}<br class=""><br class=""><br class="">Added: llvm/trunk/test/CodeGen/SystemZ/regcoal-subranges-update.mir<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/regcoal-subranges-update.mir?rev=357032&view=auto" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/regcoal-subranges-update.mir?rev=357032&view=auto</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/SystemZ/regcoal-subranges-update.mir (added)<br class="">+++ llvm/trunk/test/CodeGen/SystemZ/regcoal-subranges-update.mir Tue Mar 26 14:27:15 2019<br class="">@@ -0,0 +1,94 @@<br class="">+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br class="">+# RUN: llc -mtriple s390x-ibm-linux -mcpu=z13 -systemz-subreg-liveness -verify-machineinstrs -start-before simple-register-coalescing -stop-after greedy -o - %s | FileCheck %s<br class="">+<br class="">+# Check that when we split the live-range with several active lanes<br class="">+# as part of the live-range update, we correctly eliminate the VNI from<br class="">+# the relevant part.<br class="">+#<br class="">+# In this specific test, the register coalescer will:<br class="">+# 1. Merge %0 with %1, creating a live-range for the full value subreg_l32 + subreg_h32<br class="">+# (actually %0 gets merge with %1 via rematerialization, and technically %0 and %1<br class="">+# remain two different live-ranges.)<br class="">+# 2. Merge %2 with %1 triggering a split into the subreg_l32 + subreg_h32 ranges, since<br class="">+# %2 only touches subreg_l32. As part of the split the subrange covering subreg_h32<br class="">+# must contain only the VNI for the high part (i.e., the one tied with the remaaat of %0).<br class="">+# This used to be broken and trigger a machine verifier error, because we were not<br class="">+# clearing the dead value w.r.t. lanes when doing the splitting. I.e., we were ending<br class="">+# with a subrange referring a value that did not define that lane.<br class="">+#<br class="">+# PR40835<br class="">+---<br class="">+name: main<br class="">+tracksRegLiveness: true<br class="">+body: |<br class="">+ bb.0:<br class="">+<br class="">+ ; CHECK-LABEL: name: main<br class="">+ ; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43<br class="">+ ; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43<br class="">+ ; CHECK: [[LGHI1]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32<br class="">+ ; CHECK: [[LGHI1]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc<br class="">+ ; CHECK: undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32<br class="">+ ; CHECK: [[DLGR:%[0-9]+]]:gr128bit = DLGR [[DLGR]], [[LGHI]]<br class="">+ ; CHECK: Return implicit [[DLGR]]<br class="">+ %0:gr64bit = LGHI 43<br class="">+ %1:gr32bit = COPY %0.subreg_l32<br class="">+ %1:gr32bit = MSR %1, %1<br class="">+ %2:gr32bit = COPY killed %1<br class="">+ %2:gr32bit = AHIMux killed %2, 9, implicit-def dead $cc<br class="">+ undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit killed %2<br class="">+ %3:gr128bit = DLGR %3:gr128bit, killed %0<br class="">+ Return implicit killed %3<br class="">+<br class="">+...<br class="">+<br class="">+# Make sure the compiler does not choke on VNIs that don't<br class="">+# an explicit MI as definition.<br class="">+# In that specific example, this is the PHI not explicitly<br class="">+# represented for the value carried by %7.<br class="">+---<br class="">+name: segfault<br class="">+tracksRegLiveness: true<br class="">+liveins: []<br class="">+body: |<br class="">+ ; CHECK-LABEL: name: segfault<br class="">+ ; CHECK: bb.0:<br class="">+ ; CHECK: successors: %bb.1(0x80000000)<br class="">+ ; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0<br class="">+ ; CHECK: bb.1:<br class="">+ ; CHECK: successors: %bb.1(0x80000000)<br class="">+ ; CHECK: ADJCALLSTACKDOWN 0, 0<br class="">+ ; CHECK: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32<br class="">+ ; CHECK: $r2d = LGHI 123<br class="">+ ; CHECK: $r3d = LGHI 0<br class="">+ ; CHECK: $r4d = LGHI 0<br class="">+ ; CHECK: $r5d = COPY [[LGFR]]<br class="">+ ; CHECK: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc<br class="">+ ; CHECK: ADJCALLSTACKUP 0, 0<br class="">+ ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg<br class="">+ ; CHECK: J %bb.1<br class="">+ bb.0:<br class="">+ successors: %bb.1(0x80000000)<br class="">+<br class="">+ %2:gr64bit = LGHI 0<br class="">+ %5:gr64bit = LGHI 123<br class="">+ %7:addr64bit = COPY %2<br class="">+<br class="">+ bb.1:<br class="">+ successors: %bb.1(0x80000000)<br class="">+<br class="">+ %0:addr64bit = COPY killed %7<br class="">+ ADJCALLSTACKDOWN 0, 0<br class="">+ %3:gr32bit = COPY %0.subreg_l32<br class="">+ %4:gr64bit = LGFR killed %3<br class="">+ $r2d = COPY %5<br class="">+ $r3d = COPY %2<br class="">+ $r4d = COPY %2<br class="">+ $r5d = COPY killed %4<br class="">+ KILL killed $r2d, killed $r3d, killed $r4d, killed $r5d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc<br class="">+ ADJCALLSTACKUP 0, 0<br class="">+ %1:gr64bit = nuw nsw LA killed %0, 1, $noreg<br class="">+ %7:addr64bit = COPY killed %1<br class="">+ J %bb.1<br class="">+<br class="">+...<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></blockquote><span style="caret-color: rgb(0, 0, 0); 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