<div dir="ltr"><div dir="ltr">Hello Amara,<br><br>This commit added broken tests to the builder:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/16459">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/16459</a><br>. . .<br>Failing Tests (9):<br> LLVM :: CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir<br> LLVM :: CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir<br> LLVM :: CodeGen/AArch64/GlobalISel/select-insert-extract.mir<br> LLVM :: CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir<br> LLVM :: CodeGen/AArch64/GlobalISel/select-unmerge.mir<br> LLVM :: CodeGen/AArch64/arm64-rev.ll<br> LLVM :: CodeGen/AArch64/arm64-vfloatintrinsics.ll<br> LLVM :: CodeGen/AArch64/f16-instructions.ll<br> LLVM :: CodeGen/AArch64/sincospow-vector-expansion.ll<br><br>Please have a look?<br>The builder was already red and did not send any notifications.<br><br>Thanks<br><br>Galina<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Mar 18, 2019 at 12:18 PM Amara Emerson via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: aemerson<br>
Date: Mon Mar 18 12:20:10 2019<br>
New Revision: 356396<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=356396&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=356396&view=rev</a><br>
Log:<br>
Revert r356304: remove subreg parameter from MachineIRBuilder::buildCopy()<br>
<br>
After review comments, it was preferred to not teach MachineIRBuilder about<br>
non-generic instructions beyond using buildInstr().<br>
<br>
For AArch64 I've changed the buildCopy() calls to buildInstr() + a<br>
separate addReg() call.<br>
<br>
This also relaxes the MachineIRBuilder's COPY checking more because it may<br>
not always have a SrcOp given to it.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h<br>
llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=356396&r1=356395&r2=356396&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=356396&r1=356395&r2=356396&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Mon Mar 18 12:20:10 2019<br>
@@ -640,8 +640,7 @@ public:<br>
/// \pre setBasicBlock or setMI must have been called.<br>
///<br>
/// \return a MachineInstrBuilder for the newly created instruction.<br>
- MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op,<br>
- unsigned Subreg = 0);<br>
+ MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);<br>
<br>
/// Build and insert `Res = G_LOAD Addr, MMO`.<br>
///<br>
<br>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=356396&r1=356395&r2=356396&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=356396&r1=356395&r2=356396&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Mon Mar 18 12:20:10 2019<br>
@@ -242,11 +242,8 @@ MachineInstrBuilder MachineIRBuilder::bu<br>
}<br>
<br>
MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,<br>
- const SrcOp &Op,<br>
- unsigned Subreg) {<br>
- auto Copy = buildInstr(TargetOpcode::COPY, Res, Op);<br>
- Copy->getOperand(1).setSubReg(Subreg);<br>
- return Copy;<br>
+ const SrcOp &Op) {<br>
+ return buildInstr(TargetOpcode::COPY, Res, Op);<br>
}<br>
<br>
MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,<br>
@@ -916,6 +913,9 @@ MachineInstrBuilder MachineIRBuilder::bu<br>
case TargetOpcode::COPY:<br>
assert(DstOps.size() == 1 && "Invalid Dst");<br>
assert(SrcOps.size() == 1 && "Invalid Srcs");<br>
+ assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||<br>
+ SrcOps[0].getLLTTy(*getMRI()) == LLT() ||<br>
+ DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));<br>
break;<br>
case TargetOpcode::G_FCMP:<br>
case TargetOpcode::G_ICMP: {<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=356396&r1=356395&r2=356396&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=356396&r1=356395&r2=356396&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Mar 18 12:20:10 2019<br>
@@ -478,7 +478,8 @@ static bool selectSubregisterCopy(Machin<br>
unsigned SubReg) {<br>
MachineIRBuilder MIB(I);<br>
auto Copy = MIB.buildCopy({From}, {SrcReg});<br>
- auto SubRegCopy = MIB.buildCopy({To}, {Copy}, SubReg);<br>
+ auto SubRegCopy = MIB.buildInstr(TargetOpcode::COPY, {To}, {})<br>
+ .addReg(Copy.getReg(0), 0, SubReg);<br>
MachineOperand &RegOp = I.getOperand(1);<br>
RegOp.setReg(SubRegCopy.getReg(0));<br>
<br>
@@ -1104,7 +1105,8 @@ bool AArch64InstructionSelector::select(<br>
<br>
unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));<br>
MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator()));<br>
- MIB.buildCopy({I.getOperand(0).getReg()}, {DstReg}, AArch64::sub_32);<br>
+ MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})<br>
+ .addReg(DstReg, 0, AArch64::sub_32);<br>
RBI.constrainGenericRegister(I.getOperand(0).getReg(),<br>
AArch64::GPR32RegClass, MRI);<br>
I.getOperand(0).setReg(DstReg);<br>
@@ -1938,7 +1940,8 @@ MachineInstr *AArch64InstructionSelector<br>
DstReg = MRI.createVirtualRegister(DstRC);<br>
// If the lane index is 0, we just use a subregister COPY.<br>
if (LaneIdx == 0) {<br>
- auto Copy = MIRBuilder.buildCopy({*DstReg}, {VecReg}, ExtractSubReg);<br>
+ auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {*DstReg}, {})<br>
+ .addReg(VecReg, 0, ExtractSubReg);<br>
RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);<br>
return &*Copy;<br>
}<br>
@@ -2115,7 +2118,8 @@ bool AArch64InstructionSelector::selectU<br>
//<br>
// Perform the first copy separately as a subregister copy.<br>
unsigned CopyTo = I.getOperand(0).getReg();<br>
- auto FirstCopy = MIB.buildCopy({CopyTo}, {InsertRegs[0]}, ExtractSubReg);<br>
+ auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {})<br>
+ .addReg(InsertRegs[0], 0, ExtractSubReg);<br>
constrainSelectedInstRegOperands(*FirstCopy, TII, TRI, RBI);<br>
<br>
// Now, perform the remaining copies as vector lane copies.<br>
@@ -2388,7 +2392,9 @@ bool AArch64InstructionSelector::selectS<br>
constrainSelectedInstRegOperands(*TBL1, TII, TRI, RBI);<br>
<br>
auto Copy =<br>
- MIRBuilder.buildCopy({I.getOperand(0).getReg()}, {TBL1}, AArch64::dsub);<br>
+ MIRBuilder<br>
+ .buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})<br>
+ .addReg(TBL1.getReg(0), 0, AArch64::dsub);<br>
RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);<br>
I.eraseFromParent();<br>
return true;<br>
@@ -2538,7 +2544,8 @@ bool AArch64InstructionSelector::selectB<br>
unsigned Reg = MRI.createVirtualRegister(RC);<br>
unsigned DstReg = I.getOperand(0).getReg();<br>
<br>
- MIRBuilder.buildCopy({DstReg}, {DstVec}, SubReg);<br>
+ MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})<br>
+ .addReg(DstVec, 0, SubReg);<br>
MachineOperand &RegOp = I.getOperand(1);<br>
RegOp.setReg(Reg);<br>
RBI.constrainGenericRegister(DstReg, *RC, MRI);<br>
<br>
<br>
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</blockquote></div>