<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">r356394 should have fixed this<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Mar 18, 2019, at 3:34 PM, Galina Kistanova via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div dir="ltr" class="">Hello Matt,<br class=""><br class="">This commit added broken tests to the builder:<br class=""><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/16397" class="">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/16397</a><br class="">. . .<br class="">Failing Tests (19):<br class="">    . . .<br class="">    LLVM :: CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir<br class="">    LLVM :: CodeGen/MIR/AMDGPU/machine-function-info.ll<br class="">    . . .<br class="">Please have a look?<br class="">The builder was already red and did not send any notifications.<br class=""><br class="">Thanks<br class=""><br class="">Galina<br class=""></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Mar 14, 2019 at 3:53 PM Matt Arsenault via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: arsenm<br class="">
Date: Thu Mar 14 15:54:43 2019<br class="">
New Revision: 356215<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=356215&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=356215&view=rev</a><br class="">
Log:<br class="">
MIR: Allow targets to serialize MachineFunctionInfo<br class="">
<br class="">
This has been a very painful missing feature that has made producing<br class="">
reduced testcases difficult. In particular the various registers<br class="">
determined for stack access during function lowering were necessary to<br class="">
avoid undefined register errors in a large percentage of<br class="">
cases. Implement a subset of the important fields that need to be<br class="">
preserved for AMDGPU.<br class="">
<br class="">
Most of the changes are to support targets parsing register fields and<br class="">
properly reporting errors. The biggest sort-of bug remaining is for<br class="">
fields that can be initialized from the IR section will be overwritten<br class="">
by a default initialized machineFunctionInfo section. Another<br class="">
remaining bug is the machineFunctionInfo section is still printed even<br class="">
if empty.<br class="">
<br class="">
Added:<br class="">
    llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h<br class="">
      - copied, changed from r356207, llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir<br class="">
    llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir<br class="">
Removed:<br class="">
    llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br class="">
Modified:<br class="">
    llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br class="">
    llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h<br class="">
    llvm/trunk/include/llvm/Target/TargetMachine.h<br class="">
    llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br class="">
    llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br class="">
    llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br class="">
    llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br class="">
    llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h<br class="">
    llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br class="">
    llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br class="">
    llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp<br class="">
    llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h<br class="">
    llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir<br class="">
    llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir<br class="">
    llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir<br class="">
    llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir<br class="">
    llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir<br class="">
    llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir<br class="">
<br class="">
Copied: llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h (from r356207, llvm/trunk/lib/CodeGen/MIRParser/MIParser.h)<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h?p2=llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h&p1=llvm/trunk/lib/CodeGen/MIRParser/MIParser.h&r1=356207&r2=356215&rev=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h?p2=llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h&p1=llvm/trunk/lib/CodeGen/MIRParser/MIParser.h&r1=356207&r2=356215&rev=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h Thu Mar 14 15:54:43 2019<br class="">
@@ -164,8 +164,8 @@ struct PerFunctionMIParsingState {<br class="">
   PerTargetMIParsingState &Target;<br class="">
<br class="">
   DenseMap<unsigned, MachineBasicBlock *> MBBSlots;<br class="">
-  DenseMap<unsigned, VRegInfo*> VRegInfos;<br class="">
-  StringMap<VRegInfo*> VRegInfosNamed;<br class="">
+  DenseMap<unsigned, VRegInfo *> VRegInfos;<br class="">
+  StringMap<VRegInfo *> VRegInfosNamed;<br class="">
   DenseMap<unsigned, int> FixedStackObjectSlots;<br class="">
   DenseMap<unsigned, int> StackObjectSlots;<br class="">
   DenseMap<unsigned, unsigned> ConstantPoolSlots;<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Thu Mar 14 15:54:43 2019<br class="">
@@ -36,6 +36,7 @@ struct StringValue {<br class="">
<br class="">
   StringValue() = default;<br class="">
   StringValue(std::string Value) : Value(std::move(Value)) {}<br class="">
+  StringValue(const char Val[]) : Value(Val) {}<br class="">
<br class="">
   bool operator==(const StringValue &Other) const {<br class="">
     return Value == Other.Value;<br class="">
@@ -482,6 +483,20 @@ template <> struct MappingTraits<Machine<br class="">
   }<br class="">
 };<br class="">
<br class="">
+/// Targets should override this in a way that mirrors the implementation of<br class="">
+/// llvm::MachineFunctionInfo.<br class="">
+struct MachineFunctionInfo {<br class="">
+  virtual ~MachineFunctionInfo() {}<br class="">
+  virtual void mappingImpl(IO &YamlIO) {}<br class="">
+};<br class="">
+<br class="">
+template <> struct MappingTraits<std::unique_ptr<MachineFunctionInfo>> {<br class="">
+  static void mapping(IO &YamlIO, std::unique_ptr<MachineFunctionInfo> &MFI) {<br class="">
+    if (MFI)<br class="">
+      MFI->mappingImpl(YamlIO);<br class="">
+  }<br class="">
+};<br class="">
+<br class="">
 struct MachineFunction {<br class="">
   StringRef Name;<br class="">
   unsigned Alignment = 0;<br class="">
@@ -503,6 +518,7 @@ struct MachineFunction {<br class="">
   std::vector<FixedMachineStackObject> FixedStackObjects;<br class="">
   std::vector<MachineStackObject> StackObjects;<br class="">
   std::vector<MachineConstantPoolValue> Constants; /// Constant pool.<br class="">
+  std::unique_ptr<MachineFunctionInfo> MachineFuncInfo;<br class="">
   MachineJumpTable JumpTableInfo;<br class="">
   BlockStringValue Body;<br class="">
 };<br class="">
@@ -531,6 +547,7 @@ template <> struct MappingTraits<Machine<br class="">
                        std::vector<MachineStackObject>());<br class="">
     YamlIO.mapOptional("constants", MF.Constants,<br class="">
                        std::vector<MachineConstantPoolValue>());<br class="">
+    YamlIO.mapOptional("machineFunctionInfo", MF.MachineFuncInfo);<br class="">
     if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())<br class="">
       YamlIO.mapOptional("jumpTable", MF.JumpTableInfo, MachineJumpTable());<br class="">
     YamlIO.mapOptional("body", MF.Body, BlockStringValue());<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Thu Mar 14 15:54:43 2019<br class="">
@@ -150,6 +150,8 @@ public:<br class="">
   bool doInitialization(Module &) override;<br class="">
   bool doFinalization(Module &) override;<br class="">
<br class="">
+  const LLVMTargetMachine &getTarget() const { return TM; }<br class="">
+<br class="">
   const MCContext &getContext() const { return Context; }<br class="">
   MCContext &getContext() { return Context; }<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/Target/TargetMachine.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)<br class="">
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Mar 14 15:54:43 2019<br class="">
@@ -35,6 +35,9 @@ class MCSubtargetInfo;<br class="">
 class MCSymbol;<br class="">
 class raw_pwrite_stream;<br class="">
 class PassManagerBuilder;<br class="">
+struct PerFunctionMIParsingState;<br class="">
+class SMDiagnostic;<br class="">
+class SMRange;<br class="">
 class Target;<br class="">
 class TargetIntrinsicInfo;<br class="">
 class TargetIRAnalysis;<br class="">
@@ -49,6 +52,10 @@ class PassManagerBase;<br class="">
 }<br class="">
 using legacy::PassManagerBase;<br class="">
<br class="">
+namespace yaml {<br class="">
+struct MachineFunctionInfo;<br class="">
+}<br class="">
+<br class="">
 //===----------------------------------------------------------------------===//<br class="">
 ///<br class="">
 /// Primary interface to the complete machine description for the target<br class="">
@@ -114,6 +121,27 @@ public:<br class="">
     return nullptr;<br class="">
   }<br class="">
<br class="">
+  /// Allocate and return a default initialized instance of the YAML<br class="">
+  /// representation for the MachineFunctionInfo.<br class="">
+  virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const {<br class="">
+    return nullptr;<br class="">
+  }<br class="">
+<br class="">
+  /// Allocate and initialize an instance of the YAML representation of the<br class="">
+  /// MachineFunctionInfo.<br class="">
+  virtual yaml::MachineFunctionInfo *<br class="">
+  convertFuncInfoToYAML(const MachineFunction &MF) const {<br class="">
+    return nullptr;<br class="">
+  }<br class="">
+<br class="">
+  /// Parse out the target's MachineFunctionInfo from the YAML reprsentation.<br class="">
+  virtual bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,<br class="">
+                                        PerFunctionMIParsingState &PFS,<br class="">
+                                        SMDiagnostic &Error,<br class="">
+                                        SMRange &SourceRange) const {<br class="">
+    return false;<br class="">
+  }<br class="">
+<br class="">
   /// This method returns a pointer to the specified type of<br class="">
   /// TargetSubtargetInfo.  In debug builds, it verifies that the object being<br class="">
   /// returned is of the correct type.<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Thu Mar 14 15:54:43 2019<br class="">
@@ -10,7 +10,7 @@<br class="">
 //<br class="">
 //===----------------------------------------------------------------------===//<br class="">
<br class="">
-#include "MIParser.h"<br class="">
+#include "llvm/CodeGen/MIRParser/MIParser.h"<br class="">
 #include "MILexer.h"<br class="">
 #include "llvm/ADT/APInt.h"<br class="">
 #include "llvm/ADT/APSInt.h"<br class="">
<br class="">
Removed: llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=356214&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=356214&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (removed)<br class="">
@@ -1,233 +0,0 @@<br class="">
-//===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//<br class="">
-//<br class="">
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.<br class="">
-// See <a href="https://llvm.org/LICENSE.txt" rel="noreferrer" target="_blank" class="">https://llvm.org/LICENSE.txt</a> for license information.<br class="">
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception<br class="">
-//<br class="">
-//===----------------------------------------------------------------------===//<br class="">
-//<br class="">
-// This file declares the function that parses the machine instructions.<br class="">
-//<br class="">
-//===----------------------------------------------------------------------===//<br class="">
-<br class="">
-#ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H<br class="">
-#define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H<br class="">
-<br class="">
-#include "llvm/ADT/DenseMap.h"<br class="">
-#include "llvm/ADT/StringMap.h"<br class="">
-#include "llvm/CodeGen/MachineMemOperand.h"<br class="">
-#include "llvm/Support/Allocator.h"<br class="">
-<br class="">
-namespace llvm {<br class="">
-<br class="">
-class MachineBasicBlock;<br class="">
-class MachineFunction;<br class="">
-class MDNode;<br class="">
-class RegisterBank;<br class="">
-struct SlotMapping;<br class="">
-class SMDiagnostic;<br class="">
-class SourceMgr;<br class="">
-class StringRef;<br class="">
-class TargetRegisterClass;<br class="">
-class TargetSubtargetInfo;<br class="">
-<br class="">
-struct VRegInfo {<br class="">
-  enum uint8_t {<br class="">
-    UNKNOWN, NORMAL, GENERIC, REGBANK<br class="">
-  } Kind = UNKNOWN;<br class="">
-  bool Explicit = false; ///< VReg was explicitly specified in the .mir file.<br class="">
-  union {<br class="">
-    const TargetRegisterClass *RC;<br class="">
-    const RegisterBank *RegBank;<br class="">
-  } D;<br class="">
-  unsigned VReg;<br class="">
-  unsigned PreferredReg = 0;<br class="">
-};<br class="">
-<br class="">
-using Name2RegClassMap = StringMap<const TargetRegisterClass *>;<br class="">
-using Name2RegBankMap = StringMap<const RegisterBank *>;<br class="">
-<br class="">
-struct PerTargetMIParsingState {<br class="">
-private:<br class="">
-  const TargetSubtargetInfo &Subtarget;<br class="">
-<br class="">
-  /// Maps from instruction names to op codes.<br class="">
-  StringMap<unsigned> Names2InstrOpCodes;<br class="">
-<br class="">
-  /// Maps from register names to registers.<br class="">
-  StringMap<unsigned> Names2Regs;<br class="">
-<br class="">
-  /// Maps from register mask names to register masks.<br class="">
-  StringMap<const uint32_t *> Names2RegMasks;<br class="">
-<br class="">
-  /// Maps from subregister names to subregister indices.<br class="">
-  StringMap<unsigned> Names2SubRegIndices;<br class="">
-<br class="">
-  /// Maps from target index names to target indices.<br class="">
-  StringMap<int> Names2TargetIndices;<br class="">
-<br class="">
-  /// Maps from direct target flag names to the direct target flag values.<br class="">
-  StringMap<unsigned> Names2DirectTargetFlags;<br class="">
-<br class="">
-  /// Maps from direct target flag names to the bitmask target flag values.<br class="">
-  StringMap<unsigned> Names2BitmaskTargetFlags;<br class="">
-<br class="">
-  /// Maps from MMO target flag names to MMO target flag values.<br class="">
-  StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags;<br class="">
-<br class="">
-  /// Maps from register class names to register classes.<br class="">
-  Name2RegClassMap Names2RegClasses;<br class="">
-<br class="">
-  /// Maps from register bank names to register banks.<br class="">
-  Name2RegBankMap Names2RegBanks;<br class="">
-<br class="">
-  void initNames2InstrOpCodes();<br class="">
-  void initNames2Regs();<br class="">
-  void initNames2RegMasks();<br class="">
-  void initNames2SubRegIndices();<br class="">
-  void initNames2TargetIndices();<br class="">
-  void initNames2DirectTargetFlags();<br class="">
-  void initNames2BitmaskTargetFlags();<br class="">
-  void initNames2MMOTargetFlags();<br class="">
-<br class="">
-  void initNames2RegClasses();<br class="">
-  void initNames2RegBanks();<br class="">
-<br class="">
-public:<br class="">
-  /// Try to convert an instruction name to an opcode. Return true if the<br class="">
-  /// instruction name is invalid.<br class="">
-  bool parseInstrName(StringRef InstrName, unsigned &OpCode);<br class="">
-<br class="">
-  /// Try to convert a register name to a register number. Return true if the<br class="">
-  /// register name is invalid.<br class="">
-  bool getRegisterByName(StringRef RegName, unsigned &Reg);<br class="">
-<br class="">
-  /// Check if the given identifier is a name of a register mask.<br class="">
-  ///<br class="">
-  /// Return null if the identifier isn't a register mask.<br class="">
-  const uint32_t *getRegMask(StringRef Identifier);<br class="">
-<br class="">
-  /// Check if the given identifier is a name of a subregister index.<br class="">
-  ///<br class="">
-  /// Return 0 if the name isn't a subregister index class.<br class="">
-  unsigned getSubRegIndex(StringRef Name);<br class="">
-<br class="">
-  /// Try to convert a name of target index to the corresponding target index.<br class="">
-  ///<br class="">
-  /// Return true if the name isn't a name of a target index.<br class="">
-  bool getTargetIndex(StringRef Name, int &Index);<br class="">
-<br class="">
-  /// Try to convert a name of a direct target flag to the corresponding<br class="">
-  /// target flag.<br class="">
-  ///<br class="">
-  /// Return true if the name isn't a name of a direct flag.<br class="">
-  bool getDirectTargetFlag(StringRef Name, unsigned &Flag);<br class="">
-<br class="">
-  /// Try to convert a name of a bitmask target flag to the corresponding<br class="">
-  /// target flag.<br class="">
-  ///<br class="">
-  /// Return true if the name isn't a name of a bitmask target flag.<br class="">
-  bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag);<br class="">
-<br class="">
-  /// Try to convert a name of a MachineMemOperand target flag to the<br class="">
-  /// corresponding target flag.<br class="">
-  ///<br class="">
-  /// Return true if the name isn't a name of a target MMO flag.<br class="">
-  bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag);<br class="">
-<br class="">
-  /// Check if the given identifier is a name of a register class.<br class="">
-  ///<br class="">
-  /// Return null if the name isn't a register class.<br class="">
-  const TargetRegisterClass *getRegClass(StringRef Name);<br class="">
-<br class="">
-  /// Check if the given identifier is a name of a register bank.<br class="">
-  ///<br class="">
-  /// Return null if the name isn't a register bank.<br class="">
-  const RegisterBank *getRegBank(StringRef Name);<br class="">
-<br class="">
-  PerTargetMIParsingState(const TargetSubtargetInfo &STI)<br class="">
-    : Subtarget(STI) {<br class="">
-    initNames2RegClasses();<br class="">
-    initNames2RegBanks();<br class="">
-  }<br class="">
-<br class="">
-  ~PerTargetMIParsingState() = default;<br class="">
-<br class="">
-  void setTarget(const TargetSubtargetInfo &NewSubtarget);<br class="">
-};<br class="">
-<br class="">
-struct PerFunctionMIParsingState {<br class="">
-  BumpPtrAllocator Allocator;<br class="">
-  MachineFunction &MF;<br class="">
-  SourceMgr *SM;<br class="">
-  const SlotMapping &IRSlots;<br class="">
-  PerTargetMIParsingState &Target;<br class="">
-<br class="">
-  DenseMap<unsigned, MachineBasicBlock *> MBBSlots;<br class="">
-  DenseMap<unsigned, VRegInfo*> VRegInfos;<br class="">
-  StringMap<VRegInfo*> VRegInfosNamed;<br class="">
-  DenseMap<unsigned, int> FixedStackObjectSlots;<br class="">
-  DenseMap<unsigned, int> StackObjectSlots;<br class="">
-  DenseMap<unsigned, unsigned> ConstantPoolSlots;<br class="">
-  DenseMap<unsigned, unsigned> JumpTableSlots;<br class="">
-<br class="">
-  PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,<br class="">
-                            const SlotMapping &IRSlots,<br class="">
-                            PerTargetMIParsingState &Target);<br class="">
-<br class="">
-  VRegInfo &getVRegInfo(unsigned Num);<br class="">
-  VRegInfo &getVRegInfoNamed(StringRef RegName);<br class="">
-};<br class="">
-<br class="">
-/// Parse the machine basic block definitions, and skip the machine<br class="">
-/// instructions.<br class="">
-///<br class="">
-/// This function runs the first parsing pass on the machine function's body.<br class="">
-/// It parses only the machine basic block definitions and creates the machine<br class="">
-/// basic blocks in the given machine function.<br class="">
-///<br class="">
-/// The machine instructions aren't parsed during the first pass because all<br class="">
-/// the machine basic blocks aren't defined yet - this makes it impossible to<br class="">
-/// resolve the machine basic block references.<br class="">
-///<br class="">
-/// Return true if an error occurred.<br class="">
-bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,<br class="">
-                                       StringRef Src, SMDiagnostic &Error);<br class="">
-<br class="">
-/// Parse the machine instructions.<br class="">
-///<br class="">
-/// This function runs the second parsing pass on the machine function's body.<br class="">
-/// It skips the machine basic block definitions and parses only the machine<br class="">
-/// instructions and basic block attributes like liveins and successors.<br class="">
-///<br class="">
-/// The second parsing pass assumes that the first parsing pass already ran<br class="">
-/// on the given source string.<br class="">
-///<br class="">
-/// Return true if an error occurred.<br class="">
-bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,<br class="">
-                              SMDiagnostic &Error);<br class="">
-<br class="">
-bool parseMBBReference(PerFunctionMIParsingState &PFS,<br class="">
-                       MachineBasicBlock *&MBB, StringRef Src,<br class="">
-                       SMDiagnostic &Error);<br class="">
-<br class="">
-bool parseRegisterReference(PerFunctionMIParsingState &PFS,<br class="">
-                            unsigned &Reg, StringRef Src,<br class="">
-                            SMDiagnostic &Error);<br class="">
-<br class="">
-bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,<br class="">
-                                 StringRef Src, SMDiagnostic &Error);<br class="">
-<br class="">
-bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,<br class="">
-                                   VRegInfo *&Info, StringRef Src,<br class="">
-                                   SMDiagnostic &Error);<br class="">
-<br class="">
-bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,<br class="">
-                               StringRef Src, SMDiagnostic &Error);<br class="">
-<br class="">
-bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,<br class="">
-                 SMDiagnostic &Error);<br class="">
-<br class="">
-} // end namespace llvm<br class="">
-<br class="">
-#endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Thu Mar 14 15:54:43 2019<br class="">
@@ -12,7 +12,6 @@<br class="">
 //===----------------------------------------------------------------------===//<br class="">
<br class="">
 #include "llvm/CodeGen/MIRParser/MIRParser.h"<br class="">
-#include "MIParser.h"<br class="">
 #include "llvm/ADT/DenseMap.h"<br class="">
 #include "llvm/ADT/STLExtras.h"<br class="">
 #include "llvm/ADT/StringMap.h"<br class="">
@@ -21,6 +20,7 @@<br class="">
 #include "llvm/AsmParser/SlotMapping.h"<br class="">
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"<br class="">
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"<br class="">
+#include "llvm/CodeGen/MIRParser/MIParser.h"<br class="">
 #include "llvm/CodeGen/MIRYamlMapping.h"<br class="">
 #include "llvm/CodeGen/MachineConstantPool.h"<br class="">
 #include "llvm/CodeGen/MachineFrameInfo.h"<br class="">
@@ -39,6 +39,7 @@<br class="">
 #include "llvm/Support/SMLoc.h"<br class="">
 #include "llvm/Support/SourceMgr.h"<br class="">
 #include "llvm/Support/YAMLTraits.h"<br class="">
+#include "llvm/Target/TargetMachine.h"<br class="">
 #include <memory><br class="">
<br class="">
 using namespace llvm;<br class="">
@@ -266,6 +267,11 @@ bool MIRParserImpl::parseMachineFunction<br class="">
   // Parse the yaml.<br class="">
   yaml::MachineFunction YamlMF;<br class="">
   yaml::EmptyContext Ctx;<br class="">
+<br class="">
+  const LLVMTargetMachine &TM = MMI.getTarget();<br class="">
+  YamlMF.MachineFuncInfo = std::unique_ptr<yaml::MachineFunctionInfo>(<br class="">
+      TM.createDefaultFuncInfoYAML());<br class="">
+<br class="">
   yaml::yamlize(In, YamlMF, false, Ctx);<br class="">
   if (In.error())<br class="">
     return true;<br class="">
@@ -407,6 +413,19 @@ MIRParserImpl::initializeMachineFunction<br class="">
   if (setupRegisterInfo(PFS, YamlMF))<br class="">
     return true;<br class="">
<br class="">
+  if (YamlMF.MachineFuncInfo) {<br class="">
+    const LLVMTargetMachine &TM = MF.getTarget();<br class="">
+    // Note this is called after the initial constructor of the<br class="">
+    // MachineFunctionInfo based on the MachineFunction, which may depend on the<br class="">
+    // IR.<br class="">
+<br class="">
+    SMRange SrcRange;<br class="">
+    if (TM.parseMachineFunctionInfo(*YamlMF.MachineFuncInfo, PFS, Error,<br class="">
+                                    SrcRange)) {<br class="">
+      return error(Error, SrcRange);<br class="">
+    }<br class="">
+  }<br class="">
+<br class="">
   computeFunctionProperties(MF);<br class="">
<br class="">
   MF.getSubtarget().mirFileLoaded(MF);<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Thu Mar 14 15:54:43 2019<br class="">
@@ -215,6 +215,11 @@ void MIRPrinter::print(const MachineFunc<br class="">
     convert(YamlMF, *ConstantPool);<br class="">
   if (const auto *JumpTableInfo = MF.getJumpTableInfo())<br class="">
     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);<br class="">
+<br class="">
+  const TargetMachine &TM = MF.getTarget();<br class="">
+  YamlMF.MachineFuncInfo =<br class="">
+      std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));<br class="">
+<br class="">
   raw_string_ostream StrOS(YamlMF.Body.Value.Value);<br class="">
   bool IsNewlineNeeded = false;<br class="">
   for (const auto &MBB : MF) {<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Thu Mar 14 15:54:43 2019<br class="">
@@ -24,11 +24,13 @@<br class="">
 #include "GCNIterativeScheduler.h"<br class="">
 #include "GCNSchedStrategy.h"<br class="">
 #include "R600MachineScheduler.h"<br class="">
+#include "SIMachineFunctionInfo.h"<br class="">
 #include "SIMachineScheduler.h"<br class="">
 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"<br class="">
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"<br class="">
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"<br class="">
 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"<br class="">
+#include "llvm/CodeGen/MIRParser/MIParser.h"<br class="">
 #include "llvm/CodeGen/Passes.h"<br class="">
 #include "llvm/CodeGen/TargetPassConfig.h"<br class="">
 #include "llvm/IR/Attributes.h"<br class="">
@@ -930,3 +932,74 @@ void GCNPassConfig::addPreEmitPass() {<br class="">
 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {<br class="">
   return new GCNPassConfig(*this, PM);<br class="">
 }<br class="">
+<br class="">
+yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {<br class="">
+  return new yaml::SIMachineFunctionInfo();<br class="">
+}<br class="">
+<br class="">
+yaml::MachineFunctionInfo *<br class="">
+GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {<br class="">
+  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();<br class="">
+  return new yaml::SIMachineFunctionInfo(*MFI,<br class="">
+                                         *MF.getSubtarget().getRegisterInfo());<br class="">
+}<br class="">
+<br class="">
+bool GCNTargetMachine::parseMachineFunctionInfo(<br class="">
+    const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,<br class="">
+    SMDiagnostic &Error, SMRange &SourceRange) const {<br class="">
+  const yaml::SIMachineFunctionInfo &YamlMFI =<br class="">
+      reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);<br class="">
+  MachineFunction &MF = PFS.MF;<br class="">
+  SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();<br class="">
+<br class="">
+  MFI->initializeBaseYamlFields(YamlMFI);<br class="">
+<br class="">
+  auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {<br class="">
+    if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {<br class="">
+      SourceRange = RegName.SourceRange;<br class="">
+      return true;<br class="">
+    }<br class="">
+<br class="">
+    return false;<br class="">
+  };<br class="">
+<br class="">
+  auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {<br class="">
+    // Create a diagnostic for a the register string literal.<br class="">
+    const MemoryBuffer &Buffer =<br class="">
+        *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());<br class="">
+    Error = SMDiagnostic(*<a href="http://pfs.sm/" rel="noreferrer" target="_blank" class="">PFS.SM</a>, SMLoc(), Buffer.getBufferIdentifier(), 1,<br class="">
+                         RegName.Value.size(), SourceMgr::DK_Error,<br class="">
+                         "incorrect register class for field", RegName.Value,<br class="">
+                         None, None);<br class="">
+    SourceRange = RegName.SourceRange;<br class="">
+    return true;<br class="">
+  };<br class="">
+<br class="">
+  if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||<br class="">
+      parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) ||<br class="">
+      parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||<br class="">
+      parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))<br class="">
+    return true;<br class="">
+<br class="">
+  if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&<br class="">
+      !AMDGPU::SReg_128RegClass.contains(MFI->ScratchRSrcReg)) {<br class="">
+    return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);<br class="">
+  }<br class="">
+<br class="">
+  if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG &&<br class="">
+      !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {<br class="">
+    return diagnoseRegisterClass(YamlMFI.ScratchWaveOffsetReg);<br class="">
+  }<br class="">
+<br class="">
+  if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&<br class="">
+      !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {<br class="">
+    return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);<br class="">
+  }<br class="">
+<br class="">
+  if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&<br class="">
+      !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {<br class="">
+    return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);<br class="">
+  }<br class="">
+<br class="">
+  return false;<br class="">
+}<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h Thu Mar 14 15:54:43 2019<br class="">
@@ -110,6 +110,14 @@ public:<br class="">
   bool useIPRA() const override {<br class="">
     return true;<br class="">
   }<br class="">
+<br class="">
+  yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;<br class="">
+  yaml::MachineFunctionInfo *<br class="">
+  convertFuncInfoToYAML(const MachineFunction &MF) const override;<br class="">
+  bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,<br class="">
+                                PerFunctionMIParsingState &PFS,<br class="">
+                                SMDiagnostic &Error,<br class="">
+                                SMRange &SourceRange) const override;<br class="">
 };<br class="">
<br class="">
 } // end namespace llvm<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt Thu Mar 14 15:54:43 2019<br class="">
@@ -29,5 +29,5 @@ has_disassembler = 1<br class="">
 type = Library<br class="">
 name = AMDGPUCodeGen<br class="">
 parent = AMDGPU<br class="">
-required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils Vectorize GlobalISel BinaryFormat<br class="">
+required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils Vectorize GlobalISel BinaryFormat MIRParser<br class="">
 add_to_library_groups = AMDGPU<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Mar 14 15:54:43 2019<br class="">
@@ -9607,13 +9607,22 @@ void SITargetLowering::finalizeLowering(<br class="">
     assert(Info->getStackPtrOffsetReg() != Info->getFrameOffsetReg());<br class="">
     assert(!TRI->isSubRegister(Info->getScratchRSrcReg(),<br class="">
                                Info->getStackPtrOffsetReg()));<br class="">
-    MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());<br class="">
+    if (Info->getStackPtrOffsetReg() != AMDGPU::SP_REG)<br class="">
+      MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());<br class="">
   }<br class="">
<br class="">
-  MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());<br class="">
-  MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());<br class="">
-  MRI.replaceRegWith(AMDGPU::SCRATCH_WAVE_OFFSET_REG,<br class="">
-                     Info->getScratchWaveOffsetReg());<br class="">
+  // We need to worry about replacing the default register with itself in case<br class="">
+  // of MIR testcases missing the MFI.<br class="">
+  if (Info->getScratchRSrcReg() != AMDGPU::PRIVATE_RSRC_REG)<br class="">
+    MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());<br class="">
+<br class="">
+  if (Info->getFrameOffsetReg() != AMDGPU::FP_REG)<br class="">
+    MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());<br class="">
+<br class="">
+  if (Info->getScratchWaveOffsetReg() != AMDGPU::SCRATCH_WAVE_OFFSET_REG) {<br class="">
+    MRI.replaceRegWith(AMDGPU::SCRATCH_WAVE_OFFSET_REG,<br class="">
+                       Info->getScratchWaveOffsetReg());<br class="">
+  }<br class="">
<br class="">
   Info->limitOccupancy(MF);<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Thu Mar 14 15:54:43 2019<br class="">
@@ -319,3 +319,42 @@ MCPhysReg SIMachineFunctionInfo::getNext<br class="">
 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {<br class="">
   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;<br class="">
 }<br class="">
+<br class="">
+static yaml::StringValue regToString(unsigned Reg,<br class="">
+                                     const TargetRegisterInfo &TRI) {<br class="">
+  yaml::StringValue Dest;<br class="">
+  raw_string_ostream OS(Dest.Value);<br class="">
+  OS << printReg(Reg, &TRI);<br class="">
+  return Dest;<br class="">
+}<br class="">
+<br class="">
+yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(<br class="">
+  const llvm::SIMachineFunctionInfo& MFI,<br class="">
+  const TargetRegisterInfo &TRI)<br class="">
+  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),<br class="">
+    MaxKernArgAlign(MFI.getMaxKernArgAlign()),<br class="">
+    LDSSize(MFI.getLDSSize()),<br class="">
+    IsEntryFunction(MFI.isEntryFunction()),<br class="">
+    NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),<br class="">
+    MemoryBound(MFI.isMemoryBound()),<br class="">
+    WaveLimiter(MFI.needsWaveLimiter()),<br class="">
+    ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),<br class="">
+    ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),<br class="">
+    FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),<br class="">
+    StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)) {}<br class="">
+<br class="">
+void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {<br class="">
+  MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);<br class="">
+}<br class="">
+<br class="">
+bool SIMachineFunctionInfo::initializeBaseYamlFields(<br class="">
+  const yaml::SIMachineFunctionInfo &YamlMFI) {<br class="">
+  ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;<br class="">
+  MaxKernArgAlign = YamlMFI.MaxKernArgAlign;<br class="">
+  LDSSize = YamlMFI.LDSSize;<br class="">
+  IsEntryFunction = YamlMFI.IsEntryFunction;<br class="">
+  NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;<br class="">
+  MemoryBound = YamlMFI.MemoryBound;<br class="">
+  WaveLimiter = YamlMFI.WaveLimiter;<br class="">
+  return false;<br class="">
+}<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h Thu Mar 14 15:54:43 2019<br class="">
@@ -15,13 +15,14 @@<br class="">
<br class="">
 #include "AMDGPUArgumentUsageInfo.h"<br class="">
 #include "AMDGPUMachineFunction.h"<br class="">
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"<br class="">
 #include "SIInstrInfo.h"<br class="">
 #include "SIRegisterInfo.h"<br class="">
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"<br class="">
 #include "llvm/ADT/ArrayRef.h"<br class="">
 #include "llvm/ADT/DenseMap.h"<br class="">
 #include "llvm/ADT/Optional.h"<br class="">
 #include "llvm/ADT/SmallVector.h"<br class="">
+#include "llvm/CodeGen/MIRYamlMapping.h"<br class="">
 #include "llvm/CodeGen/PseudoSourceValue.h"<br class="">
 #include "llvm/CodeGen/TargetInstrInfo.h"<br class="">
 #include "llvm/MC/MCRegisterInfo.h"<br class="">
@@ -78,9 +79,58 @@ public:<br class="">
   }<br class="">
 };<br class="">
<br class="">
+namespace yaml {<br class="">
+<br class="">
+struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {<br class="">
+  uint64_t ExplicitKernArgSize = 0;<br class="">
+  unsigned MaxKernArgAlign = 0;<br class="">
+  unsigned LDSSize = 0;<br class="">
+  bool IsEntryFunction = false;<br class="">
+  bool NoSignedZerosFPMath = false;<br class="">
+  bool MemoryBound = false;<br class="">
+  bool WaveLimiter = false;<br class="">
+<br class="">
+  StringValue ScratchRSrcReg = "$private_rsrc_reg";<br class="">
+  StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";<br class="">
+  StringValue FrameOffsetReg = "$fp_reg";<br class="">
+  StringValue StackPtrOffsetReg = "$sp_reg";<br class="">
+<br class="">
+  SIMachineFunctionInfo() = default;<br class="">
+  SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,<br class="">
+                        const TargetRegisterInfo &TRI);<br class="">
+<br class="">
+  void mappingImpl(yaml::IO &YamlIO) override;<br class="">
+  ~SIMachineFunctionInfo() = default;<br class="">
+};<br class="">
+<br class="">
+template <> struct MappingTraits<SIMachineFunctionInfo> {<br class="">
+  static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {<br class="">
+    YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,<br class="">
+                       UINT64_C(0));<br class="">
+    YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);<br class="">
+    YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);<br class="">
+    YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);<br class="">
+    YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);<br class="">
+    YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);<br class="">
+    YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);<br class="">
+    YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,<br class="">
+                       StringValue("$private_rsrc_reg"));<br class="">
+    YamlIO.mapOptional("scratchWaveOffsetReg", MFI.ScratchWaveOffsetReg,<br class="">
+                       StringValue("$scratch_wave_offset_reg"));<br class="">
+    YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,<br class="">
+                       StringValue("$fp_reg"));<br class="">
+    YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,<br class="">
+                       StringValue("$sp_reg"));<br class="">
+  }<br class="">
+};<br class="">
+<br class="">
+} // end namespace yaml<br class="">
+<br class="">
 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which<br class="">
 /// tells the hardware which interpolation parameters to load.<br class="">
 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {<br class="">
+  friend class GCNTargetMachine;<br class="">
+<br class="">
   unsigned TIDReg = AMDGPU::NoRegister;<br class="">
<br class="">
   // Registers that may be reserved for spilling purposes. These may be the same<br class="">
@@ -219,6 +269,8 @@ private:<br class="">
 public:<br class="">
   SIMachineFunctionInfo(const MachineFunction &MF);<br class="">
<br class="">
+  bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);<br class="">
+<br class="">
   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {<br class="">
     auto I = SGPRToVGPRSpills.find(FrameIndex);<br class="">
     return (I == SGPRToVGPRSpills.end()) ?<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -53,6 +53,8 @@<br class="">
<br class="">
 name: basic_insert_dcache_wb<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
@@ -69,6 +71,8 @@ body: |<br class="">
<br class="">
 name: explicit_flush_after<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
@@ -87,6 +91,8 @@ body: |<br class="">
<br class="">
 name: explicit_flush_before<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
@@ -100,6 +106,8 @@ body: |<br class="">
 # CHECK-NEXT: S_ENDPGM 0<br class="">
 name: no_scalar_store<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
@@ -119,6 +127,8 @@ body: |<br class="">
<br class="">
 name: multi_block_store<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
@@ -146,6 +156,8 @@ body: |<br class="">
<br class="">
 name: one_block_store<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
@@ -165,6 +177,8 @@ body: |<br class="">
<br class="">
 name: si_return<br class="">
 tracksRegLiveness: false<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
<br class="">
 body: |<br class="">
   bb.0:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -76,6 +76,11 @@ name:            sgpr_spill_wrong_stack_<br class="">
 tracksRegLiveness: true<br class="">
 frameInfo:<br class="">
   hasCalls:        true<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br class="">
+  scratchWaveOffsetReg: $sgpr4<br class="">
+  frameOffsetReg: $sgpr5<br class="">
+  stackPtrOffsetReg: $sgpr32<br class="">
 body:             |<br class="">
   bb.0:<br class="">
     %0:sreg_32_xm0 = COPY $sgpr5<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -8,6 +8,10 @@<br class="">
<br class="">
 name:            foo<br class="">
 tracksRegLiveness: true<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br class="">
+  scratchWaveOffsetReg: $sgpr4<br class="">
+  stackPtrOffsetReg: $sgpr32<br class="">
 registers:<br class="">
   - { id: 0, class: sreg_64 }<br class="">
   - { id: 1100, class: sreg_128 }<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -19,6 +19,11 @@<br class="">
<br class="">
 name: expecting_non_empty_interval<br class="">
 tracksRegLiveness: true<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br class="">
+  scratchWaveOffsetReg: $sgpr4<br class="">
+  frameOffsetReg: $sgpr5<br class="">
+  stackPtrOffsetReg: $sgpr32<br class="">
 body:             |<br class="">
   bb.0:<br class="">
     successors: %bb.1<br class="">
@@ -49,6 +54,11 @@ body:             |<br class="">
 # CHECK-NEXT: S_NOP 0, implicit %2.sub2<br class="">
 name: rematerialize_empty_interval_has_reference<br class="">
 tracksRegLiveness: true<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br class="">
+  scratchWaveOffsetReg: $sgpr4<br class="">
+  frameOffsetReg: $sgpr5<br class="">
+  stackPtrOffsetReg: $sgpr32<br class="">
 body:             |<br class="">
   bb.0:<br class="">
     successors: %bb.1<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -17,9 +17,14 @@<br class="">
<br class="">
 name: no_merge_sgpr_vgpr_spill_slot<br class="">
 tracksRegLiveness: true<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br class="">
+  scratchWaveOffsetReg: $sgpr4<br class="">
+  frameOffsetReg: $sgpr5<br class="">
+  stackPtrOffsetReg: $sgpr32<br class="">
 body: |<br class="">
   bb.0:<br class="">
-      %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec<br class="">
+    %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec<br class="">
     %2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec<br class="">
     S_NOP 0, implicit %0<br class="">
     %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -39,6 +39,11 @@<br class="">
 ---<br class="">
 name:            _amdgpu_ps_main<br class="">
 tracksRegLiveness: true<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br class="">
+  scratchWaveOffsetReg: $sgpr4<br class="">
+  frameOffsetReg: $sgpr5<br class="">
+  stackPtrOffsetReg: $sgpr32<br class="">
 liveins:<br class="">
   - { reg: '$vgpr2', virtual-reg: '%0' }<br class="">
   - { reg: '$vgpr3', virtual-reg: '%1' }<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,151 @@<br class="">
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck -check-prefixes=FULL,ALL %s<br class="">
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefixes=SIMPLE,ALL %s<br class="">
+<br class="">
+<br class="">
+---<br class="">
+# ALL-LABEL: name: kernel0<br class="">
+# FULL: machineFunctionInfo:<br class="">
+# FULL-NEXT: explicitKernArgSize: 128<br class="">
+# FULL-NEXT: maxKernArgAlign: 64<br class="">
+# FULL-NEXT: ldsSize: 2048<br class="">
+# FULL-NEXT: isEntryFunction: true<br class="">
+# FULL-NEXT: noSignedZerosFPMath: false<br class="">
+# FULL-NEXT: memoryBound:     true<br class="">
+# FULL-NEXT: waveLimiter:     true<br class="">
+# FULL-NEXT: scratchRSrcReg:  '$sgpr8_sgpr9_sgpr10_sgpr11'<br class="">
+# FULL-NEXT: scratchWaveOffsetReg:  '$sgpr12'<br class="">
+# FULL-NEXT: frameOffsetReg:  '$sgpr12'<br class="">
+# FULL-NEXT: stackPtrOffsetReg:  '$sgpr13'<br class="">
+# FULL-NEXT: body:<br class="">
+<br class="">
+# SIMPLE: machineFunctionInfo:<br class="">
+# SIMPLE-NEXT: explicitKernArgSize: 128<br class="">
+# SIMPLE-NEXT: maxKernArgAlign: 64<br class="">
+# SIMPLE-NEXT: ldsSize: 2048<br class="">
+# SIMPLE-NEXT: isEntryFunction: true<br class="">
+# SIMPLE-NEXT: memoryBound: true<br class="">
+# SIMPLE-NEXT: waveLimiter: true<br class="">
+# SIMPLE-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'<br class="">
+# SIMPLE-NEXT: scratchWaveOffsetReg:  '$sgpr12'<br class="">
+# SIMPLE-NEXT: frameOffsetReg:  '$sgpr12'<br class="">
+# SIMPLE-NEXT: stackPtrOffsetReg:  '$sgpr13'<br class="">
+# SIMPLE-NEXT: body:<br class="">
+name: kernel0<br class="">
+machineFunctionInfo:<br class="">
+  explicitKernArgSize: 128<br class="">
+  maxKernArgAlign: 64<br class="">
+  ldsSize: 2048<br class="">
+  isEntryFunction: true<br class="">
+  noSignedZerosFPMath: false<br class="">
+  memoryBound:     true<br class="">
+  waveLimiter:     true<br class="">
+  scratchRSrcReg:  '$sgpr8_sgpr9_sgpr10_sgpr11'<br class="">
+  scratchWaveOffsetReg:  '$sgpr12'<br class="">
+  frameOffsetReg: '$sgpr12'<br class="">
+  stackPtrOffsetReg:  '$sgpr13'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+    S_ENDPGM 0<br class="">
+<br class="">
+...<br class="">
+<br class="">
+# FIXME: Should be able to not print section for simple<br class="">
+---<br class="">
+# ALL-LABEL: name: no_mfi<br class="">
+# FULL: machineFunctionInfo:<br class="">
+# FULL-NEXT: explicitKernArgSize: 0<br class="">
+# FULL-NEXT: maxKernArgAlign: 0<br class="">
+# FULL-NEXT: ldsSize: 0<br class="">
+# FULL-NEXT: isEntryFunction: false<br class="">
+# FULL-NEXT: noSignedZerosFPMath: false<br class="">
+# FULL-NEXT: memoryBound:     false<br class="">
+# FULL-NEXT: waveLimiter:     false<br class="">
+# FULL-NEXT: scratchRSrcReg:  '$private_rsrc_reg'<br class="">
+# FULL-NEXT: scratchWaveOffsetReg:  '$scratch_wave_offset_reg'<br class="">
+# FULL-NEXT: frameOffsetReg:  '$fp_reg'<br class="">
+# FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'<br class="">
+<br class="">
+# SIMPLE: machineFunctionInfo:<br class="">
+# SIMPLE-NEXT: body:<br class="">
+<br class="">
+name: no_mfi<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+    S_ENDPGM 0<br class="">
+<br class="">
+...<br class="">
+<br class="">
+---<br class="">
+# ALL-LABEL: name: empty_mfi<br class="">
+# FULL: machineFunctionInfo:<br class="">
+# FULL-NEXT: explicitKernArgSize: 0<br class="">
+# FULL-NEXT: maxKernArgAlign: 0<br class="">
+# FULL-NEXT: ldsSize: 0<br class="">
+# FULL-NEXT: isEntryFunction: false<br class="">
+# FULL-NEXT: noSignedZerosFPMath: false<br class="">
+# FULL-NEXT: memoryBound:     false<br class="">
+# FULL-NEXT: waveLimiter:     false<br class="">
+# FULL-NEXT: scratchRSrcReg:  '$private_rsrc_reg'<br class="">
+# FULL-NEXT: scratchWaveOffsetReg:  '$scratch_wave_offset_reg'<br class="">
+# FULL-NEXT: frameOffsetReg:  '$fp_reg'<br class="">
+# FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'<br class="">
+<br class="">
+# SIMPLE: machineFunctionInfo:<br class="">
+# SIMPLE-NEXT: body:<br class="">
+<br class="">
+name: empty_mfi<br class="">
+machineFunctionInfo:<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+    S_ENDPGM 0<br class="">
+<br class="">
+...<br class="">
+<br class="">
+---<br class="">
+# ALL-LABEL: name: empty_mfi_entry_func<br class="">
+# FULL: machineFunctionInfo:<br class="">
+# FULL-NEXT: explicitKernArgSize: 0<br class="">
+# FULL-NEXT: maxKernArgAlign: 0<br class="">
+# FULL-NEXT: ldsSize: 0<br class="">
+# FULL-NEXT: isEntryFunction: true<br class="">
+# FULL-NEXT: noSignedZerosFPMath: false<br class="">
+# FULL-NEXT: memoryBound:     false<br class="">
+# FULL-NEXT: waveLimiter:     false<br class="">
+# FULL-NEXT: scratchRSrcReg:  '$private_rsrc_reg'<br class="">
+# FULL-NEXT: scratchWaveOffsetReg:  '$scratch_wave_offset_reg'<br class="">
+# FULL-NEXT: frameOffsetReg:  '$fp_reg'<br class="">
+# FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'<br class="">
+<br class="">
+# SIMPLE: machineFunctionInfo:<br class="">
+# SIMPLE-NEXT: isEntryFunction: true<br class="">
+# SIMPLE-NEXT: body:<br class="">
+<br class="">
+name: empty_mfi_entry_func<br class="">
+machineFunctionInfo:<br class="">
+  isEntryFunction: true<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+    S_ENDPGM 0<br class="">
+<br class="">
+...<br class="">
+<br class="">
+---<br class="">
+# ALL-LABEL: name: default_regs_mfi<br class="">
+<br class="">
+# FULL: scratchRSrcReg:  '$private_rsrc_reg'<br class="">
+# FULL-NEXT: scratchWaveOffsetReg:  '$scratch_wave_offset_reg'<br class="">
+# FULL-NEXT: frameOffsetReg:  '$fp_reg'<br class="">
+# FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'<br class="">
+<br class="">
+# SIMPLE-NOT: scratchRSrcReg<br class="">
+# SIMPLE-NOT: scratchWaveOffsetReg<br class="">
+# SIMPLE-NOT:: stackPtrOffsetReg<br class="">
+name: default_regs_mfi<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg:  '$private_rsrc_reg'<br class="">
+<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+    S_ENDPGM 0<br class="">
+<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,12 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :7:27: incorrect register class for field<br class="">
+# CHECK: scratchRSrcReg:  '$noreg'<br class="">
+---<br class="">
+name: noreg_rsrc_reg<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg:  '$noreg'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,12 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :7:21: unknown register name 'not_a_register_name'<br class="">
+# CHECK: scratchRSrcReg:  '$not_a_register_name'<br class="">
+---<br class="">
+name: invalid_rsrc_reg<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg:  '$not_a_register_name'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,83 @@<br class="">
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after expand-isel-pseudos -o %t.mir %s<br class="">
+; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s<br class="">
+<br class="">
+; Test that SIMachineFunctionInfo can be round trip serialized through<br class="">
+; MIR.<br class="">
+<br class="">
+@lds = addrspace(3) global [512 x float] undef, align 4<br class="">
+<br class="">
+; CHECK-LABEL: {{^}}name: kernel<br class="">
+; CHECK: machineFunctionInfo:<br class="">
+; CHECK-NEXT: explicitKernArgSize: 128<br class="">
+; CHECK-NEXT: maxKernArgAlign: 64<br class="">
+; CHECK-NEXT: ldsSize: 2048<br class="">
+; CHECK-NEXT: isEntryFunction: true<br class="">
+; CHECK-NEXT: noSignedZerosFPMath: false<br class="">
+; CHECK-NEXT: memoryBound: false<br class="">
+; CHECK-NEXT: waveLimiter: false<br class="">
+; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'<br class="">
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'<br class="">
+; CHECK-NEXT: frameOffsetReg:  '$sgpr101'<br class="">
+; CHECK-NEXT: stackPtrOffsetReg: '$sp_reg'<br class="">
+; CHECK-NEXT: body:<br class="">
+define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {<br class="">
+  %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0<br class="">
+  store float 0.0, float addrspace(3)* %gep, align 4<br class="">
+  ret void<br class="">
+}<br class="">
+<br class="">
+; CHECK-LABEL: {{^}}name: ps_shader<br class="">
+; CHECK: machineFunctionInfo:<br class="">
+; CHECK-NEXT: explicitKernArgSize: 0<br class="">
+; CHECK-NEXT: maxKernArgAlign: 0<br class="">
+; CHECK-NEXT: ldsSize: 0<br class="">
+; CHECK-NEXT: isEntryFunction: true<br class="">
+; CHECK-NEXT: noSignedZerosFPMath: false<br class="">
+; CHECK-NEXT: memoryBound: false<br class="">
+; CHECK-NEXT: waveLimiter: false<br class="">
+; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'<br class="">
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'<br class="">
+; CHECK-NEXT: frameOffsetReg:  '$sgpr101'<br class="">
+; CHECK-NEXT: stackPtrOffsetReg: '$sp_reg'<br class="">
+; CHECK-NEXT: body:<br class="">
+define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {<br class="">
+  ret void<br class="">
+}<br class="">
+<br class="">
+; CHECK-LABEL: {{^}}name: function<br class="">
+; CHECK: machineFunctionInfo:<br class="">
+; CHECK-NEXT: explicitKernArgSize: 0<br class="">
+; CHECK-NEXT: maxKernArgAlign: 0<br class="">
+; CHECK-NEXT: ldsSize: 0<br class="">
+; CHECK-NEXT: isEntryFunction: false<br class="">
+; CHECK-NEXT: noSignedZerosFPMath: false<br class="">
+; CHECK-NEXT: memoryBound: false<br class="">
+; CHECK-NEXT: waveLimiter: false<br class="">
+; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'<br class="">
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr4'<br class="">
+; CHECK-NEXT: frameOffsetReg: '$sgpr5'<br class="">
+; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'<br class="">
+; CHECK-NEXT: body:<br class="">
+define void @function() {<br class="">
+  ret void<br class="">
+}<br class="">
+<br class="">
+; CHECK-LABEL: {{^}}name: function_nsz<br class="">
+; CHECK: machineFunctionInfo:<br class="">
+; CHECK-NEXT: explicitKernArgSize: 0<br class="">
+; CHECK-NEXT: maxKernArgAlign: 0<br class="">
+; CHECK-NEXT: ldsSize: 0<br class="">
+; CHECK-NEXT: isEntryFunction: false<br class="">
+; CHECK-NEXT: noSignedZerosFPMath: true<br class="">
+; CHECK-NEXT: memoryBound: false<br class="">
+; CHECK-NEXT: waveLimiter: false<br class="">
+; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'<br class="">
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr4'<br class="">
+; CHECK-NEXT: frameOffsetReg: '$sgpr5'<br class="">
+; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'<br class="">
+; CHECK-NEXT: body:<br class="">
+define void @function_nsz() #0 {<br class="">
+  ret void<br class="">
+}<br class="">
+<br class="">
+attributes #0 = { "no-signed-zeros-fp-math" = "true" }<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,13 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :8:27: incorrect register class for field<br class="">
+# CHECK: frameOffsetReg:  '$vgpr0'<br class="">
+<br class="">
+---<br class="">
+name: wrong_reg_class_frame_offset_reg<br class="">
+machineFunctionInfo:<br class="">
+  frameOffsetReg:  '$vgpr0'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,12 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :7:21: expected a named register<br class="">
+# CHECK: frameOffsetReg:  ''<br class="">
+---<br class="">
+name: empty_frame_offset_reg<br class="">
+machineFunctionInfo:<br class="">
+  frameOffsetReg:  ''<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,12 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :7:21: expected a named register<br class="">
+# CHECK: scratchRSrcReg:  ''<br class="">
+---<br class="">
+name: empty_scratch_rsrc_reg<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg:  ''<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,12 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :7:27: expected a named register<br class="">
+# CHECK: scratchWaveOffsetReg:  ''<br class="">
+---<br class="">
+name: empty_scratch_wave_offset_reg<br class="">
+machineFunctionInfo:<br class="">
+  scratchWaveOffsetReg:  ''<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,12 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :7:24: expected a named register<br class="">
+# CHECK: stackPtrOffsetReg:  ''<br class="">
+---<br class="">
+name: empty_stack_ptr_offset_reg<br class="">
+machineFunctionInfo:<br class="">
+  stackPtrOffsetReg:  ''<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,13 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :8:45: incorrect register class for field<br class="">
+# CHECK: scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'<br class="">
+<br class="">
+---<br class="">
+name: wrong_reg_class_scratch_rsrc_reg<br class="">
+machineFunctionInfo:<br class="">
+  scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,13 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :8:33: incorrect register class for field<br class="">
+# CHECK: scratchWaveOffsetReg:  '$vgpr0'<br class="">
+<br class="">
+---<br class="">
+name: wrong_reg_class_scratch_wave_offset_reg<br class="">
+machineFunctionInfo:<br class="">
+  scratchWaveOffsetReg:  '$vgpr0'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir?rev=356215&view=auto</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir Thu Mar 14 15:54:43 2019<br class="">
@@ -0,0 +1,13 @@<br class="">
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br class="">
+# CHECK: :8:30: incorrect register class for field<br class="">
+# CHECK: stackPtrOffsetReg:  '$vgpr0'<br class="">
+<br class="">
+---<br class="">
+name: wrong_reg_class_stack_ptr_offset_reg<br class="">
+machineFunctionInfo:<br class="">
+  stackPtrOffsetReg:  '$vgpr0'<br class="">
+body:             |<br class="">
+  bb.0:<br class="">
+<br class="">
+    S_ENDPGM<br class="">
+...<br class="">
<br class="">
<br class="">
_______________________________________________<br class="">
llvm-commits mailing list<br class="">
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a><br class="">
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</blockquote></div>
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