<div dir="ltr"><div dir="ltr">Hello Matt,<br><br>This commit added broken tests to the builder:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/16397">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/16397</a><br>. . .<br>Failing Tests (19):<br> . . .<br> LLVM :: CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir<br> LLVM :: CodeGen/MIR/AMDGPU/machine-function-info.ll<br> . . .<br>Please have a look?<br>The builder was already red and did not send any notifications.<br><br>Thanks<br><br>Galina<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Mar 14, 2019 at 3:53 PM Matt Arsenault via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: arsenm<br>
Date: Thu Mar 14 15:54:43 2019<br>
New Revision: 356215<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=356215&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=356215&view=rev</a><br>
Log:<br>
MIR: Allow targets to serialize MachineFunctionInfo<br>
<br>
This has been a very painful missing feature that has made producing<br>
reduced testcases difficult. In particular the various registers<br>
determined for stack access during function lowering were necessary to<br>
avoid undefined register errors in a large percentage of<br>
cases. Implement a subset of the important fields that need to be<br>
preserved for AMDGPU.<br>
<br>
Most of the changes are to support targets parsing register fields and<br>
properly reporting errors. The biggest sort-of bug remaining is for<br>
fields that can be initialized from the IR section will be overwritten<br>
by a default initialized machineFunctionInfo section. Another<br>
remaining bug is the machineFunctionInfo section is still printed even<br>
if empty.<br>
<br>
Added:<br>
llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h<br>
- copied, changed from r356207, llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir<br>
Removed:<br>
llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br>
llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h<br>
llvm/trunk/include/llvm/Target/TargetMachine.h<br>
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h<br>
llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h<br>
llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir<br>
<br>
Copied: llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h (from r356207, llvm/trunk/lib/CodeGen/MIRParser/MIParser.h)<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h?p2=llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h&p1=llvm/trunk/lib/CodeGen/MIRParser/MIParser.h&r1=356207&r2=356215&rev=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h?p2=llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h&p1=llvm/trunk/lib/CodeGen/MIRParser/MIParser.h&r1=356207&r2=356215&rev=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MIRParser/MIParser.h Thu Mar 14 15:54:43 2019<br>
@@ -164,8 +164,8 @@ struct PerFunctionMIParsingState {<br>
PerTargetMIParsingState &Target;<br>
<br>
DenseMap<unsigned, MachineBasicBlock *> MBBSlots;<br>
- DenseMap<unsigned, VRegInfo*> VRegInfos;<br>
- StringMap<VRegInfo*> VRegInfosNamed;<br>
+ DenseMap<unsigned, VRegInfo *> VRegInfos;<br>
+ StringMap<VRegInfo *> VRegInfosNamed;<br>
DenseMap<unsigned, int> FixedStackObjectSlots;<br>
DenseMap<unsigned, int> StackObjectSlots;<br>
DenseMap<unsigned, unsigned> ConstantPoolSlots;<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Thu Mar 14 15:54:43 2019<br>
@@ -36,6 +36,7 @@ struct StringValue {<br>
<br>
StringValue() = default;<br>
StringValue(std::string Value) : Value(std::move(Value)) {}<br>
+ StringValue(const char Val[]) : Value(Val) {}<br>
<br>
bool operator==(const StringValue &Other) const {<br>
return Value == Other.Value;<br>
@@ -482,6 +483,20 @@ template <> struct MappingTraits<Machine<br>
}<br>
};<br>
<br>
+/// Targets should override this in a way that mirrors the implementation of<br>
+/// llvm::MachineFunctionInfo.<br>
+struct MachineFunctionInfo {<br>
+ virtual ~MachineFunctionInfo() {}<br>
+ virtual void mappingImpl(IO &YamlIO) {}<br>
+};<br>
+<br>
+template <> struct MappingTraits<std::unique_ptr<MachineFunctionInfo>> {<br>
+ static void mapping(IO &YamlIO, std::unique_ptr<MachineFunctionInfo> &MFI) {<br>
+ if (MFI)<br>
+ MFI->mappingImpl(YamlIO);<br>
+ }<br>
+};<br>
+<br>
struct MachineFunction {<br>
StringRef Name;<br>
unsigned Alignment = 0;<br>
@@ -503,6 +518,7 @@ struct MachineFunction {<br>
std::vector<FixedMachineStackObject> FixedStackObjects;<br>
std::vector<MachineStackObject> StackObjects;<br>
std::vector<MachineConstantPoolValue> Constants; /// Constant pool.<br>
+ std::unique_ptr<MachineFunctionInfo> MachineFuncInfo;<br>
MachineJumpTable JumpTableInfo;<br>
BlockStringValue Body;<br>
};<br>
@@ -531,6 +547,7 @@ template <> struct MappingTraits<Machine<br>
std::vector<MachineStackObject>());<br>
YamlIO.mapOptional("constants", MF.Constants,<br>
std::vector<MachineConstantPoolValue>());<br>
+ YamlIO.mapOptional("machineFunctionInfo", MF.MachineFuncInfo);<br>
if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())<br>
YamlIO.mapOptional("jumpTable", MF.JumpTableInfo, MachineJumpTable());<br>
YamlIO.mapOptional("body", MF.Body, BlockStringValue());<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Thu Mar 14 15:54:43 2019<br>
@@ -150,6 +150,8 @@ public:<br>
bool doInitialization(Module &) override;<br>
bool doFinalization(Module &) override;<br>
<br>
+ const LLVMTargetMachine &getTarget() const { return TM; }<br>
+<br>
const MCContext &getContext() const { return Context; }<br>
MCContext &getContext() { return Context; }<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Mar 14 15:54:43 2019<br>
@@ -35,6 +35,9 @@ class MCSubtargetInfo;<br>
class MCSymbol;<br>
class raw_pwrite_stream;<br>
class PassManagerBuilder;<br>
+struct PerFunctionMIParsingState;<br>
+class SMDiagnostic;<br>
+class SMRange;<br>
class Target;<br>
class TargetIntrinsicInfo;<br>
class TargetIRAnalysis;<br>
@@ -49,6 +52,10 @@ class PassManagerBase;<br>
}<br>
using legacy::PassManagerBase;<br>
<br>
+namespace yaml {<br>
+struct MachineFunctionInfo;<br>
+}<br>
+<br>
//===----------------------------------------------------------------------===//<br>
///<br>
/// Primary interface to the complete machine description for the target<br>
@@ -114,6 +121,27 @@ public:<br>
return nullptr;<br>
}<br>
<br>
+ /// Allocate and return a default initialized instance of the YAML<br>
+ /// representation for the MachineFunctionInfo.<br>
+ virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const {<br>
+ return nullptr;<br>
+ }<br>
+<br>
+ /// Allocate and initialize an instance of the YAML representation of the<br>
+ /// MachineFunctionInfo.<br>
+ virtual yaml::MachineFunctionInfo *<br>
+ convertFuncInfoToYAML(const MachineFunction &MF) const {<br>
+ return nullptr;<br>
+ }<br>
+<br>
+ /// Parse out the target's MachineFunctionInfo from the YAML reprsentation.<br>
+ virtual bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,<br>
+ PerFunctionMIParsingState &PFS,<br>
+ SMDiagnostic &Error,<br>
+ SMRange &SourceRange) const {<br>
+ return false;<br>
+ }<br>
+<br>
/// This method returns a pointer to the specified type of<br>
/// TargetSubtargetInfo. In debug builds, it verifies that the object being<br>
/// returned is of the correct type.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Thu Mar 14 15:54:43 2019<br>
@@ -10,7 +10,7 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
-#include "MIParser.h"<br>
+#include "llvm/CodeGen/MIRParser/MIParser.h"<br>
#include "MILexer.h"<br>
#include "llvm/ADT/APInt.h"<br>
#include "llvm/ADT/APSInt.h"<br>
<br>
Removed: llvm/trunk/lib/CodeGen/MIRParser/MIParser.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=356214&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=356214&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (removed)<br>
@@ -1,233 +0,0 @@<br>
-//===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//<br>
-//<br>
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.<br>
-// See <a href="https://llvm.org/LICENSE.txt" rel="noreferrer" target="_blank">https://llvm.org/LICENSE.txt</a> for license information.<br>
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-//<br>
-// This file declares the function that parses the machine instructions.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-<br>
-#ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H<br>
-#define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H<br>
-<br>
-#include "llvm/ADT/DenseMap.h"<br>
-#include "llvm/ADT/StringMap.h"<br>
-#include "llvm/CodeGen/MachineMemOperand.h"<br>
-#include "llvm/Support/Allocator.h"<br>
-<br>
-namespace llvm {<br>
-<br>
-class MachineBasicBlock;<br>
-class MachineFunction;<br>
-class MDNode;<br>
-class RegisterBank;<br>
-struct SlotMapping;<br>
-class SMDiagnostic;<br>
-class SourceMgr;<br>
-class StringRef;<br>
-class TargetRegisterClass;<br>
-class TargetSubtargetInfo;<br>
-<br>
-struct VRegInfo {<br>
- enum uint8_t {<br>
- UNKNOWN, NORMAL, GENERIC, REGBANK<br>
- } Kind = UNKNOWN;<br>
- bool Explicit = false; ///< VReg was explicitly specified in the .mir file.<br>
- union {<br>
- const TargetRegisterClass *RC;<br>
- const RegisterBank *RegBank;<br>
- } D;<br>
- unsigned VReg;<br>
- unsigned PreferredReg = 0;<br>
-};<br>
-<br>
-using Name2RegClassMap = StringMap<const TargetRegisterClass *>;<br>
-using Name2RegBankMap = StringMap<const RegisterBank *>;<br>
-<br>
-struct PerTargetMIParsingState {<br>
-private:<br>
- const TargetSubtargetInfo &Subtarget;<br>
-<br>
- /// Maps from instruction names to op codes.<br>
- StringMap<unsigned> Names2InstrOpCodes;<br>
-<br>
- /// Maps from register names to registers.<br>
- StringMap<unsigned> Names2Regs;<br>
-<br>
- /// Maps from register mask names to register masks.<br>
- StringMap<const uint32_t *> Names2RegMasks;<br>
-<br>
- /// Maps from subregister names to subregister indices.<br>
- StringMap<unsigned> Names2SubRegIndices;<br>
-<br>
- /// Maps from target index names to target indices.<br>
- StringMap<int> Names2TargetIndices;<br>
-<br>
- /// Maps from direct target flag names to the direct target flag values.<br>
- StringMap<unsigned> Names2DirectTargetFlags;<br>
-<br>
- /// Maps from direct target flag names to the bitmask target flag values.<br>
- StringMap<unsigned> Names2BitmaskTargetFlags;<br>
-<br>
- /// Maps from MMO target flag names to MMO target flag values.<br>
- StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags;<br>
-<br>
- /// Maps from register class names to register classes.<br>
- Name2RegClassMap Names2RegClasses;<br>
-<br>
- /// Maps from register bank names to register banks.<br>
- Name2RegBankMap Names2RegBanks;<br>
-<br>
- void initNames2InstrOpCodes();<br>
- void initNames2Regs();<br>
- void initNames2RegMasks();<br>
- void initNames2SubRegIndices();<br>
- void initNames2TargetIndices();<br>
- void initNames2DirectTargetFlags();<br>
- void initNames2BitmaskTargetFlags();<br>
- void initNames2MMOTargetFlags();<br>
-<br>
- void initNames2RegClasses();<br>
- void initNames2RegBanks();<br>
-<br>
-public:<br>
- /// Try to convert an instruction name to an opcode. Return true if the<br>
- /// instruction name is invalid.<br>
- bool parseInstrName(StringRef InstrName, unsigned &OpCode);<br>
-<br>
- /// Try to convert a register name to a register number. Return true if the<br>
- /// register name is invalid.<br>
- bool getRegisterByName(StringRef RegName, unsigned &Reg);<br>
-<br>
- /// Check if the given identifier is a name of a register mask.<br>
- ///<br>
- /// Return null if the identifier isn't a register mask.<br>
- const uint32_t *getRegMask(StringRef Identifier);<br>
-<br>
- /// Check if the given identifier is a name of a subregister index.<br>
- ///<br>
- /// Return 0 if the name isn't a subregister index class.<br>
- unsigned getSubRegIndex(StringRef Name);<br>
-<br>
- /// Try to convert a name of target index to the corresponding target index.<br>
- ///<br>
- /// Return true if the name isn't a name of a target index.<br>
- bool getTargetIndex(StringRef Name, int &Index);<br>
-<br>
- /// Try to convert a name of a direct target flag to the corresponding<br>
- /// target flag.<br>
- ///<br>
- /// Return true if the name isn't a name of a direct flag.<br>
- bool getDirectTargetFlag(StringRef Name, unsigned &Flag);<br>
-<br>
- /// Try to convert a name of a bitmask target flag to the corresponding<br>
- /// target flag.<br>
- ///<br>
- /// Return true if the name isn't a name of a bitmask target flag.<br>
- bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag);<br>
-<br>
- /// Try to convert a name of a MachineMemOperand target flag to the<br>
- /// corresponding target flag.<br>
- ///<br>
- /// Return true if the name isn't a name of a target MMO flag.<br>
- bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag);<br>
-<br>
- /// Check if the given identifier is a name of a register class.<br>
- ///<br>
- /// Return null if the name isn't a register class.<br>
- const TargetRegisterClass *getRegClass(StringRef Name);<br>
-<br>
- /// Check if the given identifier is a name of a register bank.<br>
- ///<br>
- /// Return null if the name isn't a register bank.<br>
- const RegisterBank *getRegBank(StringRef Name);<br>
-<br>
- PerTargetMIParsingState(const TargetSubtargetInfo &STI)<br>
- : Subtarget(STI) {<br>
- initNames2RegClasses();<br>
- initNames2RegBanks();<br>
- }<br>
-<br>
- ~PerTargetMIParsingState() = default;<br>
-<br>
- void setTarget(const TargetSubtargetInfo &NewSubtarget);<br>
-};<br>
-<br>
-struct PerFunctionMIParsingState {<br>
- BumpPtrAllocator Allocator;<br>
- MachineFunction &MF;<br>
- SourceMgr *SM;<br>
- const SlotMapping &IRSlots;<br>
- PerTargetMIParsingState &Target;<br>
-<br>
- DenseMap<unsigned, MachineBasicBlock *> MBBSlots;<br>
- DenseMap<unsigned, VRegInfo*> VRegInfos;<br>
- StringMap<VRegInfo*> VRegInfosNamed;<br>
- DenseMap<unsigned, int> FixedStackObjectSlots;<br>
- DenseMap<unsigned, int> StackObjectSlots;<br>
- DenseMap<unsigned, unsigned> ConstantPoolSlots;<br>
- DenseMap<unsigned, unsigned> JumpTableSlots;<br>
-<br>
- PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,<br>
- const SlotMapping &IRSlots,<br>
- PerTargetMIParsingState &Target);<br>
-<br>
- VRegInfo &getVRegInfo(unsigned Num);<br>
- VRegInfo &getVRegInfoNamed(StringRef RegName);<br>
-};<br>
-<br>
-/// Parse the machine basic block definitions, and skip the machine<br>
-/// instructions.<br>
-///<br>
-/// This function runs the first parsing pass on the machine function's body.<br>
-/// It parses only the machine basic block definitions and creates the machine<br>
-/// basic blocks in the given machine function.<br>
-///<br>
-/// The machine instructions aren't parsed during the first pass because all<br>
-/// the machine basic blocks aren't defined yet - this makes it impossible to<br>
-/// resolve the machine basic block references.<br>
-///<br>
-/// Return true if an error occurred.<br>
-bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,<br>
- StringRef Src, SMDiagnostic &Error);<br>
-<br>
-/// Parse the machine instructions.<br>
-///<br>
-/// This function runs the second parsing pass on the machine function's body.<br>
-/// It skips the machine basic block definitions and parses only the machine<br>
-/// instructions and basic block attributes like liveins and successors.<br>
-///<br>
-/// The second parsing pass assumes that the first parsing pass already ran<br>
-/// on the given source string.<br>
-///<br>
-/// Return true if an error occurred.<br>
-bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,<br>
- SMDiagnostic &Error);<br>
-<br>
-bool parseMBBReference(PerFunctionMIParsingState &PFS,<br>
- MachineBasicBlock *&MBB, StringRef Src,<br>
- SMDiagnostic &Error);<br>
-<br>
-bool parseRegisterReference(PerFunctionMIParsingState &PFS,<br>
- unsigned &Reg, StringRef Src,<br>
- SMDiagnostic &Error);<br>
-<br>
-bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,<br>
- StringRef Src, SMDiagnostic &Error);<br>
-<br>
-bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,<br>
- VRegInfo *&Info, StringRef Src,<br>
- SMDiagnostic &Error);<br>
-<br>
-bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,<br>
- StringRef Src, SMDiagnostic &Error);<br>
-<br>
-bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,<br>
- SMDiagnostic &Error);<br>
-<br>
-} // end namespace llvm<br>
-<br>
-#endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Thu Mar 14 15:54:43 2019<br>
@@ -12,7 +12,6 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
#include "llvm/CodeGen/MIRParser/MIRParser.h"<br>
-#include "MIParser.h"<br>
#include "llvm/ADT/DenseMap.h"<br>
#include "llvm/ADT/STLExtras.h"<br>
#include "llvm/ADT/StringMap.h"<br>
@@ -21,6 +20,7 @@<br>
#include "llvm/AsmParser/SlotMapping.h"<br>
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"<br>
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"<br>
+#include "llvm/CodeGen/MIRParser/MIParser.h"<br>
#include "llvm/CodeGen/MIRYamlMapping.h"<br>
#include "llvm/CodeGen/MachineConstantPool.h"<br>
#include "llvm/CodeGen/MachineFrameInfo.h"<br>
@@ -39,6 +39,7 @@<br>
#include "llvm/Support/SMLoc.h"<br>
#include "llvm/Support/SourceMgr.h"<br>
#include "llvm/Support/YAMLTraits.h"<br>
+#include "llvm/Target/TargetMachine.h"<br>
#include <memory><br>
<br>
using namespace llvm;<br>
@@ -266,6 +267,11 @@ bool MIRParserImpl::parseMachineFunction<br>
// Parse the yaml.<br>
yaml::MachineFunction YamlMF;<br>
yaml::EmptyContext Ctx;<br>
+<br>
+ const LLVMTargetMachine &TM = MMI.getTarget();<br>
+ YamlMF.MachineFuncInfo = std::unique_ptr<yaml::MachineFunctionInfo>(<br>
+ TM.createDefaultFuncInfoYAML());<br>
+<br>
yaml::yamlize(In, YamlMF, false, Ctx);<br>
if (In.error())<br>
return true;<br>
@@ -407,6 +413,19 @@ MIRParserImpl::initializeMachineFunction<br>
if (setupRegisterInfo(PFS, YamlMF))<br>
return true;<br>
<br>
+ if (YamlMF.MachineFuncInfo) {<br>
+ const LLVMTargetMachine &TM = MF.getTarget();<br>
+ // Note this is called after the initial constructor of the<br>
+ // MachineFunctionInfo based on the MachineFunction, which may depend on the<br>
+ // IR.<br>
+<br>
+ SMRange SrcRange;<br>
+ if (TM.parseMachineFunctionInfo(*YamlMF.MachineFuncInfo, PFS, Error,<br>
+ SrcRange)) {<br>
+ return error(Error, SrcRange);<br>
+ }<br>
+ }<br>
+<br>
computeFunctionProperties(MF);<br>
<br>
MF.getSubtarget().mirFileLoaded(MF);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Thu Mar 14 15:54:43 2019<br>
@@ -215,6 +215,11 @@ void MIRPrinter::print(const MachineFunc<br>
convert(YamlMF, *ConstantPool);<br>
if (const auto *JumpTableInfo = MF.getJumpTableInfo())<br>
convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);<br>
+<br>
+ const TargetMachine &TM = MF.getTarget();<br>
+ YamlMF.MachineFuncInfo =<br>
+ std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));<br>
+<br>
raw_string_ostream StrOS(YamlMF.Body.Value.Value);<br>
bool IsNewlineNeeded = false;<br>
for (const auto &MBB : MF) {<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Thu Mar 14 15:54:43 2019<br>
@@ -24,11 +24,13 @@<br>
#include "GCNIterativeScheduler.h"<br>
#include "GCNSchedStrategy.h"<br>
#include "R600MachineScheduler.h"<br>
+#include "SIMachineFunctionInfo.h"<br>
#include "SIMachineScheduler.h"<br>
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"<br>
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"<br>
#include "llvm/CodeGen/GlobalISel/Legalizer.h"<br>
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"<br>
+#include "llvm/CodeGen/MIRParser/MIParser.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
#include "llvm/CodeGen/TargetPassConfig.h"<br>
#include "llvm/IR/Attributes.h"<br>
@@ -930,3 +932,74 @@ void GCNPassConfig::addPreEmitPass() {<br>
TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {<br>
return new GCNPassConfig(*this, PM);<br>
}<br>
+<br>
+yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {<br>
+ return new yaml::SIMachineFunctionInfo();<br>
+}<br>
+<br>
+yaml::MachineFunctionInfo *<br>
+GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {<br>
+ const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();<br>
+ return new yaml::SIMachineFunctionInfo(*MFI,<br>
+ *MF.getSubtarget().getRegisterInfo());<br>
+}<br>
+<br>
+bool GCNTargetMachine::parseMachineFunctionInfo(<br>
+ const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,<br>
+ SMDiagnostic &Error, SMRange &SourceRange) const {<br>
+ const yaml::SIMachineFunctionInfo &YamlMFI =<br>
+ reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);<br>
+ MachineFunction &MF = PFS.MF;<br>
+ SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();<br>
+<br>
+ MFI->initializeBaseYamlFields(YamlMFI);<br>
+<br>
+ auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {<br>
+ if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {<br>
+ SourceRange = RegName.SourceRange;<br>
+ return true;<br>
+ }<br>
+<br>
+ return false;<br>
+ };<br>
+<br>
+ auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {<br>
+ // Create a diagnostic for a the register string literal.<br>
+ const MemoryBuffer &Buffer =<br>
+ *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());<br>
+ Error = SMDiagnostic(*<a href="http://PFS.SM" rel="noreferrer" target="_blank">PFS.SM</a>, SMLoc(), Buffer.getBufferIdentifier(), 1,<br>
+ RegName.Value.size(), SourceMgr::DK_Error,<br>
+ "incorrect register class for field", RegName.Value,<br>
+ None, None);<br>
+ SourceRange = RegName.SourceRange;<br>
+ return true;<br>
+ };<br>
+<br>
+ if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||<br>
+ parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) ||<br>
+ parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||<br>
+ parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))<br>
+ return true;<br>
+<br>
+ if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&<br>
+ !AMDGPU::SReg_128RegClass.contains(MFI->ScratchRSrcReg)) {<br>
+ return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);<br>
+ }<br>
+<br>
+ if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG &&<br>
+ !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {<br>
+ return diagnoseRegisterClass(YamlMFI.ScratchWaveOffsetReg);<br>
+ }<br>
+<br>
+ if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&<br>
+ !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {<br>
+ return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);<br>
+ }<br>
+<br>
+ if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&<br>
+ !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {<br>
+ return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);<br>
+ }<br>
+<br>
+ return false;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h Thu Mar 14 15:54:43 2019<br>
@@ -110,6 +110,14 @@ public:<br>
bool useIPRA() const override {<br>
return true;<br>
}<br>
+<br>
+ yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;<br>
+ yaml::MachineFunctionInfo *<br>
+ convertFuncInfoToYAML(const MachineFunction &MF) const override;<br>
+ bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,<br>
+ PerFunctionMIParsingState &PFS,<br>
+ SMDiagnostic &Error,<br>
+ SMRange &SourceRange) const override;<br>
};<br>
<br>
} // end namespace llvm<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/LLVMBuild.txt Thu Mar 14 15:54:43 2019<br>
@@ -29,5 +29,5 @@ has_disassembler = 1<br>
type = Library<br>
name = AMDGPUCodeGen<br>
parent = AMDGPU<br>
-required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils Vectorize GlobalISel BinaryFormat<br>
+required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils Vectorize GlobalISel BinaryFormat MIRParser<br>
add_to_library_groups = AMDGPU<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Mar 14 15:54:43 2019<br>
@@ -9607,13 +9607,22 @@ void SITargetLowering::finalizeLowering(<br>
assert(Info->getStackPtrOffsetReg() != Info->getFrameOffsetReg());<br>
assert(!TRI->isSubRegister(Info->getScratchRSrcReg(),<br>
Info->getStackPtrOffsetReg()));<br>
- MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());<br>
+ if (Info->getStackPtrOffsetReg() != AMDGPU::SP_REG)<br>
+ MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg());<br>
}<br>
<br>
- MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());<br>
- MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());<br>
- MRI.replaceRegWith(AMDGPU::SCRATCH_WAVE_OFFSET_REG,<br>
- Info->getScratchWaveOffsetReg());<br>
+ // We need to worry about replacing the default register with itself in case<br>
+ // of MIR testcases missing the MFI.<br>
+ if (Info->getScratchRSrcReg() != AMDGPU::PRIVATE_RSRC_REG)<br>
+ MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG, Info->getScratchRSrcReg());<br>
+<br>
+ if (Info->getFrameOffsetReg() != AMDGPU::FP_REG)<br>
+ MRI.replaceRegWith(AMDGPU::FP_REG, Info->getFrameOffsetReg());<br>
+<br>
+ if (Info->getScratchWaveOffsetReg() != AMDGPU::SCRATCH_WAVE_OFFSET_REG) {<br>
+ MRI.replaceRegWith(AMDGPU::SCRATCH_WAVE_OFFSET_REG,<br>
+ Info->getScratchWaveOffsetReg());<br>
+ }<br>
<br>
Info->limitOccupancy(MF);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Thu Mar 14 15:54:43 2019<br>
@@ -319,3 +319,42 @@ MCPhysReg SIMachineFunctionInfo::getNext<br>
MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {<br>
return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;<br>
}<br>
+<br>
+static yaml::StringValue regToString(unsigned Reg,<br>
+ const TargetRegisterInfo &TRI) {<br>
+ yaml::StringValue Dest;<br>
+ raw_string_ostream OS(Dest.Value);<br>
+ OS << printReg(Reg, &TRI);<br>
+ return Dest;<br>
+}<br>
+<br>
+yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(<br>
+ const llvm::SIMachineFunctionInfo& MFI,<br>
+ const TargetRegisterInfo &TRI)<br>
+ : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),<br>
+ MaxKernArgAlign(MFI.getMaxKernArgAlign()),<br>
+ LDSSize(MFI.getLDSSize()),<br>
+ IsEntryFunction(MFI.isEntryFunction()),<br>
+ NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),<br>
+ MemoryBound(MFI.isMemoryBound()),<br>
+ WaveLimiter(MFI.needsWaveLimiter()),<br>
+ ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),<br>
+ ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),<br>
+ FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),<br>
+ StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)) {}<br>
+<br>
+void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {<br>
+ MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);<br>
+}<br>
+<br>
+bool SIMachineFunctionInfo::initializeBaseYamlFields(<br>
+ const yaml::SIMachineFunctionInfo &YamlMFI) {<br>
+ ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;<br>
+ MaxKernArgAlign = YamlMFI.MaxKernArgAlign;<br>
+ LDSSize = YamlMFI.LDSSize;<br>
+ IsEntryFunction = YamlMFI.IsEntryFunction;<br>
+ NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;<br>
+ MemoryBound = YamlMFI.MemoryBound;<br>
+ WaveLimiter = YamlMFI.WaveLimiter;<br>
+ return false;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h Thu Mar 14 15:54:43 2019<br>
@@ -15,13 +15,14 @@<br>
<br>
#include "AMDGPUArgumentUsageInfo.h"<br>
#include "AMDGPUMachineFunction.h"<br>
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"<br>
#include "SIInstrInfo.h"<br>
#include "SIRegisterInfo.h"<br>
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"<br>
#include "llvm/ADT/ArrayRef.h"<br>
#include "llvm/ADT/DenseMap.h"<br>
#include "llvm/ADT/Optional.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
+#include "llvm/CodeGen/MIRYamlMapping.h"<br>
#include "llvm/CodeGen/PseudoSourceValue.h"<br>
#include "llvm/CodeGen/TargetInstrInfo.h"<br>
#include "llvm/MC/MCRegisterInfo.h"<br>
@@ -78,9 +79,58 @@ public:<br>
}<br>
};<br>
<br>
+namespace yaml {<br>
+<br>
+struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {<br>
+ uint64_t ExplicitKernArgSize = 0;<br>
+ unsigned MaxKernArgAlign = 0;<br>
+ unsigned LDSSize = 0;<br>
+ bool IsEntryFunction = false;<br>
+ bool NoSignedZerosFPMath = false;<br>
+ bool MemoryBound = false;<br>
+ bool WaveLimiter = false;<br>
+<br>
+ StringValue ScratchRSrcReg = "$private_rsrc_reg";<br>
+ StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";<br>
+ StringValue FrameOffsetReg = "$fp_reg";<br>
+ StringValue StackPtrOffsetReg = "$sp_reg";<br>
+<br>
+ SIMachineFunctionInfo() = default;<br>
+ SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,<br>
+ const TargetRegisterInfo &TRI);<br>
+<br>
+ void mappingImpl(yaml::IO &YamlIO) override;<br>
+ ~SIMachineFunctionInfo() = default;<br>
+};<br>
+<br>
+template <> struct MappingTraits<SIMachineFunctionInfo> {<br>
+ static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {<br>
+ YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,<br>
+ UINT64_C(0));<br>
+ YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);<br>
+ YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);<br>
+ YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);<br>
+ YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);<br>
+ YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);<br>
+ YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);<br>
+ YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,<br>
+ StringValue("$private_rsrc_reg"));<br>
+ YamlIO.mapOptional("scratchWaveOffsetReg", MFI.ScratchWaveOffsetReg,<br>
+ StringValue("$scratch_wave_offset_reg"));<br>
+ YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,<br>
+ StringValue("$fp_reg"));<br>
+ YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,<br>
+ StringValue("$sp_reg"));<br>
+ }<br>
+};<br>
+<br>
+} // end namespace yaml<br>
+<br>
/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which<br>
/// tells the hardware which interpolation parameters to load.<br>
class SIMachineFunctionInfo final : public AMDGPUMachineFunction {<br>
+ friend class GCNTargetMachine;<br>
+<br>
unsigned TIDReg = AMDGPU::NoRegister;<br>
<br>
// Registers that may be reserved for spilling purposes. These may be the same<br>
@@ -219,6 +269,8 @@ private:<br>
public:<br>
SIMachineFunctionInfo(const MachineFunction &MF);<br>
<br>
+ bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);<br>
+<br>
ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {<br>
auto I = SGPRToVGPRSpills.find(FrameIndex);<br>
return (I == SGPRToVGPRSpills.end()) ?<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir Thu Mar 14 15:54:43 2019<br>
@@ -53,6 +53,8 @@<br>
<br>
name: basic_insert_dcache_wb<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
@@ -69,6 +71,8 @@ body: |<br>
<br>
name: explicit_flush_after<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
@@ -87,6 +91,8 @@ body: |<br>
<br>
name: explicit_flush_before<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
@@ -100,6 +106,8 @@ body: |<br>
# CHECK-NEXT: S_ENDPGM 0<br>
name: no_scalar_store<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
@@ -119,6 +127,8 @@ body: |<br>
<br>
name: multi_block_store<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
@@ -146,6 +156,8 @@ body: |<br>
<br>
name: one_block_store<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
@@ -165,6 +177,8 @@ body: |<br>
<br>
name: si_return<br>
tracksRegLiveness: false<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
<br>
body: |<br>
bb.0:<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir Thu Mar 14 15:54:43 2019<br>
@@ -76,6 +76,11 @@ name: sgpr_spill_wrong_stack_<br>
tracksRegLiveness: true<br>
frameInfo:<br>
hasCalls: true<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br>
+ scratchWaveOffsetReg: $sgpr4<br>
+ frameOffsetReg: $sgpr5<br>
+ stackPtrOffsetReg: $sgpr32<br>
body: |<br>
bb.0:<br>
%0:sreg_32_xm0 = COPY $sgpr5<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-before-exec.mir Thu Mar 14 15:54:43 2019<br>
@@ -8,6 +8,10 @@<br>
<br>
name: foo<br>
tracksRegLiveness: true<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br>
+ scratchWaveOffsetReg: $sgpr4<br>
+ stackPtrOffsetReg: $sgpr32<br>
registers:<br>
- { id: 0, class: sreg_64 }<br>
- { id: 1100, class: sreg_128 }<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir Thu Mar 14 15:54:43 2019<br>
@@ -19,6 +19,11 @@<br>
<br>
name: expecting_non_empty_interval<br>
tracksRegLiveness: true<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br>
+ scratchWaveOffsetReg: $sgpr4<br>
+ frameOffsetReg: $sgpr5<br>
+ stackPtrOffsetReg: $sgpr32<br>
body: |<br>
bb.0:<br>
successors: %bb.1<br>
@@ -49,6 +54,11 @@ body: |<br>
# CHECK-NEXT: S_NOP 0, implicit %2.sub2<br>
name: rematerialize_empty_interval_has_reference<br>
tracksRegLiveness: true<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br>
+ scratchWaveOffsetReg: $sgpr4<br>
+ frameOffsetReg: $sgpr5<br>
+ stackPtrOffsetReg: $sgpr32<br>
body: |<br>
bb.0:<br>
successors: %bb.1<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir Thu Mar 14 15:54:43 2019<br>
@@ -17,9 +17,14 @@<br>
<br>
name: no_merge_sgpr_vgpr_spill_slot<br>
tracksRegLiveness: true<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br>
+ scratchWaveOffsetReg: $sgpr4<br>
+ frameOffsetReg: $sgpr5<br>
+ stackPtrOffsetReg: $sgpr32<br>
body: |<br>
bb.0:<br>
- %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec<br>
+ %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec<br>
%2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec<br>
S_NOP 0, implicit %0<br>
%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir?rev=356215&r1=356214&r2=356215&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir?rev=356215&r1=356214&r2=356215&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir Thu Mar 14 15:54:43 2019<br>
@@ -39,6 +39,11 @@<br>
---<br>
name: _amdgpu_ps_main<br>
tracksRegLiveness: true<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3<br>
+ scratchWaveOffsetReg: $sgpr4<br>
+ frameOffsetReg: $sgpr5<br>
+ stackPtrOffsetReg: $sgpr32<br>
liveins:<br>
- { reg: '$vgpr2', virtual-reg: '%0' }<br>
- { reg: '$vgpr3', virtual-reg: '%1' }<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,151 @@<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck -check-prefixes=FULL,ALL %s<br>
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefixes=SIMPLE,ALL %s<br>
+<br>
+<br>
+---<br>
+# ALL-LABEL: name: kernel0<br>
+# FULL: machineFunctionInfo:<br>
+# FULL-NEXT: explicitKernArgSize: 128<br>
+# FULL-NEXT: maxKernArgAlign: 64<br>
+# FULL-NEXT: ldsSize: 2048<br>
+# FULL-NEXT: isEntryFunction: true<br>
+# FULL-NEXT: noSignedZerosFPMath: false<br>
+# FULL-NEXT: memoryBound: true<br>
+# FULL-NEXT: waveLimiter: true<br>
+# FULL-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'<br>
+# FULL-NEXT: scratchWaveOffsetReg: '$sgpr12'<br>
+# FULL-NEXT: frameOffsetReg: '$sgpr12'<br>
+# FULL-NEXT: stackPtrOffsetReg: '$sgpr13'<br>
+# FULL-NEXT: body:<br>
+<br>
+# SIMPLE: machineFunctionInfo:<br>
+# SIMPLE-NEXT: explicitKernArgSize: 128<br>
+# SIMPLE-NEXT: maxKernArgAlign: 64<br>
+# SIMPLE-NEXT: ldsSize: 2048<br>
+# SIMPLE-NEXT: isEntryFunction: true<br>
+# SIMPLE-NEXT: memoryBound: true<br>
+# SIMPLE-NEXT: waveLimiter: true<br>
+# SIMPLE-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'<br>
+# SIMPLE-NEXT: scratchWaveOffsetReg: '$sgpr12'<br>
+# SIMPLE-NEXT: frameOffsetReg: '$sgpr12'<br>
+# SIMPLE-NEXT: stackPtrOffsetReg: '$sgpr13'<br>
+# SIMPLE-NEXT: body:<br>
+name: kernel0<br>
+machineFunctionInfo:<br>
+ explicitKernArgSize: 128<br>
+ maxKernArgAlign: 64<br>
+ ldsSize: 2048<br>
+ isEntryFunction: true<br>
+ noSignedZerosFPMath: false<br>
+ memoryBound: true<br>
+ waveLimiter: true<br>
+ scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'<br>
+ scratchWaveOffsetReg: '$sgpr12'<br>
+ frameOffsetReg: '$sgpr12'<br>
+ stackPtrOffsetReg: '$sgpr13'<br>
+body: |<br>
+ bb.0:<br>
+ S_ENDPGM 0<br>
+<br>
+...<br>
+<br>
+# FIXME: Should be able to not print section for simple<br>
+---<br>
+# ALL-LABEL: name: no_mfi<br>
+# FULL: machineFunctionInfo:<br>
+# FULL-NEXT: explicitKernArgSize: 0<br>
+# FULL-NEXT: maxKernArgAlign: 0<br>
+# FULL-NEXT: ldsSize: 0<br>
+# FULL-NEXT: isEntryFunction: false<br>
+# FULL-NEXT: noSignedZerosFPMath: false<br>
+# FULL-NEXT: memoryBound: false<br>
+# FULL-NEXT: waveLimiter: false<br>
+# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'<br>
+# FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg'<br>
+# FULL-NEXT: frameOffsetReg: '$fp_reg'<br>
+# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'<br>
+<br>
+# SIMPLE: machineFunctionInfo:<br>
+# SIMPLE-NEXT: body:<br>
+<br>
+name: no_mfi<br>
+body: |<br>
+ bb.0:<br>
+ S_ENDPGM 0<br>
+<br>
+...<br>
+<br>
+---<br>
+# ALL-LABEL: name: empty_mfi<br>
+# FULL: machineFunctionInfo:<br>
+# FULL-NEXT: explicitKernArgSize: 0<br>
+# FULL-NEXT: maxKernArgAlign: 0<br>
+# FULL-NEXT: ldsSize: 0<br>
+# FULL-NEXT: isEntryFunction: false<br>
+# FULL-NEXT: noSignedZerosFPMath: false<br>
+# FULL-NEXT: memoryBound: false<br>
+# FULL-NEXT: waveLimiter: false<br>
+# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'<br>
+# FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg'<br>
+# FULL-NEXT: frameOffsetReg: '$fp_reg'<br>
+# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'<br>
+<br>
+# SIMPLE: machineFunctionInfo:<br>
+# SIMPLE-NEXT: body:<br>
+<br>
+name: empty_mfi<br>
+machineFunctionInfo:<br>
+body: |<br>
+ bb.0:<br>
+ S_ENDPGM 0<br>
+<br>
+...<br>
+<br>
+---<br>
+# ALL-LABEL: name: empty_mfi_entry_func<br>
+# FULL: machineFunctionInfo:<br>
+# FULL-NEXT: explicitKernArgSize: 0<br>
+# FULL-NEXT: maxKernArgAlign: 0<br>
+# FULL-NEXT: ldsSize: 0<br>
+# FULL-NEXT: isEntryFunction: true<br>
+# FULL-NEXT: noSignedZerosFPMath: false<br>
+# FULL-NEXT: memoryBound: false<br>
+# FULL-NEXT: waveLimiter: false<br>
+# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'<br>
+# FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg'<br>
+# FULL-NEXT: frameOffsetReg: '$fp_reg'<br>
+# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'<br>
+<br>
+# SIMPLE: machineFunctionInfo:<br>
+# SIMPLE-NEXT: isEntryFunction: true<br>
+# SIMPLE-NEXT: body:<br>
+<br>
+name: empty_mfi_entry_func<br>
+machineFunctionInfo:<br>
+ isEntryFunction: true<br>
+body: |<br>
+ bb.0:<br>
+ S_ENDPGM 0<br>
+<br>
+...<br>
+<br>
+---<br>
+# ALL-LABEL: name: default_regs_mfi<br>
+<br>
+# FULL: scratchRSrcReg: '$private_rsrc_reg'<br>
+# FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg'<br>
+# FULL-NEXT: frameOffsetReg: '$fp_reg'<br>
+# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'<br>
+<br>
+# SIMPLE-NOT: scratchRSrcReg<br>
+# SIMPLE-NOT: scratchWaveOffsetReg<br>
+# SIMPLE-NOT:: stackPtrOffsetReg<br>
+name: default_regs_mfi<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: '$private_rsrc_reg'<br>
+<br>
+body: |<br>
+ bb.0:<br>
+ S_ENDPGM 0<br>
+<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,12 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :7:27: incorrect register class for field<br>
+# CHECK: scratchRSrcReg: '$noreg'<br>
+---<br>
+name: noreg_rsrc_reg<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: '$noreg'<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,12 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :7:21: unknown register name 'not_a_register_name'<br>
+# CHECK: scratchRSrcReg: '$not_a_register_name'<br>
+---<br>
+name: invalid_rsrc_reg<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: '$not_a_register_name'<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,83 @@<br>
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after expand-isel-pseudos -o %t.mir %s<br>
+; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s<br>
+<br>
+; Test that SIMachineFunctionInfo can be round trip serialized through<br>
+; MIR.<br>
+<br>
+@lds = addrspace(3) global [512 x float] undef, align 4<br>
+<br>
+; CHECK-LABEL: {{^}}name: kernel<br>
+; CHECK: machineFunctionInfo:<br>
+; CHECK-NEXT: explicitKernArgSize: 128<br>
+; CHECK-NEXT: maxKernArgAlign: 64<br>
+; CHECK-NEXT: ldsSize: 2048<br>
+; CHECK-NEXT: isEntryFunction: true<br>
+; CHECK-NEXT: noSignedZerosFPMath: false<br>
+; CHECK-NEXT: memoryBound: false<br>
+; CHECK-NEXT: waveLimiter: false<br>
+; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'<br>
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'<br>
+; CHECK-NEXT: frameOffsetReg: '$sgpr101'<br>
+; CHECK-NEXT: stackPtrOffsetReg: '$sp_reg'<br>
+; CHECK-NEXT: body:<br>
+define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {<br>
+ %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0<br>
+ store float 0.0, float addrspace(3)* %gep, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; CHECK-LABEL: {{^}}name: ps_shader<br>
+; CHECK: machineFunctionInfo:<br>
+; CHECK-NEXT: explicitKernArgSize: 0<br>
+; CHECK-NEXT: maxKernArgAlign: 0<br>
+; CHECK-NEXT: ldsSize: 0<br>
+; CHECK-NEXT: isEntryFunction: true<br>
+; CHECK-NEXT: noSignedZerosFPMath: false<br>
+; CHECK-NEXT: memoryBound: false<br>
+; CHECK-NEXT: waveLimiter: false<br>
+; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'<br>
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'<br>
+; CHECK-NEXT: frameOffsetReg: '$sgpr101'<br>
+; CHECK-NEXT: stackPtrOffsetReg: '$sp_reg'<br>
+; CHECK-NEXT: body:<br>
+define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {<br>
+ ret void<br>
+}<br>
+<br>
+; CHECK-LABEL: {{^}}name: function<br>
+; CHECK: machineFunctionInfo:<br>
+; CHECK-NEXT: explicitKernArgSize: 0<br>
+; CHECK-NEXT: maxKernArgAlign: 0<br>
+; CHECK-NEXT: ldsSize: 0<br>
+; CHECK-NEXT: isEntryFunction: false<br>
+; CHECK-NEXT: noSignedZerosFPMath: false<br>
+; CHECK-NEXT: memoryBound: false<br>
+; CHECK-NEXT: waveLimiter: false<br>
+; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'<br>
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr4'<br>
+; CHECK-NEXT: frameOffsetReg: '$sgpr5'<br>
+; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'<br>
+; CHECK-NEXT: body:<br>
+define void @function() {<br>
+ ret void<br>
+}<br>
+<br>
+; CHECK-LABEL: {{^}}name: function_nsz<br>
+; CHECK: machineFunctionInfo:<br>
+; CHECK-NEXT: explicitKernArgSize: 0<br>
+; CHECK-NEXT: maxKernArgAlign: 0<br>
+; CHECK-NEXT: ldsSize: 0<br>
+; CHECK-NEXT: isEntryFunction: false<br>
+; CHECK-NEXT: noSignedZerosFPMath: true<br>
+; CHECK-NEXT: memoryBound: false<br>
+; CHECK-NEXT: waveLimiter: false<br>
+; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'<br>
+; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr4'<br>
+; CHECK-NEXT: frameOffsetReg: '$sgpr5'<br>
+; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'<br>
+; CHECK-NEXT: body:<br>
+define void @function_nsz() #0 {<br>
+ ret void<br>
+}<br>
+<br>
+attributes #0 = { "no-signed-zeros-fp-math" = "true" }<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,13 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :8:27: incorrect register class for field<br>
+# CHECK: frameOffsetReg: '$vgpr0'<br>
+<br>
+---<br>
+name: wrong_reg_class_frame_offset_reg<br>
+machineFunctionInfo:<br>
+ frameOffsetReg: '$vgpr0'<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,12 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :7:21: expected a named register<br>
+# CHECK: frameOffsetReg: ''<br>
+---<br>
+name: empty_frame_offset_reg<br>
+machineFunctionInfo:<br>
+ frameOffsetReg: ''<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,12 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :7:21: expected a named register<br>
+# CHECK: scratchRSrcReg: ''<br>
+---<br>
+name: empty_scratch_rsrc_reg<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: ''<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,12 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :7:27: expected a named register<br>
+# CHECK: scratchWaveOffsetReg: ''<br>
+---<br>
+name: empty_scratch_wave_offset_reg<br>
+machineFunctionInfo:<br>
+ scratchWaveOffsetReg: ''<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,12 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :7:24: expected a named register<br>
+# CHECK: stackPtrOffsetReg: ''<br>
+---<br>
+name: empty_stack_ptr_offset_reg<br>
+machineFunctionInfo:<br>
+ stackPtrOffsetReg: ''<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,13 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :8:45: incorrect register class for field<br>
+# CHECK: scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'<br>
+<br>
+---<br>
+name: wrong_reg_class_scratch_rsrc_reg<br>
+machineFunctionInfo:<br>
+ scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,13 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :8:33: incorrect register class for field<br>
+# CHECK: scratchWaveOffsetReg: '$vgpr0'<br>
+<br>
+---<br>
+name: wrong_reg_class_scratch_wave_offset_reg<br>
+machineFunctionInfo:<br>
+ scratchWaveOffsetReg: '$vgpr0'<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir?rev=356215&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir?rev=356215&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir Thu Mar 14 15:54:43 2019<br>
@@ -0,0 +1,13 @@<br>
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s<br>
+# CHECK: :8:30: incorrect register class for field<br>
+# CHECK: stackPtrOffsetReg: '$vgpr0'<br>
+<br>
+---<br>
+name: wrong_reg_class_stack_ptr_offset_reg<br>
+machineFunctionInfo:<br>
+ stackPtrOffsetReg: '$vgpr0'<br>
+body: |<br>
+ bb.0:<br>
+<br>
+ S_ENDPGM<br>
+...<br>
<br>
<br>
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