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<p style="margin-top:0;margin-bottom:0">Hi Daniel,</p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">It has already been fixed [1] by <span style="font-family: "Source Code Pro", monospace; font-size: 14px;"><span>Douglas Yung.</span></span></p>
<p style="margin-top:0;margin-bottom:0"><span style="font-family: "Source Code Pro", monospace; font-size: 14px;"><span><br>
</span></span></p>
<p style="margin-top:0;margin-bottom:0"><span style="font-family: "Source Code Pro", monospace; font-size: 14px;"><span>Regards,<br>
Petar</span></span></p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">[1] <a href="https://llvm.googlesource.com/llvm/+/c8c4a422420860f7d11d080f0bf5969d2bb4ebbb" class="OWAAutoLink" id="LPlnk364952" previewremoved="true">https://llvm.googlesource.com/llvm/+/c8c4a422420860f7d11d080f0bf5969d2bb4ebbb</a></p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> daniel_l_sanders@apple.com <daniel_l_sanders@apple.com> on behalf of Daniel Sanders <daniel_l_sanders@apple.com><br>
<b>Sent:</b> Wednesday, March 13, 2019 10:40 PM<br>
<b>To:</b> Petar Jovanovic<br>
<b>Cc:</b> llvm-commits<br>
<b>Subject:</b> Re: [llvm] r355825 - [MIPS][microMIPS] Add a pattern to match TruncIntFP</font>
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<br>
> On Mar 11, 2019, at 07:13, Petar Jovanovic via llvm-commits <llvm-commits@lists.llvm.org> wrote:<br>
> <br>
> Author: petarj<br>
> Date: Mon Mar 11 07:13:31 2019<br>
> New Revision: 355825<br>
> <br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=355825&view=rev" id="LPlnk971208" class="OWAAutoLink" previewremoved="true">
http://llvm.org/viewvc/llvm-project?rev=355825&view=rev</a><br>
> Log:<br>
> [MIPS][microMIPS] Add a pattern to match TruncIntFP<br>
> <br>
> A pattern needed to match TruncIntFP was missing. This was causing multiple<br>
> tests from llvm test suite to fail during compilation for micromips.<br>
> <br>
> Patch by Mirko Brkusanin.<br>
> <br>
> Differential Revision: <a href="https://reviews.llvm.org/D58722" id="LPlnk526417" class="OWAAutoLink" previewremoved="true">
https://reviews.llvm.org/D58722</a><br>
> <br>
> <br>
> Added:<br>
> llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll<br>
> Modified:<br>
> llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td<br>
> llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td<br>
> <br>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=355825&r1=355824&r2=355825&view=diff" id="LPlnk489211" class="OWAAutoLink" previewremoved="true">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=355825&r1=355824&r2=355825&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Mon Mar 11 07:13:31 2019<br>
> @@ -1039,7 +1039,7 @@ class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6<br>
> class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,<br>
> FGR32Opnd, II_TRUNC>;<br>
> class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,<br>
> - AFGR64Opnd, II_TRUNC>;<br>
> + FGR64Opnd, II_TRUNC>;<br>
> class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,<br>
> II_SQRT_S, fsqrt>;<br>
> class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,<br>
> @@ -1749,6 +1749,8 @@ def : MipsPat<(f32 fpimm0), (MTC1_MMR6 Z<br>
> def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;<br>
> def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),<br>
> (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;<br>
> +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),<br>
> + (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;<br>
> <br>
> def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),<br>
> (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,<br>
> <br>
> Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=355825&r1=355824&r2=355825&view=diff" id="LPlnk829185" class="OWAAutoLink" previewremoved="true">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=355825&r1=355824&r2=355825&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Mon Mar 11 07:13:31 2019<br>
> @@ -424,6 +424,11 @@ def : MipsPat<(f64 (fpextend FGR32Opnd:$<br>
> def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),<br>
> (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,<br>
> FGR_32;<br>
> +def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),<br>
> + (CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,<br>
> + FGR_64;<br>
> +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),<br>
> + (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6;<br>
> <br>
> // Selects<br>
> defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,<br>
> <br>
> Added: llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll?rev=355825&view=auto" id="LPlnk114001" class="OWAAutoLink" previewremoved="true">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll?rev=355825&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll Mon Mar 11 07:13:31 2019<br>
> @@ -0,0 +1,418 @@<br>
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32R2-FP64<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32R2-SF<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32R3R5<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32R3R5<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M32R6<br>
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M64<br>
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M64<br>
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M64<br>
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=M64R6<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=MMR2-FP32<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=MMR2-FP64<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=MMR2-SF<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=MMR6<br>
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\<br>
> +; RUN: FileCheck %s -check-prefixes=MMR6-SF<br>
> +<br>
> +; Test that fptosi can be matched for MIPS targets for various FPU<br>
> +; configurations<br>
> +<br>
> +define i32 @test1(float %t) {<br>
> +; M32-LABEL: test1:<br>
> +; M32: # %bb.0: # %entry<br>
> +; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S<br>
<br>
Hi Petar,<br>
<br>
The instruction numbers this test is checking for (#2637 in this instance) are tablegen-erated and can change as people add more records to tablegen. In particular, if someone adds a TargetOpcode or a GlobalISel generic opcode then this number will change.
Could you change the #2637 to {{.*}} and similarly for the other instances below?<br>
<br>
> +; M32-NEXT: # <MCOperand Reg:147><br>
<br>
Register numbers are potentially unstable too but as far as I know the only source of instability is the target itself.<br>
<br>
> +; M32-NEXT: # <MCOperand Reg:159>><br>
> +; M32-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32-NEXT: # <MCOperand Reg:19>><br>
> +; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32-NEXT: # <MCOperand Reg:321><br>
> +; M32-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M32R2-FP64-LABEL: test1:<br>
> +; M32R2-FP64: # %bb.0: # %entry<br>
> +; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S<br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147><br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:159>><br>
> +; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:19>><br>
> +; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:321><br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M32R2-SF-LABEL: test1:<br>
> +; M32R2-SF: # %bb.0: # %entry<br>
> +; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:-24>><br>
> +; M32R2-SF-NEXT: .cfi_def_cfa_offset 24<br>
> +; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill<br>
> +; M32R2-SF-NEXT: # <MCInst #2519 SW<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:19><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; M32R2-SF-NEXT: .cfi_offset 31, -4<br>
> +; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #1606 JAL<br>
> +; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>><br>
> +; M32R2-SF-NEXT: nop # <MCInst #2370 SLL<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:21><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:21><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:0>><br>
> +; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload<br>
> +; M32R2-SF-NEXT: # <MCInst #1722 LW<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:19><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>><br>
> +; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:24>><br>
> +;<br>
> +; M32R3R5-LABEL: test1:<br>
> +; M32R3R5: # %bb.0: # %entry<br>
> +; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S<br>
> +; M32R3R5-NEXT: # <MCOperand Reg:147><br>
> +; M32R3R5-NEXT: # <MCOperand Reg:159>><br>
> +; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32R3R5-NEXT: # <MCOperand Reg:19>><br>
> +; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32R3R5-NEXT: # <MCOperand Reg:321><br>
> +; M32R3R5-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M32R6-LABEL: test1:<br>
> +; M32R6: # %bb.0: # %entry<br>
> +; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S<br>
> +; M32R6-NEXT: # <MCOperand Reg:147><br>
> +; M32R6-NEXT: # <MCOperand Reg:159>><br>
> +; M32R6-NEXT: jr $ra # <MCInst #1607 JALR<br>
> +; M32R6-NEXT: # <MCOperand Reg:21><br>
> +; M32R6-NEXT: # <MCOperand Reg:19>><br>
> +; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32R6-NEXT: # <MCOperand Reg:321><br>
> +; M32R6-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M64-LABEL: test1:<br>
> +; M64: # %bb.0: # %entry<br>
> +; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S<br>
> +; M64-NEXT: # <MCOperand Reg:147><br>
> +; M64-NEXT: # <MCOperand Reg:159>><br>
> +; M64-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M64-NEXT: # <MCOperand Reg:301>><br>
> +; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M64-NEXT: # <MCOperand Reg:321><br>
> +; M64-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M64R6-LABEL: test1:<br>
> +; M64R6: # %bb.0: # %entry<br>
> +; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S<br>
> +; M64R6-NEXT: # <MCOperand Reg:147><br>
> +; M64R6-NEXT: # <MCOperand Reg:159>><br>
> +; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64<br>
> +; M64R6-NEXT: # <MCOperand Reg:355><br>
> +; M64R6-NEXT: # <MCOperand Reg:301>><br>
> +; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M64R6-NEXT: # <MCOperand Reg:321><br>
> +; M64R6-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; MMR2-FP32-LABEL: test1:<br>
> +; MMR2-FP32: # %bb.0: # %entry<br>
> +; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM<br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147><br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:159>><br>
> +; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM<br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:19>><br>
> +; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM<br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:321><br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; MMR2-FP64-LABEL: test1:<br>
> +; MMR2-FP64: # %bb.0: # %entry<br>
> +; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM<br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147><br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:159>><br>
> +; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM<br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:19>><br>
> +; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM<br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:321><br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; MMR2-SF-LABEL: test1:<br>
> +; MMR2-SF: # %bb.0: # %entry<br>
> +; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:-24>><br>
> +; MMR2-SF-NEXT: .cfi_def_cfa_offset 24<br>
> +; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill<br>
> +; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR2-SF-NEXT: .cfi_offset 31, -4<br>
> +; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #1621 JAL_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>><br>
> +; MMR2-SF-NEXT: nop # <MCInst #2370 SLL<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:21><br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:21><br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:0>><br>
> +; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload<br>
> +; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:24>><br>
> +; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>><br>
> +;<br>
> +; MMR6-LABEL: test1:<br>
> +; MMR6: # %bb.0: # %entry<br>
> +; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MMR6<br>
> +; MMR6-NEXT: # <MCOperand Reg:147><br>
> +; MMR6-NEXT: # <MCOperand Reg:159>><br>
> +; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM<br>
> +; MMR6-NEXT: # <MCOperand Reg:321><br>
> +; MMR6-NEXT: # <MCOperand Reg:147>><br>
> +; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM<br>
> +; MMR6-NEXT: # <MCOperand Reg:19>><br>
> +;<br>
> +; MMR6-SF-LABEL: test1:<br>
> +; MMR6-SF: # %bb.0: # %entry<br>
> +; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:-24>><br>
> +; MMR6-SF-NEXT: .cfi_def_cfa_offset 24<br>
> +; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill<br>
> +; MMR6-SF-NEXT: # <MCInst #2519 SW<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR6-SF-NEXT: .cfi_offset 31, -4<br>
> +; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #1610 JALRC16_MMR6<br>
> +; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>><br>
> +; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload<br>
> +; MMR6-SF-NEXT: # <MCInst #1722 LW<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:24>><br>
> +; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>><br>
> +entry:<br>
> + %conv = fptosi float %t to i32<br>
> + ret i32 %conv<br>
> +}<br>
> +<br>
> +define i32 @test2(double %t) {<br>
> +; M32-LABEL: test2:<br>
> +; M32: # %bb.0: # %entry<br>
> +; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32<br>
> +; M32-NEXT: # <MCOperand Reg:147><br>
> +; M32-NEXT: # <MCOperand Reg:133>><br>
> +; M32-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32-NEXT: # <MCOperand Reg:19>><br>
> +; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32-NEXT: # <MCOperand Reg:321><br>
> +; M32-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M32R2-FP64-LABEL: test2:<br>
> +; M32R2-FP64: # %bb.0: # %entry<br>
> +; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64<br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147><br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:373>><br>
> +; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:19>><br>
> +; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:321><br>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M32R2-SF-LABEL: test2:<br>
> +; M32R2-SF: # %bb.0: # %entry<br>
> +; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:-24>><br>
> +; M32R2-SF-NEXT: .cfi_def_cfa_offset 24<br>
> +; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill<br>
> +; M32R2-SF-NEXT: # <MCInst #2519 SW<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:19><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; M32R2-SF-NEXT: .cfi_offset 31, -4<br>
> +; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #1606 JAL<br>
> +; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>><br>
> +; M32R2-SF-NEXT: nop # <MCInst #2370 SLL<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:21><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:21><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:0>><br>
> +; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload<br>
> +; M32R2-SF-NEXT: # <MCInst #1722 LW<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:19><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>><br>
> +; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu<br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20><br>
> +; M32R2-SF-NEXT: # <MCOperand Imm:24>><br>
> +;<br>
> +; M32R3R5-LABEL: test2:<br>
> +; M32R3R5: # %bb.0: # %entry<br>
> +; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32<br>
> +; M32R3R5-NEXT: # <MCOperand Reg:147><br>
> +; M32R3R5-NEXT: # <MCOperand Reg:133>><br>
> +; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M32R3R5-NEXT: # <MCOperand Reg:19>><br>
> +; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32R3R5-NEXT: # <MCOperand Reg:321><br>
> +; M32R3R5-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M32R6-LABEL: test2:<br>
> +; M32R6: # %bb.0: # %entry<br>
> +; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64<br>
> +; M32R6-NEXT: # <MCOperand Reg:147><br>
> +; M32R6-NEXT: # <MCOperand Reg:373>><br>
> +; M32R6-NEXT: jr $ra # <MCInst #1607 JALR<br>
> +; M32R6-NEXT: # <MCOperand Reg:21><br>
> +; M32R6-NEXT: # <MCOperand Reg:19>><br>
> +; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M32R6-NEXT: # <MCOperand Reg:321><br>
> +; M32R6-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M64-LABEL: test2:<br>
> +; M64: # %bb.0: # %entry<br>
> +; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64<br>
> +; M64-NEXT: # <MCOperand Reg:147><br>
> +; M64-NEXT: # <MCOperand Reg:373>><br>
> +; M64-NEXT: jr $ra # <MCInst #1628 JR<br>
> +; M64-NEXT: # <MCOperand Reg:301>><br>
> +; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M64-NEXT: # <MCOperand Reg:321><br>
> +; M64-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; M64R6-LABEL: test2:<br>
> +; M64R6: # %bb.0: # %entry<br>
> +; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64<br>
> +; M64R6-NEXT: # <MCOperand Reg:147><br>
> +; M64R6-NEXT: # <MCOperand Reg:373>><br>
> +; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64<br>
> +; M64R6-NEXT: # <MCOperand Reg:355><br>
> +; M64R6-NEXT: # <MCOperand Reg:301>><br>
> +; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1<br>
> +; M64R6-NEXT: # <MCOperand Reg:321><br>
> +; M64R6-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; MMR2-FP32-LABEL: test2:<br>
> +; MMR2-FP32: # %bb.0: # %entry<br>
> +; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_MM<br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147><br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:133>><br>
> +; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM<br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:19>><br>
> +; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM<br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:321><br>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; MMR2-FP64-LABEL: test2:<br>
> +; MMR2-FP64: # %bb.0: # %entry<br>
> +; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM<br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147><br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:373>><br>
> +; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM<br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:19>><br>
> +; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM<br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:321><br>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147>><br>
> +;<br>
> +; MMR2-SF-LABEL: test2:<br>
> +; MMR2-SF: # %bb.0: # %entry<br>
> +; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:-24>><br>
> +; MMR2-SF-NEXT: .cfi_def_cfa_offset 24<br>
> +; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill<br>
> +; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR2-SF-NEXT: .cfi_offset 31, -4<br>
> +; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #1621 JAL_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>><br>
> +; MMR2-SF-NEXT: nop # <MCInst #2370 SLL<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:21><br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:21><br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:0>><br>
> +; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload<br>
> +; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Imm:24>><br>
> +; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM<br>
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>><br>
> +;<br>
> +; MMR6-LABEL: test2:<br>
> +; MMR6: # %bb.0: # %entry<br>
> +; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D_MMR6<br>
> +; MMR6-NEXT: # <MCOperand Reg:147><br>
> +; MMR6-NEXT: # <MCOperand Reg:373>><br>
> +; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM<br>
> +; MMR6-NEXT: # <MCOperand Reg:321><br>
> +; MMR6-NEXT: # <MCOperand Reg:147>><br>
> +; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM<br>
> +; MMR6-NEXT: # <MCOperand Reg:19>><br>
> +;<br>
> +; MMR6-SF-LABEL: test2:<br>
> +; MMR6-SF: # %bb.0: # %entry<br>
> +; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:-24>><br>
> +; MMR6-SF-NEXT: .cfi_def_cfa_offset 24<br>
> +; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill<br>
> +; MMR6-SF-NEXT: # <MCInst #2519 SW<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR6-SF-NEXT: .cfi_offset 31, -4<br>
> +; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #1610 JALRC16_MMR6<br>
> +; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>><br>
> +; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload<br>
> +; MMR6-SF-NEXT: # <MCInst #1722 LW<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:19><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>><br>
> +; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20><br>
> +; MMR6-SF-NEXT: # <MCOperand Imm:24>><br>
> +; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM<br>
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>><br>
> +entry:<br>
> + %conv = fptosi double %t to i32<br>
> + ret i32 %conv<br>
> +}<br>
> <br>
> <br>
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