<div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Feb 20, 2019 at 4:30 PM Amara Emerson via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: aemerson<br>
Date: Wed Feb 20 16:31:13 2019<br>
New Revision: 354532<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=354532&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=354532&view=rev</a><br>
Log:<br>
Revert "[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR"<br>
<br>
This reverts r354521 because it broke the bots, but passes on Darwin somehow.<br>
<br>
Removed:<br>
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir<br>
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br>
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=354532&r1=354531&r2=354532&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=354532&r1=354531&r2=354532&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Wed Feb 20 16:31:13 2019<br>
@@ -23,7 +23,6 @@<br>
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"<br>
#include "llvm/CodeGen/GlobalISel/Utils.h"<br>
#include "llvm/CodeGen/MachineBasicBlock.h"<br>
-#include "llvm/CodeGen/MachineConstantPool.h"<br>
#include "llvm/CodeGen/MachineFunction.h"<br>
#include "llvm/CodeGen/MachineInstr.h"<br>
#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
@@ -76,14 +75,6 @@ private:<br>
bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;<br>
bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;<br>
<br>
- void collectShuffleMaskIndices(MachineInstr &I, MachineRegisterInfo &MRI,<br>
- SmallVectorImpl<int> &Idxs) const;<br>
- bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;<br>
-<br>
- unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;<br>
- MachineInstr *emitLoadFromConstantPool(Constant *CPVal,<br>
- MachineIRBuilder &MIRBuilder) const;<br>
-<br>
ComplexRendererFns selectArithImmed(MachineOperand &Root) const;<br>
<br>
ComplexRendererFns selectAddrModeUnscaled(MachineOperand &Root,<br>
@@ -1705,8 +1696,6 @@ bool AArch64InstructionSelector::select(<br>
return selectMergeValues(I, MRI);<br>
case TargetOpcode::G_UNMERGE_VALUES:<br>
return selectUnmergeValues(I, MRI);<br>
- case TargetOpcode::G_SHUFFLE_VECTOR:<br>
- return selectShuffleVector(I, MRI);<br>
}<br>
<br>
return false;<br>
@@ -1923,125 +1912,6 @@ bool AArch64InstructionSelector::selectU<br>
I.eraseFromParent();<br>
return true;<br>
}<br>
-<br>
-void AArch64InstructionSelector::collectShuffleMaskIndices(<br>
- MachineInstr &I, MachineRegisterInfo &MRI,<br>
- SmallVectorImpl<int> &Idxs) const {<br>
- MachineInstr *MaskDef = MRI.getVRegDef(I.getOperand(3).getReg());<br>
- assert(<br>
- MaskDef->getOpcode() == TargetOpcode::G_BUILD_VECTOR &&<br>
- "G_SHUFFLE_VECTOR should have a constant mask operand as G_BUILD_VECTOR");<br>
- // Find the constant indices.<br>
- for (unsigned i = 1, e = MaskDef->getNumOperands(); i < e; ++i) {<br>
- MachineInstr *ScalarDef = MRI.getVRegDef(MaskDef->getOperand(i).getReg());<br>
- assert(ScalarDef && "Could not find vreg def of shufflevec index op");<br>
- // Look through copies.<br>
- while (ScalarDef->getOpcode() == TargetOpcode::COPY) {<br>
- ScalarDef = MRI.getVRegDef(ScalarDef->getOperand(1).getReg());<br>
- assert(ScalarDef && "Could not find def of copy operand");<br>
- }<br>
- assert(ScalarDef->getOpcode() == TargetOpcode::G_CONSTANT);<br>
- Idxs.push_back(ScalarDef->getOperand(1).getCImm()->getSExtValue());<br>
- }<br>
-}<br>
-<br>
-unsigned<br>
-AArch64InstructionSelector::emitConstantPoolEntry(Constant *CPVal,<br>
- MachineFunction &MF) const {<br>
- Type *CPTy = CPVal->getType()->getPointerTo();<br>
- unsigned Align = MF.getDataLayout().getPrefTypeAlignment(CPTy);<br>
- if (Align == 0)<br>
- Align = MF.getDataLayout().getTypeAllocSize(CPTy);<br>
-<br>
- MachineConstantPool *MCP = MF.getConstantPool();<br>
- return MCP->getConstantPoolIndex(CPVal, Align);<br>
-}<br>
-<br>
-MachineInstr *AArch64InstructionSelector::emitLoadFromConstantPool(<br>
- Constant *CPVal, MachineIRBuilder &MIRBuilder) const {<br>
- unsigned CPIdx = emitConstantPoolEntry(CPVal, MIRBuilder.getMF());<br>
-<br>
- auto Adrp =<br>
- MIRBuilder.buildInstr(AArch64::ADRP, {&AArch64::GPR64RegClass}, {})<br>
- .addConstantPoolIndex(CPIdx, 0, AArch64II::MO_PAGE);<br>
- auto Load =<br>
- MIRBuilder.buildInstr(AArch64::LDRQui, {&AArch64::FPR128RegClass}, {Adrp})<br>
- .addConstantPoolIndex(CPIdx, 0,<br>
- AArch64II::MO_PAGEOFF | AArch64II::MO_NC);<br>
- constrainSelectedInstRegOperands(*Adrp, TII, TRI, RBI);<br>
- constrainSelectedInstRegOperands(*Load, TII, TRI, RBI);<br>
- return &*Load;<br>
-}<br>
-<br>
-bool AArch64InstructionSelector::selectShuffleVector(<br>
- MachineInstr &I, MachineRegisterInfo &MRI) const {<br>
- const LLT DstTy = MRI.getType(I.getOperand(0).getReg());<br>
- unsigned Src1Reg = I.getOperand(1).getReg();<br>
- const LLT Src1Ty = MRI.getType(Src1Reg);<br>
- unsigned Src2Reg = I.getOperand(2).getReg();<br>
- const LLT Src2Ty = MRI.getType(Src2Reg);<br>
-<br>
- MachineBasicBlock &MBB = *I.getParent();<br>
- MachineFunction &MF = *MBB.getParent();<br>
- LLVMContext &Ctx = MF.getFunction().getContext();<br>
-<br>
- // G_SHUFFLE_VECTOR doesn't really have a strictly enforced constant mask<br>
- // operand, it comes in as a normal vector value which we have to analyze to<br>
- // find the mask indices.<br>
- SmallVector<int, 8> Mask;<br>
- collectShuffleMaskIndices(I, MRI, Mask);<br>
- assert(!Mask.empty() && "Expected to find mask indices");<br>
-<br>
- // G_SHUFFLE_VECTOR is weird in that the source operands can be scalars, if<br>
- // it's originated from a <1 x T> type. Those should have been lowered into<br>
- // G_BUILD_VECTOR earlier.<br>
- if (!Src1Ty.isVector() || !Src2Ty.isVector()) {<br>
- LLVM_DEBUG(dbgs() << "Could not select a \"scalar\" G_SHUFFLE_VECTOR\n");<br>
- return false;<br>
- }<br>
-<br>
- unsigned BytesPerElt = DstTy.getElementType().getSizeInBits() / 8;<br>
-<br>
- SmallVector<Constant *, 64> CstIdxs;<br>
- for (int Val : Mask) {<br>
- for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {<br>
- unsigned Offset = Byte + Val * BytesPerElt;<br>
- CstIdxs.emplace_back(ConstantInt::get(Type::getInt8Ty(Ctx), Offset));<br>
- }<br>
- }<br>
-<br>
- if (DstTy.getSizeInBits() != 128) {<br>
- assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");<br>
- // This case can be done with TBL1.<br>
- return false;<br>
- }<br>
-<br>
- // Use a constant pool to load the index vector for TBL.<br>
- Constant *CPVal = ConstantVector::get(CstIdxs);<br>
- MachineIRBuilder MIRBuilder(I);<br>
- MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIRBuilder);<br>
- if (!IndexLoad) {<br>
- LLVM_DEBUG(dbgs() << "Could not load from a constant pool");<br>
- return false;<br>
- }<br>
-<br>
- // For TBL2 we need to emit a REG_SEQUENCE to tie together two consecutive<br>
- // Q registers for regalloc.<br>
- auto RegSeq = MIRBuilder<br>
- .buildInstr(TargetOpcode::REG_SEQUENCE,<br>
- {&AArch64::QQRegClass}, {Src1Reg})<br>
- .addImm(AArch64::qsub0)<br>
- .addUse(Src2Reg)<br>
- .addImm(AArch64::qsub1);<br>
-<br>
- auto TBL2 =<br>
- MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},<br>
- {RegSeq, IndexLoad->getOperand(0).getReg()});<br>
- constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);<br>
- constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);<br>
- I.eraseFromParent();<br>
- return true;<br>
-}<br>
<br>
bool AArch64InstructionSelector::selectBuildVector(<br>
MachineInstr &I, MachineRegisterInfo &MRI) const {<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=354532&r1=354531&r2=354532&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=354532&r1=354531&r2=354532&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Wed Feb 20 16:31:13 2019<br>
@@ -461,29 +461,6 @@ AArch64LegalizerInfo::AArch64LegalizerIn<br>
{s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})<br>
.scalarize(1);<br>
<br>
- getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)<br>
- .legalIf([=](const LegalityQuery &Query) {<br>
- const LLT &DstTy = Query.Types[0];<br>
- const LLT &SrcTy = Query.Types[1];<br>
- // For now just support the TBL2 variant which needs the source vectors<br>
- // to be the same size as the dest.<br>
- if (DstTy != SrcTy)<br>
- return false;<br>
- ArrayRef<LLT> SupportedDstTys = {v2s32, v4s32, v2s64};<br>
- for (auto &Ty : SupportedDstTys) {<br></blockquote><div> </div><div>Hi Amara,</div><div>I was also investigating this issue. With an AddressSanitizer build, it indicated at stack-use-after-scope on the ArrayRef line above. I found that inlining into the for-loop with:</div><div> for (auto &Ty: {v2s32, v4s32, v2s64}) {</div><div>would not trigger the asan error. Just passing this along in case it helps you.</div><div>Richard</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
- if (DstTy == Ty)<br>
- return true;<br>
- }<br>
- return false;<br>
- })<br>
- // G_SHUFFLE_VECTOR can have scalar sources (from 1 x s vectors), we<br>
- // just want those lowered into G_BUILD_VECTOR<br>
- .lowerIf([=](const LegalityQuery &Query) {<br>
- return !Query.Types[1].isVector();<br>
- })<br>
- .clampNumElements(0, v4s32, v4s32)<br>
- .clampNumElements(0, v2s64, v2s64);<br>
-<br>
computeTables();<br>
verify(*ST.getInstrInfo());<br>
}<br>
<br>
Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir?rev=354531&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir?rev=354531&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir (removed)<br>
@@ -1,54 +0,0 @@<br>
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -mtriple=aarch64 -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s<br>
----<br>
-name: shuffle_v4i32<br>
-alignment: 2<br>
-tracksRegLiveness: true<br>
-body: |<br>
- bb.1:<br>
- liveins: $q0, $q1<br>
-<br>
- ; CHECK-LABEL: name: shuffle_v4i32<br>
- ; CHECK: liveins: $q0, $q1<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0<br>
- ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1<br>
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0<br>
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)<br>
- ; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], [[BUILD_VECTOR]](<4 x s32>)<br>
- ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>)<br>
- ; CHECK: RET_ReallyLR implicit $q0<br>
- %0:_(<4 x s32>) = COPY $q0<br>
- %1:_(<4 x s32>) = COPY $q1<br>
- %4:_(s32) = G_CONSTANT i32 0<br>
- %3:_(<4 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32)<br>
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)<br>
- $q0 = COPY %2(<4 x s32>)<br>
- RET_ReallyLR implicit $q0<br>
-<br>
-...<br>
----<br>
-name: shuffle_v2i64<br>
-alignment: 2<br>
-tracksRegLiveness: true<br>
-body: |<br>
- bb.1:<br>
- liveins: $q0, $q1<br>
-<br>
- ; CHECK-LABEL: name: shuffle_v2i64<br>
- ; CHECK: liveins: $q0, $q1<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0<br>
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1<br>
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0<br>
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)<br>
- ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], [[BUILD_VECTOR]](<2 x s32>)<br>
- ; CHECK: $q0 = COPY [[SHUF]](<2 x s64>)<br>
- ; CHECK: RET_ReallyLR implicit $q0<br>
- %0:_(<2 x s64>) = COPY $q0<br>
- %1:_(<2 x s64>) = COPY $q1<br>
- %4:_(s32) = G_CONSTANT i32 0<br>
- %3:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)<br>
- %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>)<br>
- $q0 = COPY %2(<2 x s64>)<br>
- RET_ReallyLR implicit $q0<br>
-<br>
-...<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=354532&r1=354531&r2=354532&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=354532&r1=354531&r2=354532&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Wed Feb 20 16:31:13 2019<br>
@@ -313,7 +313,7 @@<br>
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected<br>
#<br>
# DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 3 type indices<br>
-# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected<br>
+# DEBUG: .. type index coverage check SKIPPED: no rules defined<br>
#<br>
# DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices<br>
# DEBUG: .. type index coverage check SKIPPED: no rules defined<br>
<br>
Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir?rev=354531&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir?rev=354531&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir (removed)<br>
@@ -1,151 +0,0 @@<br>
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s<br>
---- |<br>
- ; ModuleID = 'shufflevec-only-legal.ll'<br>
- source_filename = "shufflevec-only-legal.ll"<br>
- target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"<br>
- target triple = "aarch64"<br>
-<br>
- define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {<br>
- %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0><br>
- ret <4 x i32> %shuf<br>
- }<br>
-<br>
- define <4 x i32> @shuffle_tbl_v4i32(<4 x i32> %a, <4 x i32> %b) {<br>
- %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 7, i32 1, i32 0><br>
- ret <4 x i32> %shuf<br>
- }<br>
-<br>
- define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) {<br>
- %shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer<br>
- ret <2 x i64> %shuf<br>
- }<br>
-<br>
-...<br>
----<br>
-name: shuffle_v4i32<br>
-alignment: 2<br>
-legalized: true<br>
-regBankSelected: true<br>
-tracksRegLiveness: true<br>
-registers:<br>
- - { id: 0, class: fpr }<br>
- - { id: 1, class: fpr }<br>
- - { id: 2, class: fpr }<br>
- - { id: 3, class: fpr }<br>
- - { id: 4, class: gpr }<br>
- - { id: 5, class: gpr }<br>
- - { id: 6, class: gpr }<br>
-body: |<br>
- bb.1 (%ir-block.0):<br>
- liveins: $q0, $q1<br>
-<br>
- ; CHECK-LABEL: name: shuffle_v4i32<br>
- ; CHECK: constants:<br>
- ; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'<br>
- ; CHECK: alignment: 8<br>
- ; CHECK: isTargetSpecific: false<br>
- ; CHECK: liveins: $q0, $q1<br>
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0<br>
- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br>
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0<br>
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0<br>
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1<br>
- ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]<br>
- ; CHECK: $q0 = COPY [[TBLv16i8Two]]<br>
- ; CHECK: RET_ReallyLR implicit $q0<br>
- %0:fpr(<4 x s32>) = COPY $q0<br>
- %1:fpr(<4 x s32>) = COPY $q1<br>
- %4:gpr(s32) = G_CONSTANT i32 0<br>
- %5:gpr(s32) = G_CONSTANT i32 1<br>
- %6:gpr(s32) = G_CONSTANT i32 3<br>
- %3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %4(s32)<br>
- %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)<br>
- $q0 = COPY %2(<4 x s32>)<br>
- RET_ReallyLR implicit $q0<br>
-<br>
-...<br>
----<br>
-name: shuffle_tbl_v4i32<br>
-alignment: 2<br>
-legalized: true<br>
-regBankSelected: true<br>
-tracksRegLiveness: true<br>
-registers:<br>
- - { id: 0, class: fpr }<br>
- - { id: 1, class: fpr }<br>
- - { id: 2, class: fpr }<br>
- - { id: 3, class: fpr }<br>
- - { id: 4, class: gpr }<br>
- - { id: 5, class: gpr }<br>
- - { id: 6, class: gpr }<br>
- - { id: 7, class: gpr }<br>
-body: |<br>
- bb.1 (%ir-block.0):<br>
- liveins: $q0, $q1<br>
-<br>
- ; CHECK-LABEL: name: shuffle_tbl_v4i32<br>
- ; CHECK: constants:<br>
- ; CHECK: value: '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'<br>
- ; CHECK: alignment: 8<br>
- ; CHECK: isTargetSpecific: false<br>
- ; CHECK: liveins: $q0, $q1<br>
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0<br>
- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br>
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0<br>
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0<br>
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1<br>
- ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]<br>
- ; CHECK: $q0 = COPY [[TBLv16i8Two]]<br>
- ; CHECK: RET_ReallyLR implicit $q0<br>
- %0:fpr(<4 x s32>) = COPY $q0<br>
- %1:fpr(<4 x s32>) = COPY $q1<br>
- %4:gpr(s32) = G_CONSTANT i32 5<br>
- %5:gpr(s32) = G_CONSTANT i32 7<br>
- %6:gpr(s32) = G_CONSTANT i32 1<br>
- %7:gpr(s32) = G_CONSTANT i32 0<br>
- %3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %7(s32)<br>
- %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)<br>
- $q0 = COPY %2(<4 x s32>)<br>
- RET_ReallyLR implicit $q0<br>
-<br>
-...<br>
----<br>
-name: shuffle_v2i64<br>
-alignment: 2<br>
-legalized: true<br>
-regBankSelected: true<br>
-tracksRegLiveness: true<br>
-registers:<br>
- - { id: 0, class: fpr }<br>
- - { id: 1, class: fpr }<br>
- - { id: 2, class: fpr }<br>
- - { id: 3, class: fpr }<br>
- - { id: 4, class: gpr }<br>
-body: |<br>
- bb.1 (%ir-block.0):<br>
- liveins: $q0, $q1<br>
-<br>
- ; CHECK-LABEL: name: shuffle_v2i64<br>
- ; CHECK: constants:<br>
- ; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'<br>
- ; CHECK: alignment: 8<br>
- ; CHECK: isTargetSpecific: false<br>
- ; CHECK: liveins: $q0, $q1<br>
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0<br>
- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br>
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0<br>
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0<br>
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1<br>
- ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]<br>
- ; CHECK: $q0 = COPY [[TBLv16i8Two]]<br>
- ; CHECK: RET_ReallyLR implicit $q0<br>
- %0:fpr(<2 x s64>) = COPY $q0<br>
- %1:fpr(<2 x s64>) = COPY $q1<br>
- %4:gpr(s32) = G_CONSTANT i32 0<br>
- %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)<br>
- %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>)<br>
- $q0 = COPY %2(<2 x s64>)<br>
- RET_ReallyLR implicit $q0<br>
-<br>
-...<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div></div></div></div></div>