<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Great, thanks for looking into this!<div class=""><br class=""></div><div class="">Amara<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Feb 20, 2019, at 5:10 PM, Richard Trieu <<a href="mailto:rtrieu@google.com" class="">rtrieu@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><br class="Apple-interchange-newline"><br style="caret-color: rgb(255, 255, 255); color: rgb(255, 255, 255); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><div class="gmail_quote" style="caret-color: rgb(255, 255, 255); color: rgb(255, 255, 255); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;"><div dir="ltr" class="gmail_attr">On Wed, Feb 20, 2019 at 4:30 PM Amara Emerson via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;">Author: aemerson<br class="">Date: Wed Feb 20 16:31:13 2019<br class="">New Revision: 354532<br class=""><br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=354532&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=354532&view=rev</a><br class="">Log:<br class="">Revert "[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR"<br class=""><br class="">This reverts r354521 because it broke the bots, but passes on Darwin somehow.<br class=""><br class="">Removed:<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir<br class="">Modified:<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=354532&r1=354531&r2=354532&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=354532&r1=354531&r2=354532&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Wed Feb 20 16:31:13 2019<br class="">@@ -23,7 +23,6 @@<br class=""> #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"<br class=""> #include "llvm/CodeGen/GlobalISel/Utils.h"<br class=""> #include "llvm/CodeGen/MachineBasicBlock.h"<br class="">-#include "llvm/CodeGen/MachineConstantPool.h"<br class=""> #include "llvm/CodeGen/MachineFunction.h"<br class=""> #include "llvm/CodeGen/MachineInstr.h"<br class=""> #include "llvm/CodeGen/MachineInstrBuilder.h"<br class="">@@ -76,14 +75,6 @@ private:<br class=""> bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;<br class=""> bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;<br class=""><br class="">- void collectShuffleMaskIndices(MachineInstr &I, MachineRegisterInfo &MRI,<br class="">- SmallVectorImpl<int> &Idxs) const;<br class="">- bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;<br class="">-<br class="">- unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;<br class="">- MachineInstr *emitLoadFromConstantPool(Constant *CPVal,<br class="">- MachineIRBuilder &MIRBuilder) const;<br class="">-<br class=""> ComplexRendererFns selectArithImmed(MachineOperand &Root) const;<br class=""><br class=""> ComplexRendererFns selectAddrModeUnscaled(MachineOperand &Root,<br class="">@@ -1705,8 +1696,6 @@ bool AArch64InstructionSelector::select(<br class=""> return selectMergeValues(I, MRI);<br class=""> case TargetOpcode::G_UNMERGE_VALUES:<br class=""> return selectUnmergeValues(I, MRI);<br class="">- case TargetOpcode::G_SHUFFLE_VECTOR:<br class="">- return selectShuffleVector(I, MRI);<br class=""> }<br class=""><br class=""> return false;<br class="">@@ -1923,125 +1912,6 @@ bool AArch64InstructionSelector::selectU<br class=""> I.eraseFromParent();<br class=""> return true;<br class=""> }<br class="">-<br class="">-void AArch64InstructionSelector::collectShuffleMaskIndices(<br class="">- MachineInstr &I, MachineRegisterInfo &MRI,<br class="">- SmallVectorImpl<int> &Idxs) const {<br class="">- MachineInstr *MaskDef = MRI.getVRegDef(I.getOperand(3).getReg());<br class="">- assert(<br class="">- MaskDef->getOpcode() == TargetOpcode::G_BUILD_VECTOR &&<br class="">- "G_SHUFFLE_VECTOR should have a constant mask operand as G_BUILD_VECTOR");<br class="">- // Find the constant indices.<br class="">- for (unsigned i = 1, e = MaskDef->getNumOperands(); i < e; ++i) {<br class="">- MachineInstr *ScalarDef = MRI.getVRegDef(MaskDef->getOperand(i).getReg());<br class="">- assert(ScalarDef && "Could not find vreg def of shufflevec index op");<br class="">- // Look through copies.<br class="">- while (ScalarDef->getOpcode() == TargetOpcode::COPY) {<br class="">- ScalarDef = MRI.getVRegDef(ScalarDef->getOperand(1).getReg());<br class="">- assert(ScalarDef && "Could not find def of copy operand");<br class="">- }<br class="">- assert(ScalarDef->getOpcode() == TargetOpcode::G_CONSTANT);<br class="">- Idxs.push_back(ScalarDef->getOperand(1).getCImm()->getSExtValue());<br class="">- }<br class="">-}<br class="">-<br class="">-unsigned<br class="">-AArch64InstructionSelector::emitConstantPoolEntry(Constant *CPVal,<br class="">- MachineFunction &MF) const {<br class="">- Type *CPTy = CPVal->getType()->getPointerTo();<br class="">- unsigned Align = MF.getDataLayout().getPrefTypeAlignment(CPTy);<br class="">- if (Align == 0)<br class="">- Align = MF.getDataLayout().getTypeAllocSize(CPTy);<br class="">-<br class="">- MachineConstantPool *MCP = MF.getConstantPool();<br class="">- return MCP->getConstantPoolIndex(CPVal, Align);<br class="">-}<br class="">-<br class="">-MachineInstr *AArch64InstructionSelector::emitLoadFromConstantPool(<br class="">- Constant *CPVal, MachineIRBuilder &MIRBuilder) const {<br class="">- unsigned CPIdx = emitConstantPoolEntry(CPVal, MIRBuilder.getMF());<br class="">-<br class="">- auto Adrp =<br class="">- MIRBuilder.buildInstr(AArch64::ADRP, {&AArch64::GPR64RegClass}, {})<br class="">- .addConstantPoolIndex(CPIdx, 0, AArch64II::MO_PAGE);<br class="">- auto Load =<br class="">- MIRBuilder.buildInstr(AArch64::LDRQui, {&AArch64::FPR128RegClass}, {Adrp})<br class="">- .addConstantPoolIndex(CPIdx, 0,<br class="">- AArch64II::MO_PAGEOFF | AArch64II::MO_NC);<br class="">- constrainSelectedInstRegOperands(*Adrp, TII, TRI, RBI);<br class="">- constrainSelectedInstRegOperands(*Load, TII, TRI, RBI);<br class="">- return &*Load;<br class="">-}<br class="">-<br class="">-bool AArch64InstructionSelector::selectShuffleVector(<br class="">- MachineInstr &I, MachineRegisterInfo &MRI) const {<br class="">- const LLT DstTy = MRI.getType(I.getOperand(0).getReg());<br class="">- unsigned Src1Reg = I.getOperand(1).getReg();<br class="">- const LLT Src1Ty = MRI.getType(Src1Reg);<br class="">- unsigned Src2Reg = I.getOperand(2).getReg();<br class="">- const LLT Src2Ty = MRI.getType(Src2Reg);<br class="">-<br class="">- MachineBasicBlock &MBB = *I.getParent();<br class="">- MachineFunction &MF = *MBB.getParent();<br class="">- LLVMContext &Ctx = MF.getFunction().getContext();<br class="">-<br class="">- // G_SHUFFLE_VECTOR doesn't really have a strictly enforced constant mask<br class="">- // operand, it comes in as a normal vector value which we have to analyze to<br class="">- // find the mask indices.<br class="">- SmallVector<int, 8> Mask;<br class="">- collectShuffleMaskIndices(I, MRI, Mask);<br class="">- assert(!Mask.empty() && "Expected to find mask indices");<br class="">-<br class="">- // G_SHUFFLE_VECTOR is weird in that the source operands can be scalars, if<br class="">- // it's originated from a <1 x T> type. Those should have been lowered into<br class="">- // G_BUILD_VECTOR earlier.<br class="">- if (!Src1Ty.isVector() || !Src2Ty.isVector()) {<br class="">- LLVM_DEBUG(dbgs() << "Could not select a \"scalar\" G_SHUFFLE_VECTOR\n");<br class="">- return false;<br class="">- }<br class="">-<br class="">- unsigned BytesPerElt = DstTy.getElementType().getSizeInBits() / 8;<br class="">-<br class="">- SmallVector<Constant *, 64> CstIdxs;<br class="">- for (int Val : Mask) {<br class="">- for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {<br class="">- unsigned Offset = Byte + Val * BytesPerElt;<br class="">- CstIdxs.emplace_back(ConstantInt::get(Type::getInt8Ty(Ctx), Offset));<br class="">- }<br class="">- }<br class="">-<br class="">- if (DstTy.getSizeInBits() != 128) {<br class="">- assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");<br class="">- // This case can be done with TBL1.<br class="">- return false;<br class="">- }<br class="">-<br class="">- // Use a constant pool to load the index vector for TBL.<br class="">- Constant *CPVal = ConstantVector::get(CstIdxs);<br class="">- MachineIRBuilder MIRBuilder(I);<br class="">- MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIRBuilder);<br class="">- if (!IndexLoad) {<br class="">- LLVM_DEBUG(dbgs() << "Could not load from a constant pool");<br class="">- return false;<br class="">- }<br class="">-<br class="">- // For TBL2 we need to emit a REG_SEQUENCE to tie together two consecutive<br class="">- // Q registers for regalloc.<br class="">- auto RegSeq = MIRBuilder<br class="">- .buildInstr(TargetOpcode::REG_SEQUENCE,<br class="">- {&AArch64::QQRegClass}, {Src1Reg})<br class="">- .addImm(AArch64::qsub0)<br class="">- .addUse(Src2Reg)<br class="">- .addImm(AArch64::qsub1);<br class="">-<br class="">- auto TBL2 =<br class="">- MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},<br class="">- {RegSeq, IndexLoad->getOperand(0).getReg()});<br class="">- constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);<br class="">- constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);<br class="">- I.eraseFromParent();<br class="">- return true;<br class="">-}<br class=""><br class=""> bool AArch64InstructionSelector::selectBuildVector(<br class=""> MachineInstr &I, MachineRegisterInfo &MRI) const {<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=354532&r1=354531&r2=354532&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=354532&r1=354531&r2=354532&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Wed Feb 20 16:31:13 2019<br class="">@@ -461,29 +461,6 @@ AArch64LegalizerInfo::AArch64LegalizerIn<br class=""> {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})<br class=""> .scalarize(1);<br class=""><br class="">- getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)<br class="">- .legalIf([=](const LegalityQuery &Query) {<br class="">- const LLT &DstTy = Query.Types[0];<br class="">- const LLT &SrcTy = Query.Types[1];<br class="">- // For now just support the TBL2 variant which needs the source vectors<br class="">- // to be the same size as the dest.<br class="">- if (DstTy != SrcTy)<br class="">- return false;<br class="">- ArrayRef<LLT> SupportedDstTys = {v2s32, v4s32, v2s64};<br class="">- for (auto &Ty : SupportedDstTys) {<br class=""></blockquote><div class=""> </div><div class="">Hi Amara,</div><div class="">I was also investigating this issue. With an AddressSanitizer build, it indicated at stack-use-after-scope on the ArrayRef line above. I found that inlining into the for-loop with:</div><div class=""> for (auto &Ty: {v2s32, v4s32, v2s64}) {</div><div class="">would not trigger the asan error. Just passing this along in case it helps you.</div><div class="">Richard</div><div class=""><br class=""></div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;">- if (DstTy == Ty)<br class="">- return true;<br class="">- }<br class="">- return false;<br class="">- })<br class="">- // G_SHUFFLE_VECTOR can have scalar sources (from 1 x s vectors), we<br class="">- // just want those lowered into G_BUILD_VECTOR<br class="">- .lowerIf([=](const LegalityQuery &Query) {<br class="">- return !Query.Types[1].isVector();<br class="">- })<br class="">- .clampNumElements(0, v4s32, v4s32)<br class="">- .clampNumElements(0, v2s64, v2s64);<br class="">-<br class=""> computeTables();<br class=""> verify(*ST.getInstrInfo());<br class=""> }<br class=""><br class="">Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir?rev=354531&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir?rev=354531&view=auto</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir (original)<br class="">+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir (removed)<br class="">@@ -1,54 +0,0 @@<br class="">-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br class="">-# RUN: llc -mtriple=aarch64 -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s<br class="">----<br class="">-name: shuffle_v4i32<br class="">-alignment: 2<br class="">-tracksRegLiveness: true<br class="">-body: |<br class="">- bb.1:<br class="">- liveins: $q0, $q1<br class="">-<br class="">- ; CHECK-LABEL: name: shuffle_v4i32<br class="">- ; CHECK: liveins: $q0, $q1<br class="">- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0<br class="">- ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1<br class="">- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0<br class="">- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)<br class="">- ; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], [[BUILD_VECTOR]](<4 x s32>)<br class="">- ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>)<br class="">- ; CHECK: RET_ReallyLR implicit $q0<br class="">- %0:_(<4 x s32>) = COPY $q0<br class="">- %1:_(<4 x s32>) = COPY $q1<br class="">- %4:_(s32) = G_CONSTANT i32 0<br class="">- %3:_(<4 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32)<br class="">- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)<br class="">- $q0 = COPY %2(<4 x s32>)<br class="">- RET_ReallyLR implicit $q0<br class="">-<br class="">-...<br class="">----<br class="">-name: shuffle_v2i64<br class="">-alignment: 2<br class="">-tracksRegLiveness: true<br class="">-body: |<br class="">- bb.1:<br class="">- liveins: $q0, $q1<br class="">-<br class="">- ; CHECK-LABEL: name: shuffle_v2i64<br class="">- ; CHECK: liveins: $q0, $q1<br class="">- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0<br class="">- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1<br class="">- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0<br class="">- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)<br class="">- ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], [[BUILD_VECTOR]](<2 x s32>)<br class="">- ; CHECK: $q0 = COPY [[SHUF]](<2 x s64>)<br class="">- ; CHECK: RET_ReallyLR implicit $q0<br class="">- %0:_(<2 x s64>) = COPY $q0<br class="">- %1:_(<2 x s64>) = COPY $q1<br class="">- %4:_(s32) = G_CONSTANT i32 0<br class="">- %3:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)<br class="">- %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>)<br class="">- $q0 = COPY %2(<2 x s64>)<br class="">- RET_ReallyLR implicit $q0<br class="">-<br class="">-...<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=354532&r1=354531&r2=354532&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=354532&r1=354531&r2=354532&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)<br class="">+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Wed Feb 20 16:31:13 2019<br class="">@@ -313,7 +313,7 @@<br class=""> # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected<br class=""> #<br class=""> # DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 3 type indices<br class="">-# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected<br class="">+# DEBUG: .. type index coverage check SKIPPED: no rules defined<br class=""> #<br class=""> # DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices<br class=""> # DEBUG: .. type index coverage check SKIPPED: no rules defined<br class=""><br class="">Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir?rev=354531&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir?rev=354531&view=auto</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir (original)<br class="">+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir (removed)<br class="">@@ -1,151 +0,0 @@<br class="">-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br class="">-# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s<br class="">---- |<br class="">- ; ModuleID = 'shufflevec-only-legal.ll'<br class="">- source_filename = "shufflevec-only-legal.ll"<br class="">- target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"<br class="">- target triple = "aarch64"<br class="">-<br class="">- define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {<br class="">- %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0><br class="">- ret <4 x i32> %shuf<br class="">- }<br class="">-<br class="">- define <4 x i32> @shuffle_tbl_v4i32(<4 x i32> %a, <4 x i32> %b) {<br class="">- %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 7, i32 1, i32 0><br class="">- ret <4 x i32> %shuf<br class="">- }<br class="">-<br class="">- define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) {<br class="">- %shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer<br class="">- ret <2 x i64> %shuf<br class="">- }<br class="">-<br class="">-...<br class="">----<br class="">-name: shuffle_v4i32<br class="">-alignment: 2<br class="">-legalized: true<br class="">-regBankSelected: true<br class="">-tracksRegLiveness: true<br class="">-registers:<br class="">- - { id: 0, class: fpr }<br class="">- - { id: 1, class: fpr }<br class="">- - { id: 2, class: fpr }<br class="">- - { id: 3, class: fpr }<br class="">- - { id: 4, class: gpr }<br class="">- - { id: 5, class: gpr }<br class="">- - { id: 6, class: gpr }<br class="">-body: |<br class="">- bb.1 (%ir-block.0):<br class="">- liveins: $q0, $q1<br class="">-<br class="">- ; CHECK-LABEL: name: shuffle_v4i32<br class="">- ; CHECK: constants:<br class="">- ; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'<br class="">- ; CHECK: alignment: 8<br class="">- ; CHECK: isTargetSpecific: false<br class="">- ; CHECK: liveins: $q0, $q1<br class="">- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0<br class="">- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br class="">- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0<br class="">- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0<br class="">- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1<br class="">- ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]<br class="">- ; CHECK: $q0 = COPY [[TBLv16i8Two]]<br class="">- ; CHECK: RET_ReallyLR implicit $q0<br class="">- %0:fpr(<4 x s32>) = COPY $q0<br class="">- %1:fpr(<4 x s32>) = COPY $q1<br class="">- %4:gpr(s32) = G_CONSTANT i32 0<br class="">- %5:gpr(s32) = G_CONSTANT i32 1<br class="">- %6:gpr(s32) = G_CONSTANT i32 3<br class="">- %3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %4(s32)<br class="">- %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)<br class="">- $q0 = COPY %2(<4 x s32>)<br class="">- RET_ReallyLR implicit $q0<br class="">-<br class="">-...<br class="">----<br class="">-name: shuffle_tbl_v4i32<br class="">-alignment: 2<br class="">-legalized: true<br class="">-regBankSelected: true<br class="">-tracksRegLiveness: true<br class="">-registers:<br class="">- - { id: 0, class: fpr }<br class="">- - { id: 1, class: fpr }<br class="">- - { id: 2, class: fpr }<br class="">- - { id: 3, class: fpr }<br class="">- - { id: 4, class: gpr }<br class="">- - { id: 5, class: gpr }<br class="">- - { id: 6, class: gpr }<br class="">- - { id: 7, class: gpr }<br class="">-body: |<br class="">- bb.1 (%ir-block.0):<br class="">- liveins: $q0, $q1<br class="">-<br class="">- ; CHECK-LABEL: name: shuffle_tbl_v4i32<br class="">- ; CHECK: constants:<br class="">- ; CHECK: value: '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'<br class="">- ; CHECK: alignment: 8<br class="">- ; CHECK: isTargetSpecific: false<br class="">- ; CHECK: liveins: $q0, $q1<br class="">- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0<br class="">- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br class="">- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0<br class="">- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0<br class="">- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1<br class="">- ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]<br class="">- ; CHECK: $q0 = COPY [[TBLv16i8Two]]<br class="">- ; CHECK: RET_ReallyLR implicit $q0<br class="">- %0:fpr(<4 x s32>) = COPY $q0<br class="">- %1:fpr(<4 x s32>) = COPY $q1<br class="">- %4:gpr(s32) = G_CONSTANT i32 5<br class="">- %5:gpr(s32) = G_CONSTANT i32 7<br class="">- %6:gpr(s32) = G_CONSTANT i32 1<br class="">- %7:gpr(s32) = G_CONSTANT i32 0<br class="">- %3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %7(s32)<br class="">- %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)<br class="">- $q0 = COPY %2(<4 x s32>)<br class="">- RET_ReallyLR implicit $q0<br class="">-<br class="">-...<br class="">----<br class="">-name: shuffle_v2i64<br class="">-alignment: 2<br class="">-legalized: true<br class="">-regBankSelected: true<br class="">-tracksRegLiveness: true<br class="">-registers:<br class="">- - { id: 0, class: fpr }<br class="">- - { id: 1, class: fpr }<br class="">- - { id: 2, class: fpr }<br class="">- - { id: 3, class: fpr }<br class="">- - { id: 4, class: gpr }<br class="">-body: |<br class="">- bb.1 (%ir-block.0):<br class="">- liveins: $q0, $q1<br class="">-<br class="">- ; CHECK-LABEL: name: shuffle_v2i64<br class="">- ; CHECK: constants:<br class="">- ; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'<br class="">- ; CHECK: alignment: 8<br class="">- ; CHECK: isTargetSpecific: false<br class="">- ; CHECK: liveins: $q0, $q1<br class="">- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0<br class="">- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1<br class="">- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0<br class="">- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0<br class="">- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1<br class="">- ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]<br class="">- ; CHECK: $q0 = COPY [[TBLv16i8Two]]<br class="">- ; CHECK: RET_ReallyLR implicit $q0<br class="">- %0:fpr(<2 x s64>) = COPY $q0<br class="">- %1:fpr(<2 x s64>) = COPY $q1<br class="">- %4:gpr(s32) = G_CONSTANT i32 0<br class="">- %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)<br class="">- %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>)<br class="">- $q0 = COPY %2(<2 x s64>)<br class="">- RET_ReallyLR implicit $q0<br class="">-<br class="">-...<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a><br class=""><a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank" class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a></blockquote></div></div></blockquote></div><br class=""></div></body></html>