<div><div dir="auto">SDLoc is not just debug info; it also stores the ‘IROrder’. IIRC the IROrder may affect how the DAG is linearized at the end of ISel.</div></div><div><br><div class="gmail_quote"><div dir="ltr">On Fri, 7 Dec 2018 at 00:04, Sanjay Patel via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: spatel<br>
Date: Thu Dec 6 16:01:57 2018<br>
New Revision: 348552<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=348552&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=348552&view=rev</a><br>
Log:<br>
[DAGCombiner] use root SDLoc for all nodes created by logic fold<br>
<br>
If this is not a valid way to assign an SDLoc, then we get this<br>
wrong all over SDAG.<br>
<br>
I don't know enough about the SDAG to explain this. IIUC, theoretically,<br>
debug info is not supposed to affect codegen. But here it has clearly<br>
affected 3 different targets, and the x86 change is an actual improvement.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll<br>
llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll<br>
llvm/trunk/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=348552&r1=348551&r2=348552&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=348552&r1=348551&r2=348552&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Dec 6 16:01:57 2018<br>
@@ -3754,7 +3754,7 @@ SDValue DAGCombiner::hoistLogicOpWithSam<br>
return SDValue();<br>
}<br>
// logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)<br>
- SDValue Logic = DAG.getNode(LogicOpcode, SDLoc(N0), XVT, X, Y);<br>
+ SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);<br>
AddToWorklist(Logic.getNode());<br>
return DAG.getNode(HandOpcode, DL, VT, Logic);<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll?rev=348552&r1=348551&r2=348552&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll?rev=348552&r1=348551&r2=348552&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll Thu Dec 6 16:01:57 2018<br>
@@ -65,9 +65,9 @@ define i64 @out64(i64 %x, i64 %y, i64 %m<br>
define i8 @in8(i8 %x, i8 %y, i8 %mask) {<br>
; CHECK-LABEL: in8:<br>
; CHECK: // %bb.0:<br>
-; CHECK-NEXT: and w8, w0, w2<br>
-; CHECK-NEXT: bic w9, w1, w2<br>
-; CHECK-NEXT: orr w0, w8, w9<br>
+; CHECK-NEXT: bic w8, w1, w2<br>
+; CHECK-NEXT: and w9, w0, w2<br>
+; CHECK-NEXT: orr w0, w9, w8<br>
; CHECK-NEXT: ret<br>
%n0 = xor i8 %x, %y<br>
%n1 = and i8 %n0, %mask<br>
@@ -78,9 +78,9 @@ define i8 @in8(i8 %x, i8 %y, i8 %mask) {<br>
define i16 @in16(i16 %x, i16 %y, i16 %mask) {<br>
; CHECK-LABEL: in16:<br>
; CHECK: // %bb.0:<br>
-; CHECK-NEXT: and w8, w0, w2<br>
-; CHECK-NEXT: bic w9, w1, w2<br>
-; CHECK-NEXT: orr w0, w8, w9<br>
+; CHECK-NEXT: bic w8, w1, w2<br>
+; CHECK-NEXT: and w9, w0, w2<br>
+; CHECK-NEXT: orr w0, w9, w8<br>
; CHECK-NEXT: ret<br>
%n0 = xor i16 %x, %y<br>
%n1 = and i16 %n0, %mask<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll?rev=348552&r1=348551&r2=348552&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll?rev=348552&r1=348551&r2=348552&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll Thu Dec 6 16:01:57 2018<br>
@@ -435,9 +435,9 @@ define zeroext i1 @ne_neg1_and_ne_zero(i<br>
define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {<br>
; CHECK-LABEL: and_eq:<br>
; CHECK: # %bb.0:<br>
-; CHECK-NEXT: xor 5, 5, 6<br>
; CHECK-NEXT: xor 3, 3, 4<br>
-; CHECK-NEXT: or 3, 3, 5<br>
+; CHECK-NEXT: xor 4, 5, 6<br>
+; CHECK-NEXT: or 3, 3, 4<br>
; CHECK-NEXT: cntlzw 3, 3<br>
; CHECK-NEXT: srwi 3, 3, 5<br>
; CHECK-NEXT: blr<br>
@@ -450,9 +450,9 @@ define zeroext i1 @and_eq(i16 zeroext %<br>
define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {<br>
; CHECK-LABEL: or_ne:<br>
; CHECK: # %bb.0:<br>
-; CHECK-NEXT: xor 5, 5, 6<br>
; CHECK-NEXT: xor 3, 3, 4<br>
-; CHECK-NEXT: or 3, 3, 5<br>
+; CHECK-NEXT: xor 4, 5, 6<br>
+; CHECK-NEXT: or 3, 3, 4<br>
; CHECK-NEXT: cntlzw 3, 3<br>
; CHECK-NEXT: srwi 3, 3, 5<br>
; CHECK-NEXT: xori 3, 3, 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll?rev=348552&r1=348551&r2=348552&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll?rev=348552&r1=348551&r2=348552&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll Thu Dec 6 16:01:57 2018<br>
@@ -38,8 +38,8 @@ define <2 x i8> @out_v2i8(<2 x i8> %x, <<br>
; CHECK-BASELINE-LABEL: out_v2i8:<br>
; CHECK-BASELINE: # %bb.0:<br>
; CHECK-BASELINE-NEXT: movl %r8d, %eax<br>
-; CHECK-BASELINE-NEXT: andl %r8d, %edi<br>
; CHECK-BASELINE-NEXT: andl %r9d, %esi<br>
+; CHECK-BASELINE-NEXT: andl %r8d, %edi<br>
; CHECK-BASELINE-NEXT: notb %al<br>
; CHECK-BASELINE-NEXT: notb %r9b<br>
; CHECK-BASELINE-NEXT: andb %cl, %r9b<br>
@@ -53,8 +53,8 @@ define <2 x i8> @out_v2i8(<2 x i8> %x, <<br>
; CHECK-SSE1-LABEL: out_v2i8:<br>
; CHECK-SSE1: # %bb.0:<br>
; CHECK-SSE1-NEXT: movl %r8d, %eax<br>
-; CHECK-SSE1-NEXT: andl %r8d, %edi<br>
; CHECK-SSE1-NEXT: andl %r9d, %esi<br>
+; CHECK-SSE1-NEXT: andl %r8d, %edi<br>
; CHECK-SSE1-NEXT: notb %al<br>
; CHECK-SSE1-NEXT: notb %r9b<br>
; CHECK-SSE1-NEXT: andb %cl, %r9b<br>
@@ -2587,12 +2587,12 @@ define <2 x i8> @in_v2i8(<2 x i8> %x, <2<br>
; CHECK-BASELINE-LABEL: in_v2i8:<br>
; CHECK-BASELINE: # %bb.0:<br>
; CHECK-BASELINE-NEXT: movl %edi, %eax<br>
-; CHECK-BASELINE-NEXT: xorl %ecx, %esi<br>
; CHECK-BASELINE-NEXT: xorl %edx, %eax<br>
-; CHECK-BASELINE-NEXT: andl %r8d, %eax<br>
-; CHECK-BASELINE-NEXT: andl %r9d, %esi<br>
; CHECK-BASELINE-NEXT: xorl %ecx, %esi<br>
+; CHECK-BASELINE-NEXT: andl %r9d, %esi<br>
+; CHECK-BASELINE-NEXT: andl %r8d, %eax<br>
; CHECK-BASELINE-NEXT: xorl %edx, %eax<br>
+; CHECK-BASELINE-NEXT: xorl %ecx, %esi<br>
; CHECK-BASELINE-NEXT: # kill: def $al killed $al killed $eax<br>
; CHECK-BASELINE-NEXT: movl %esi, %edx<br>
; CHECK-BASELINE-NEXT: retq<br>
@@ -2600,12 +2600,12 @@ define <2 x i8> @in_v2i8(<2 x i8> %x, <2<br>
; CHECK-SSE1-LABEL: in_v2i8:<br>
; CHECK-SSE1: # %bb.0:<br>
; CHECK-SSE1-NEXT: movl %edi, %eax<br>
-; CHECK-SSE1-NEXT: xorl %ecx, %esi<br>
; CHECK-SSE1-NEXT: xorl %edx, %eax<br>
-; CHECK-SSE1-NEXT: andl %r8d, %eax<br>
-; CHECK-SSE1-NEXT: andl %r9d, %esi<br>
; CHECK-SSE1-NEXT: xorl %ecx, %esi<br>
+; CHECK-SSE1-NEXT: andl %r9d, %esi<br>
+; CHECK-SSE1-NEXT: andl %r8d, %eax<br>
; CHECK-SSE1-NEXT: xorl %edx, %eax<br>
+; CHECK-SSE1-NEXT: xorl %ecx, %esi<br>
; CHECK-SSE1-NEXT: # kill: def $al killed $al killed $eax<br>
; CHECK-SSE1-NEXT: movl %esi, %edx<br>
; CHECK-SSE1-NEXT: retq<br>
@@ -2650,10 +2650,10 @@ define <4 x i8> @in_v4i8(<4 x i8> %x, <4<br>
; CHECK-BASELINE-LABEL: in_v4i8:<br>
; CHECK-BASELINE: # %bb.0:<br>
; CHECK-BASELINE-NEXT: movq %rdi, %rax<br>
-; CHECK-BASELINE-NEXT: xorl %r9d, %esi<br>
; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil<br>
; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b<br>
; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b<br>
+; CHECK-BASELINE-NEXT: xorl %r9d, %esi<br>
; CHECK-BASELINE-NEXT: xorb %r11b, %dl<br>
; CHECK-BASELINE-NEXT: xorb %r10b, %cl<br>
; CHECK-BASELINE-NEXT: xorb %dil, %r8b<br>
@@ -2674,10 +2674,10 @@ define <4 x i8> @in_v4i8(<4 x i8> %x, <4<br>
; CHECK-SSE1-LABEL: in_v4i8:<br>
; CHECK-SSE1: # %bb.0:<br>
; CHECK-SSE1-NEXT: movq %rdi, %rax<br>
-; CHECK-SSE1-NEXT: xorl %r9d, %esi<br>
; CHECK-SSE1-NEXT: movb {{[0-9]+}}(%rsp), %dil<br>
; CHECK-SSE1-NEXT: movb {{[0-9]+}}(%rsp), %r10b<br>
; CHECK-SSE1-NEXT: movb {{[0-9]+}}(%rsp), %r11b<br>
+; CHECK-SSE1-NEXT: xorl %r9d, %esi<br>
; CHECK-SSE1-NEXT: xorb %r11b, %dl<br>
; CHECK-SSE1-NEXT: xorb %r10b, %cl<br>
; CHECK-SSE1-NEXT: xorb %dil, %r8b<br>
@@ -2716,12 +2716,12 @@ define <2 x i16> @in_v2i16(<2 x i16> %x,<br>
; CHECK-BASELINE-LABEL: in_v2i16:<br>
; CHECK-BASELINE: # %bb.0:<br>
; CHECK-BASELINE-NEXT: movl %edi, %eax<br>
-; CHECK-BASELINE-NEXT: xorl %ecx, %esi<br>
; CHECK-BASELINE-NEXT: xorl %edx, %eax<br>
-; CHECK-BASELINE-NEXT: andl %r8d, %eax<br>
-; CHECK-BASELINE-NEXT: andl %r9d, %esi<br>
; CHECK-BASELINE-NEXT: xorl %ecx, %esi<br>
+; CHECK-BASELINE-NEXT: andl %r9d, %esi<br>
+; CHECK-BASELINE-NEXT: andl %r8d, %eax<br>
; CHECK-BASELINE-NEXT: xorl %edx, %eax<br>
+; CHECK-BASELINE-NEXT: xorl %ecx, %esi<br>
; CHECK-BASELINE-NEXT: # kill: def $ax killed $ax killed $eax<br>
; CHECK-BASELINE-NEXT: movl %esi, %edx<br>
; CHECK-BASELINE-NEXT: retq<br>
@@ -2729,12 +2729,12 @@ define <2 x i16> @in_v2i16(<2 x i16> %x,<br>
; CHECK-SSE1-LABEL: in_v2i16:<br>
; CHECK-SSE1: # %bb.0:<br>
; CHECK-SSE1-NEXT: movl %edi, %eax<br>
-; CHECK-SSE1-NEXT: xorl %ecx, %esi<br>
; CHECK-SSE1-NEXT: xorl %edx, %eax<br>
-; CHECK-SSE1-NEXT: andl %r8d, %eax<br>
-; CHECK-SSE1-NEXT: andl %r9d, %esi<br>
; CHECK-SSE1-NEXT: xorl %ecx, %esi<br>
+; CHECK-SSE1-NEXT: andl %r9d, %esi<br>
+; CHECK-SSE1-NEXT: andl %r8d, %eax<br>
; CHECK-SSE1-NEXT: xorl %edx, %eax<br>
+; CHECK-SSE1-NEXT: xorl %ecx, %esi<br>
; CHECK-SSE1-NEXT: # kill: def $ax killed $ax killed $eax<br>
; CHECK-SSE1-NEXT: movl %esi, %edx<br>
; CHECK-SSE1-NEXT: retq<br>
@@ -2915,12 +2915,12 @@ define <4 x i16> @in_v4i16(<4 x i16> %x,<br>
; CHECK-BASELINE: # %bb.0:<br>
; CHECK-BASELINE-NEXT: movq %rdi, %rax<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d<br>
-; CHECK-BASELINE-NEXT: xorl %r10d, %r8d<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d<br>
-; CHECK-BASELINE-NEXT: xorl %r11d, %ecx<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi<br>
-; CHECK-BASELINE-NEXT: xorl %edi, %edx<br>
; CHECK-BASELINE-NEXT: xorl %r9d, %esi<br>
+; CHECK-BASELINE-NEXT: xorl %edi, %edx<br>
+; CHECK-BASELINE-NEXT: xorl %r11d, %ecx<br>
+; CHECK-BASELINE-NEXT: xorl %r10d, %r8d<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx<br>
@@ -2939,12 +2939,12 @@ define <4 x i16> @in_v4i16(<4 x i16> %x,<br>
; CHECK-SSE1: # %bb.0:<br>
; CHECK-SSE1-NEXT: movq %rdi, %rax<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r10d<br>
-; CHECK-SSE1-NEXT: xorl %r10d, %r8d<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r11d<br>
-; CHECK-SSE1-NEXT: xorl %r11d, %ecx<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %edi<br>
-; CHECK-SSE1-NEXT: xorl %edi, %edx<br>
; CHECK-SSE1-NEXT: xorl %r9d, %esi<br>
+; CHECK-SSE1-NEXT: xorl %edi, %edx<br>
+; CHECK-SSE1-NEXT: xorl %r11d, %ecx<br>
+; CHECK-SSE1-NEXT: xorl %r10d, %r8d<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r8w<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %cx<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %dx<br>
@@ -3288,15 +3288,11 @@ define <8 x i16> @in_v8i16(<8 x i16> %x,<br>
; CHECK-BASELINE-LABEL: in_v8i16:<br>
; CHECK-BASELINE: # %bb.0:<br>
; CHECK-BASELINE-NEXT: pushq %rbp<br>
-; CHECK-BASELINE-NEXT: pushq %r14<br>
; CHECK-BASELINE-NEXT: pushq %rbx<br>
; CHECK-BASELINE-NEXT: movq %rdi, %rax<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d<br>
-; CHECK-BASELINE-NEXT: xorl %r10d, %r9d<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d<br>
-; CHECK-BASELINE-NEXT: xorl %r11d, %r8d<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi<br>
-; CHECK-BASELINE-NEXT: xorl %edi, %ecx<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
; CHECK-BASELINE-NEXT: xorl %ebx, %esi<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si<br>
@@ -3305,29 +3301,32 @@ define <8 x i16> @in_v8i16(<8 x i16> %x,<br>
; CHECK-BASELINE-NEXT: xorl %ebx, %edx<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx<br>
; CHECK-BASELINE-NEXT: xorl %ebx, %edx<br>
-; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r14d<br>
+; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-BASELINE-NEXT: xorl %ebx, %ecx<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx<br>
-; CHECK-BASELINE-NEXT: xorl %edi, %ecx<br>
-; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi<br>
+; CHECK-BASELINE-NEXT: xorl %ebx, %ecx<br>
+; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-BASELINE-NEXT: xorl %ebx, %r8d<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w<br>
-; CHECK-BASELINE-NEXT: xorl %r11d, %r8d<br>
+; CHECK-BASELINE-NEXT: xorl %ebx, %r8d<br>
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-BASELINE-NEXT: xorl %ebx, %r9d<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w<br>
-; CHECK-BASELINE-NEXT: xorl %r10d, %r9d<br>
+; CHECK-BASELINE-NEXT: xorl %ebx, %r9d<br>
; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp<br>
-; CHECK-BASELINE-NEXT: xorw %bx, %bp<br>
+; CHECK-BASELINE-NEXT: xorw %di, %bp<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp<br>
-; CHECK-BASELINE-NEXT: xorl %ebx, %ebp<br>
-; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx<br>
-; CHECK-BASELINE-NEXT: xorw %di, %bx<br>
-; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx<br>
-; CHECK-BASELINE-NEXT: xorl %edi, %ebx<br>
+; CHECK-BASELINE-NEXT: xorl %edi, %ebp<br>
; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi<br>
-; CHECK-BASELINE-NEXT: xorw %r14w, %di<br>
+; CHECK-BASELINE-NEXT: xorw %r11w, %di<br>
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di<br>
-; CHECK-BASELINE-NEXT: xorl %r14d, %edi<br>
-; CHECK-BASELINE-NEXT: movw %di, 14(%rax)<br>
-; CHECK-BASELINE-NEXT: movw %bx, 12(%rax)<br>
+; CHECK-BASELINE-NEXT: xorl %r11d, %edi<br>
+; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-BASELINE-NEXT: xorw %r10w, %bx<br>
+; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx<br>
+; CHECK-BASELINE-NEXT: xorl %r10d, %ebx<br>
+; CHECK-BASELINE-NEXT: movw %bx, 14(%rax)<br>
+; CHECK-BASELINE-NEXT: movw %di, 12(%rax)<br>
; CHECK-BASELINE-NEXT: movw %bp, 10(%rax)<br>
; CHECK-BASELINE-NEXT: movw %r9w, 8(%rax)<br>
; CHECK-BASELINE-NEXT: movw %r8w, 6(%rax)<br>
@@ -3335,22 +3334,17 @@ define <8 x i16> @in_v8i16(<8 x i16> %x,<br>
; CHECK-BASELINE-NEXT: movw %dx, 2(%rax)<br>
; CHECK-BASELINE-NEXT: movw %si, (%rax)<br>
; CHECK-BASELINE-NEXT: popq %rbx<br>
-; CHECK-BASELINE-NEXT: popq %r14<br>
; CHECK-BASELINE-NEXT: popq %rbp<br>
; CHECK-BASELINE-NEXT: retq<br>
;<br>
; CHECK-SSE1-LABEL: in_v8i16:<br>
; CHECK-SSE1: # %bb.0:<br>
; CHECK-SSE1-NEXT: pushq %rbp<br>
-; CHECK-SSE1-NEXT: pushq %r14<br>
; CHECK-SSE1-NEXT: pushq %rbx<br>
; CHECK-SSE1-NEXT: movq %rdi, %rax<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r10d<br>
-; CHECK-SSE1-NEXT: xorl %r10d, %r9d<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r11d<br>
-; CHECK-SSE1-NEXT: xorl %r11d, %r8d<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %edi<br>
-; CHECK-SSE1-NEXT: xorl %edi, %ecx<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
; CHECK-SSE1-NEXT: xorl %ebx, %esi<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %si<br>
@@ -3359,29 +3353,32 @@ define <8 x i16> @in_v8i16(<8 x i16> %x,<br>
; CHECK-SSE1-NEXT: xorl %ebx, %edx<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %dx<br>
; CHECK-SSE1-NEXT: xorl %ebx, %edx<br>
-; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r14d<br>
+; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-SSE1-NEXT: xorl %ebx, %ecx<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %cx<br>
-; CHECK-SSE1-NEXT: xorl %edi, %ecx<br>
-; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %edi<br>
+; CHECK-SSE1-NEXT: xorl %ebx, %ecx<br>
+; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-SSE1-NEXT: xorl %ebx, %r8d<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r8w<br>
-; CHECK-SSE1-NEXT: xorl %r11d, %r8d<br>
+; CHECK-SSE1-NEXT: xorl %ebx, %r8d<br>
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-SSE1-NEXT: xorl %ebx, %r9d<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r9w<br>
-; CHECK-SSE1-NEXT: xorl %r10d, %r9d<br>
+; CHECK-SSE1-NEXT: xorl %ebx, %r9d<br>
; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp<br>
-; CHECK-SSE1-NEXT: xorw %bx, %bp<br>
+; CHECK-SSE1-NEXT: xorw %di, %bp<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %bp<br>
-; CHECK-SSE1-NEXT: xorl %ebx, %ebp<br>
-; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx<br>
-; CHECK-SSE1-NEXT: xorw %di, %bx<br>
-; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %bx<br>
-; CHECK-SSE1-NEXT: xorl %edi, %ebx<br>
+; CHECK-SSE1-NEXT: xorl %edi, %ebp<br>
; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %edi<br>
-; CHECK-SSE1-NEXT: xorw %r14w, %di<br>
+; CHECK-SSE1-NEXT: xorw %r11w, %di<br>
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %di<br>
-; CHECK-SSE1-NEXT: xorl %r14d, %edi<br>
-; CHECK-SSE1-NEXT: movw %di, 14(%rax)<br>
-; CHECK-SSE1-NEXT: movw %bx, 12(%rax)<br>
+; CHECK-SSE1-NEXT: xorl %r11d, %edi<br>
+; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx<br>
+; CHECK-SSE1-NEXT: xorw %r10w, %bx<br>
+; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %bx<br>
+; CHECK-SSE1-NEXT: xorl %r10d, %ebx<br>
+; CHECK-SSE1-NEXT: movw %bx, 14(%rax)<br>
+; CHECK-SSE1-NEXT: movw %di, 12(%rax)<br>
; CHECK-SSE1-NEXT: movw %bp, 10(%rax)<br>
; CHECK-SSE1-NEXT: movw %r9w, 8(%rax)<br>
; CHECK-SSE1-NEXT: movw %r8w, 6(%rax)<br>
@@ -3389,7 +3386,6 @@ define <8 x i16> @in_v8i16(<8 x i16> %x,<br>
; CHECK-SSE1-NEXT: movw %dx, 2(%rax)<br>
; CHECK-SSE1-NEXT: movw %si, (%rax)<br>
; CHECK-SSE1-NEXT: popq %rbx<br>
-; CHECK-SSE1-NEXT: popq %r14<br>
; CHECK-SSE1-NEXT: popq %rbp<br>
; CHECK-SSE1-NEXT: retq<br>
;<br>
<br>
<br>
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</blockquote></div></div>