<div dir="ltr"><div dir="ltr">Hello Diogo,<br><br>This commit broke tests on one of our builders:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/14363">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/14363</a><br>. . . <br>Failing Tests (1):<br> LLVM :: MC/AArch64/armv8.3a-complex.s<br><br>Please have a look at this?<br><br>Thanks<br><br>Galina<br></div></div><br><div class="gmail_quote"><div dir="ltr">On Mon, Dec 3, 2018 at 3:11 AM Diogo N. Sampaio via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dnsampaio<br>
Date: Mon Dec 3 03:08:13 2018<br>
New Revision: 348121<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=348121&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=348121&view=rev</a><br>
Log:<br>
[NFC][AArch64] Split out backend features<br>
<br>
This patch splits backend features currently<br>
hidden behind architecture versions.<br>
<br>
For example, currently the only way to activate<br>
complex numbers extension is targeting an v8.3<br>
architecture, where after the patch this extension<br>
can be added separately.<br>
<br>
This refactoring is required by the new command lines proposal:<br>
<a href="http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html" rel="noreferrer" target="_blank">http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html</a><br>
<br>
Reviewers: DavidSpickett, olista01, t.p.northover<br>
<br>
Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio<br>
<br>
Differential revision: <a href="https://reviews.llvm.org/D54633" rel="noreferrer" target="_blank">https://reviews.llvm.org/D54633</a><br>
<br>
<br>
Removed:<br>
llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64.td<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td<br>
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
llvm/trunk/test/MC/AArch64/armv8.2a-at.s<br>
llvm/trunk/test/MC/AArch64/armv8.2a-persistent-memory.s<br>
llvm/trunk/test/MC/AArch64/armv8.3a-complex.s<br>
llvm/trunk/test/MC/AArch64/armv8.3a-js.s<br>
llvm/trunk/test/MC/AArch64/armv8.3a-signed-pointer.s<br>
llvm/trunk/test/MC/AArch64/armv8.4a-flag.s<br>
llvm/trunk/test/MC/AArch64/armv8.4a-ldst.s<br>
llvm/trunk/test/MC/AArch64/armv8.4a-tlb.s<br>
llvm/trunk/test/MC/AArch64/armv8.4a-trace.s<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Mon Dec 3 03:08:13 2018<br>
@@ -65,6 +65,18 @@ def FeatureLSE : SubtargetFeature<"lse",<br>
def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",<br>
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;<br>
<br>
+def FeaturePAN : SubtargetFeature<<br>
+ "pan", "HasPAN", "true",<br>
+ "Enables ARM v8.1 Privileged Access-Never extension">;<br>
+<br>
+def FeatureLOR : SubtargetFeature<<br>
+ "lor", "HasLOR", "true",<br>
+ "Enables ARM v8.1 Limited Ordering Regions extension">;<br>
+<br>
+def FeatureVH : SubtargetFeature<<br>
+ "vh", "HasVH", "true",<br>
+ "Enables ARM v8.1 Virtual Host extension">;<br>
+<br>
def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",<br>
"Enable ARMv8 PMUv3 Performance Monitors extension">;<br>
<br>
@@ -77,6 +89,18 @@ def FeatureFP16FML : SubtargetFeature<"f<br>
def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",<br>
"Enable Statistical Profiling extension">;<br>
<br>
+def FeaturePAN_RWV : SubtargetFeature<<br>
+ "pan-rwv", "HasPAN_RWV", "true",<br>
+ "Enable v8.2 PAN s1e1R and s1e1W Variants",<br>
+ [FeaturePAN]>;<br>
+<br>
+// UAO PState<br>
+def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",<br>
+ "Enable v8.2 UAO PState">;<br>
+<br>
+def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",<br>
+ "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;<br>
+<br>
def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",<br>
"Enable Scalable Vector Extension (SVE) instructions">;<br>
<br>
@@ -195,6 +219,66 @@ def FeatureDotProd : SubtargetFeature<<br>
"dotprod", "HasDotProd", "true",<br>
"Enable dot product support">;<br>
<br>
+def FeaturePA : SubtargetFeature<<br>
+ "pa", "HasPA", "true",<br>
+ "Enable v8.3-A Pointer Authentication enchancement">;<br>
+<br>
+def FeatureJS : SubtargetFeature<<br>
+ "jsconv", "HasJS", "true",<br>
+ "Enable v8.3-A JavaScript FP conversion enchancement",<br>
+ [FeatureFPARMv8]>;<br>
+<br>
+def FeatureCCIDX : SubtargetFeature<<br>
+ "ccidx", "HasCCIDX", "true",<br>
+ "Enable v8.3-A Extend of the CCSIDR number of sets">;<br>
+<br>
+def FeatureComplxNum : SubtargetFeature<<br>
+ "complxnum", "HasComplxNum", "true",<br>
+ "Enable v8.3-A Floating-point complex number support",<br>
+ [FeatureNEON]>;<br>
+<br>
+def FeatureNV : SubtargetFeature<<br>
+ "nv", "HasNV", "true",<br>
+ "Enable v8.4-A Nested Virtualization Enchancement">;<br>
+<br>
+def FeatureRASv8_4 : SubtargetFeature<<br>
+ "rasv8_4", "HasRASv8_4", "true",<br>
+ "Enable v8.4-A Reliability, Availability and Serviceability extension",<br>
+ [FeatureRAS]>;<br>
+<br>
+def FeatureMPAM : SubtargetFeature<<br>
+ "mpam", "HasMPAM", "true",<br>
+ "Enable v8.4-A Memory system Partitioning and Monitoring extension">;<br>
+<br>
+def FeatureDIT : SubtargetFeature<<br>
+ "dit", "HasDIT", "true",<br>
+ "Enable v8.4-A Data Independent Timing instructions">;<br>
+<br>
+def FeatureTRACEV8_4 : SubtargetFeature<<br>
+ "tracev8.4", "HasTRACEV8_4", "true",<br>
+ "Enable v8.4-A Trace extension">;<br>
+<br>
+def FeatureAM : SubtargetFeature<<br>
+ "am", "HasAM", "true",<br>
+ "Enable v8.4-A Activity Monitors extension">;<br>
+<br>
+def FeatureSEL2 : SubtargetFeature<<br>
+ "sel2", "HasSEL2", "true",<br>
+ "Enable v8.4-A Secure Exception Level 2 extension">;<br>
+<br>
+def FeatureTLB_RMI : SubtargetFeature<<br>
+ "tlb-rmi", "HasTLB_RMI", "true",<br>
+ "Enable v8.4-A TLB Range and Maintenance Instructions">;<br>
+<br>
+def FeatureFMI : SubtargetFeature<<br>
+ "fmi", "HasFMI", "true",<br>
+ "Enable v8.4-A Flag Manipulation Instructions">;<br>
+<br>
+// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset<br>
+def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",<br>
+ "Enable v8.4-A RCPC instructions with Immediate Offsets",<br>
+ [FeatureRCPC]>;<br>
+<br>
def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",<br>
"NegativeImmediates", "false",<br>
"Convert immediates and instructions "<br>
@@ -229,7 +313,7 @@ def FeaturePredCtrl : SubtargetFeature<"<br>
"Enable execution and data prediction invalidation instructions" >;<br>
<br>
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",<br>
- "true", "Enable Cache Clean to Point of Deep Persistence" >;<br>
+ "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;<br>
<br>
def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",<br>
"true", "Enable Branch Target Identification" >;<br>
@@ -245,16 +329,22 @@ def FeatureMTE : SubtargetFeature<"mte",<br>
//<br>
<br>
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",<br>
- "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;<br>
+ "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,<br>
+ FeaturePAN, FeatureLOR, FeatureVH]>;<br>
<br>
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",<br>
- "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;<br>
+ "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, <br>
+ FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;<br>
<br>
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",<br>
- "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;<br>
+ "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,<br>
+ FeatureJS, FeatureCCIDX, FeatureComplxNum]>;<br>
<br>
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",<br>
- "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>;<br>
+ "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,<br>
+ FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,<br>
+ FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,<br>
+ FeatureFMI, FeatureRCPC_IMMO]>;<br>
<br>
def HasV8_5aOps : SubtargetFeature<<br>
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Mon Dec 3 03:08:13 2018<br>
@@ -9989,9 +9989,10 @@ class BaseSIMDThreeSameVectorComplex<bit<br>
let Inst{4-0} = Rd;<br>
}<br>
<br>
+//8.3 CompNum - Floating-point complex number support<br>
multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,<br>
string asm, SDPatternOperator OpNode>{<br>
- let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {<br>
+ let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {<br>
def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype,<br>
asm, ".4h",<br>
[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),<br>
@@ -10007,7 +10008,7 @@ multiclass SIMDThreeSameVectorComplexHSD<br>
(rottype i32:$rot)))]>;<br>
}<br>
<br>
- let Predicates = [HasV8_3a, HasNEON] in {<br>
+ let Predicates = [HasComplxNum, HasNEON] in {<br>
def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype,<br>
asm, ".2s",<br>
[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),<br>
@@ -10063,7 +10064,7 @@ class BaseSIMDThreeSameVectorTiedComplex<br>
multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,<br>
Operand rottype, string asm,<br>
SDPatternOperator OpNode> {<br>
- let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {<br>
+ let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {<br>
def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64,<br>
rottype, asm, ".4h",<br>
[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),<br>
@@ -10079,7 +10080,7 @@ multiclass SIMDThreeSameVectorTiedComple<br>
(rottype i32:$rot)))]>;<br>
}<br>
<br>
- let Predicates = [HasV8_3a, HasNEON] in {<br>
+ let Predicates = [HasComplxNum, HasNEON] in {<br>
def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64,<br>
rottype, asm, ".2s",<br>
[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),<br>
@@ -10145,7 +10146,7 @@ class BaseSIMDIndexedTiedComplex<bit Q,<br>
// classes.<br>
multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,<br>
string asm, SDPatternOperator OpNode> {<br>
- let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in {<br>
+ let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {<br>
def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,<br>
V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",<br>
".4h", ".h", []> {<br>
@@ -10161,9 +10162,9 @@ multiclass SIMDIndexedTiedComplexHSD<bit<br>
let Inst{11} = idx{1};<br>
let Inst{21} = idx{0};<br>
}<br>
- } // Predicates = [HasV8_3a,HasNEON,HasFullFP16]<br>
+ } // Predicates = HasComplxNum, HasNEON, HasFullFP16]<br>
<br>
- let Predicates = [HasV8_3a,HasNEON] in {<br>
+ let Predicates = [HasComplxNum, HasNEON] in {<br>
def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,<br>
V128, V128, V128, VectorIndexD, rottype, asm, ".4s",<br>
".4s", ".4s", ".s", []> {<br>
@@ -10171,7 +10172,7 @@ multiclass SIMDIndexedTiedComplexHSD<bit<br>
let Inst{11} = idx{0};<br>
let Inst{21} = 0;<br>
}<br>
- } // Predicates = [HasV8_3a,HasNEON]<br>
+ } // Predicates = [HasComplxNum, HasNEON]<br>
}<br>
<br>
//----------------------------------------------------------------------------<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon Dec 3 03:08:13 2018<br>
@@ -24,6 +24,54 @@ def HasV8_4a : Predicate<"Subtar<br>
AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;<br>
def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,<br>
AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;<br>
+def HasVH : Predicate<"Subtarget->hasVH()">,<br>
+ AssemblerPredicate<"FeatureVH", "vh">;<br>
+<br>
+def HasLOR : Predicate<"Subtarget->hasLOR()">,<br>
+ AssemblerPredicate<"FeatureLOR", "lor">;<br>
+<br>
+def HasPA : Predicate<"Subtarget->hasPA()">,<br>
+ AssemblerPredicate<"FeaturePA", "pa">;<br>
+<br>
+def HasJS : Predicate<"Subtarget->hasJS()">,<br>
+ AssemblerPredicate<"FeatureJS", "jsconv">;<br>
+<br>
+def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">,<br>
+ AssemblerPredicate<"FeatureCCIDX", "ccidx">;<br>
+<br>
+def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">,<br>
+ AssemblerPredicate<"FeatureComplxNum", "complxnum">;<br>
+<br>
+def HasNV : Predicate<"Subtarget->hasNV()">,<br>
+ AssemblerPredicate<"FeatureNV", "nv">;<br>
+<br>
+def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">,<br>
+ AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">;<br>
+<br>
+def HasMPAM : Predicate<"Subtarget->hasMPAM()">,<br>
+ AssemblerPredicate<"FeatureMPAM", "mpam">;<br>
+<br>
+def HasDIT : Predicate<"Subtarget->hasDIT()">,<br>
+ AssemblerPredicate<"FeatureDIT", "dit">;<br>
+<br>
+def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">,<br>
+ AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">;<br>
+<br>
+def HasAM : Predicate<"Subtarget->hasAM()">,<br>
+ AssemblerPredicate<"FeatureAM", "am">;<br>
+<br>
+def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,<br>
+ AssemblerPredicate<"FeatureSEL2", "sel2">;<br>
+<br>
+def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,<br>
+ AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">;<br>
+<br>
+def HasFMI : Predicate<"Subtarget->hasFMI()">,<br>
+ AssemblerPredicate<"FeatureFMI", "fmi">;<br>
+<br>
+def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">,<br>
+ AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">;<br>
+<br>
def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,<br>
AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;<br>
def HasNEON : Predicate<"Subtarget->hasNEON()">,<br>
@@ -510,7 +558,7 @@ def ISB : CRmSystemI<barrier_op, 0b110<br>
def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {<br>
let CRm = 0b0010;<br>
let Inst{12} = 0;<br>
- let Predicates = [HasV8_4a];<br>
+ let Predicates = [HasTRACEV8_4];<br>
}<br>
}<br>
<br>
@@ -602,7 +650,7 @@ let Uses = [LR], Defs = [LR], CRm = 0b00<br>
}<br>
<br>
// These pointer authentication isntructions require armv8.3a<br>
-let Predicates = [HasV8_3a] in {<br>
+let Predicates = [HasPA] in {<br>
multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> {<br>
def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;<br>
def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;<br>
@@ -642,17 +690,17 @@ let Predicates = [HasV8_3a] in {<br>
defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>;<br>
defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>;<br>
<br>
- // v8.3a floating point conversion for javascript<br>
- let Predicates = [HasV8_3a, HasFPARMv8] in<br>
- def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,<br>
- "fjcvtzs", []> {<br>
- let Inst{31} = 0;<br>
- }<br>
+}<br>
<br>
-} // HasV8_3a<br>
+// v8.3a floating point conversion for javascript<br>
+let Predicates = [HasJS, HasFPARMv8] in<br>
+def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,<br>
+ "fjcvtzs", []> {<br>
+ let Inst{31} = 0;<br>
+} // HasJS, HasFPARMv8<br>
<br>
// v8.4 Flag manipulation instructions<br>
-let Predicates = [HasV8_4a] in {<br>
+let Predicates = [HasFMI] in {<br>
def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {<br>
let Inst{20-5} = 0b0000001000000000;<br>
}<br>
@@ -660,7 +708,7 @@ def SETF8 : BaseFlagManipulation<0, 0,<br>
def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;<br>
def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",<br>
"{\t$Rn, $imm, $mask}">;<br>
-} // HasV8_4a<br>
+} // HasFMI<br>
<br>
// v8.5 flag manipulation instructions<br>
let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {<br>
@@ -2629,8 +2677,9 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b0<br>
[(truncstorei8 GPR32z:$Rt,<br>
(am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;<br>
<br>
-// Armv8.4 LDAPR & STLR with Immediate Offset instruction<br>
-let Predicates = [HasV8_4a] in {<br>
+// Armv8.4 Weaker Release Consistency enhancements<br>
+// LDAPR & STLR with Immediate Offset instructions<br>
+let Predicates = [HasRCPC_IMMO] in {<br>
defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>;<br>
defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>;<br>
defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;<br>
@@ -2915,7 +2964,7 @@ def STLXPX : StoreExclusivePair<0b11, 0,<br>
def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;<br>
def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;<br>
<br>
-let Predicates = [HasV8_1a] in {<br>
+let Predicates = [HasLOR] in {<br>
// v8.1a "Limited Order Region" extension load-acquire instructions<br>
def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;<br>
def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Mon Dec 3 03:08:13 2018<br>
@@ -83,6 +83,33 @@ protected:<br>
bool HasFP16FML = false;<br>
bool HasSPE = false;<br>
<br>
+ // ARMv8.1 extensions<br>
+ bool HasVH = false;<br>
+ bool HasPAN = false;<br>
+ bool HasLOR = false;<br>
+<br>
+ // ARMv8.2 extensions<br>
+ bool HasPsUAO = false;<br>
+ bool HasPAN_RWV = false;<br>
+ bool HasCCPP = false;<br>
+<br>
+ // ARMv8.3 extensions<br>
+ bool HasPA = false;<br>
+ bool HasJS = false;<br>
+ bool HasCCIDX = false;<br>
+ bool HasComplxNum = false;<br>
+<br>
+ // ARMv8.4 extensions<br>
+ bool HasNV = false;<br>
+ bool HasRASv8_4 = false;<br>
+ bool HasMPAM = false;<br>
+ bool HasDIT = false;<br>
+ bool HasTRACEV8_4 = false;<br>
+ bool HasAM = false;<br>
+ bool HasSEL2 = false;<br>
+ bool HasTLB_RMI = false;<br>
+ bool HasFMI = false;<br>
+ bool HasRCPC_IMMO = false;<br>
// ARMv8.4 Crypto extensions<br>
bool HasSM4 = true;<br>
bool HasSHA3 = true;<br>
@@ -349,6 +376,30 @@ public:<br>
<br>
bool useAA() const override { return UseAA; }<br>
<br>
+ bool hasVH() const { return HasVH; }<br>
+ bool hasPAN() const { return HasPAN; }<br>
+ bool hasLOR() const { return HasLOR; }<br>
+<br>
+ bool hasPsUAO() const { return HasPsUAO; }<br>
+ bool hasPAN_RWV() const { return HasPAN_RWV; }<br>
+ bool hasCCPP() const { return HasCCPP; }<br>
+<br>
+ bool hasPA() const { return HasPA; }<br>
+ bool hasJS() const { return HasJS; }<br>
+ bool hasCCIDX() const { return HasCCIDX; }<br>
+ bool hasComplxNum() const { return HasComplxNum; }<br>
+<br>
+ bool hasNV() const { return HasNV; }<br>
+ bool hasRASv8_4() const { return HasRASv8_4; }<br>
+ bool hasMPAM() const { return HasMPAM; }<br>
+ bool hasDIT() const { return HasDIT; }<br>
+ bool hasTRACEV8_4() const { return HasTRACEV8_4; }<br>
+ bool hasAM() const { return HasAM; }<br>
+ bool hasSEL2() const { return HasSEL2; }<br>
+ bool hasTLB_RMI() const { return HasTLB_RMI; }<br>
+ bool hasFMI() const { return HasFMI; }<br>
+ bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }<br>
+<br>
bool useSmallAddressing() const {<br>
switch (TLInfo.getTargetMachine().getCodeModel()) {<br>
case CodeModel::Kernel:<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Mon Dec 3 03:08:13 2018<br>
@@ -15,6 +15,25 @@<br>
include "llvm/TableGen/SearchableTable.td"<br>
<br>
//===----------------------------------------------------------------------===//<br>
+// Features that, for the compiler, only enable system operands and PStates<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+def HasCCPP : Predicate<"Subtarget->hasCCPP()">,<br>
+ AssemblerPredicate<"FeatureCCPP", "ccpp">;<br>
+<br>
+def HasPAN : Predicate<"Subtarget->hasPAN()">,<br>
+ AssemblerPredicate<"FeaturePAN",<br>
+ "ARM v8.1 Privileged Access-Never extension">;<br>
+<br>
+def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">,<br>
+ AssemblerPredicate<"FeaturePsUAO",<br>
+ "ARM v8.2 UAO PState extension (psuao)">;<br>
+<br>
+def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,<br>
+ AssemblerPredicate<"FeaturePAN_RWV",<br>
+ "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
// AT (address translate) instruction options.<br>
//===----------------------------------------------------------------------===//<br>
<br>
@@ -45,7 +64,7 @@ def : AT<"S12E1W", 0b100, 0b0111, 0b1000<br>
def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;<br>
def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;<br>
<br>
-let Requires = [{ {AArch64::HasV8_2aOps} }] in {<br>
+let Requires = [{ {AArch64::FeaturePAN_RWV} }] in {<br>
def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;<br>
def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;<br>
}<br>
@@ -102,7 +121,7 @@ def : DC<"CVAU", 0b011, 0b0111, 0b1011,<br>
def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;<br>
def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;<br>
<br>
-let Requires = [{ {AArch64::HasV8_2aOps} }] in<br>
+let Requires = [{ {AArch64::FeatureCCPP} }] in<br>
def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;<br>
<br>
let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in<br>
@@ -178,7 +197,7 @@ class TSB<string name, bits<4> encoding><br>
bits<4> Encoding;<br>
let Encoding = encoding;<br>
<br>
- code Requires = [{ {AArch64::HasV8_4aOps} }];<br>
+ code Requires = [{ {AArch64::FeatureTRACEV8_4} }];<br>
}<br>
<br>
def : TSB<"csync", 0>;<br>
@@ -314,13 +333,14 @@ def : PState<"SPSel", 0b00101>;<br>
def : PState<"DAIFSet", 0b11110>;<br>
def : PState<"DAIFClr", 0b11111>;<br>
// v8.1a "Privileged Access Never" extension-specific PStates<br>
-let Requires = [{ {AArch64::HasV8_1aOps} }] in<br>
+let Requires = [{ {AArch64::FeaturePAN} }] in<br>
def : PState<"PAN", 0b00100>;<br>
+<br>
// v8.2a "User Access Override" extension-specific PStates<br>
-let Requires = [{ {AArch64::HasV8_2aOps} }] in<br>
+let Requires = [{ {AArch64::FeaturePsUAO} }] in<br>
def : PState<"UAO", 0b00011>;<br>
// v8.4a timining insensitivity of data processing instructions<br>
-let Requires = [{ {AArch64::HasV8_4aOps} }] in<br>
+let Requires = [{ {AArch64::FeatureDIT} }] in<br>
def : PState<"DIT", 0b11010>;<br>
// v8.5a Spectre Mitigation<br>
let Requires = [{ {AArch64::FeatureSpecRestrict} }] in<br>
@@ -413,8 +433,9 @@ def : TLBI<"VALE3", 0b110, 0b1000<br>
def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;<br>
def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;<br>
<br>
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)<br>
+let Requires = [{ {AArch64::FeatureTLB_RMI} }] in {<br>
// Armv8.4-A Outer Sharable TLB Maintenance instructions:<br>
-let Requires = [{ {AArch64::HasV8_4aOps} }] in {<br>
// op1 CRn CRm op2<br>
def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;<br>
def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;<br>
@@ -465,7 +486,7 @@ def : TLBI<"RVAE3IS", 0b110, 0b1000<br>
def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;<br>
def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;<br>
def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;<br>
-}<br>
+} //FeatureTLB_RMI<br>
<br>
// Armv8.5-A Prediction Restriction by Context instruction options:<br>
class PRCTX<string name, bits<4> crm> : SearchableTable {<br>
@@ -540,8 +561,10 @@ def : ROSysReg<"PMCEID0_EL0", 0b1<br>
def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;<br>
def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;<br>
def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;<br>
+<br>
+//v8.3 CCIDX - extending the CCsIDr number of sets<br>
def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {<br>
- let Requires = [{ {AArch64::HasV8_3aOps} }];<br>
+ let Requires = [{ {AArch64::FeatureCCIDX} }];<br>
}<br>
def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;<br>
def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;<br>
@@ -579,9 +602,7 @@ def : ROSysReg<"ID_AA64ISAR0_EL1", 0b<br>
def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;<br>
def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;<br>
def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;<br>
-def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> {<br>
- let Requires = [{ {AArch64::HasV8_2aOps} }];<br>
-}<br>
+def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;<br>
def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;<br>
def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;<br>
def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;<br>
@@ -651,7 +672,7 @@ def : ROSysReg<"ID_AA64ZFR0_EL1", 0b1<br>
<br>
// v8.1a "Limited Ordering Regions" extension-specific system register<br>
// Op0 Op1 CRn CRm Op2<br>
-let Requires = [{ {AArch64::HasV8_1aOps} }] in<br>
+let Requires = [{ {AArch64::FeatureLOR} }] in<br>
def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;<br>
<br>
// v8.2a "RAS extension" registers<br>
@@ -1185,21 +1206,21 @@ def : RWSysReg<"ICH_LR14_EL2", 0b1<br>
def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>;<br>
<br>
// v8.1a "Privileged Access Never" extension-specific system registers<br>
-let Requires = [{ {AArch64::HasV8_1aOps} }] in<br>
+let Requires = [{ {AArch64::FeaturePAN} }] in<br>
def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;<br>
<br>
// v8.1a "Limited Ordering Regions" extension-specific system registers<br>
// Op0 Op1 CRn CRm Op2<br>
-let Requires = [{ {AArch64::HasV8_1aOps} }] in {<br>
+let Requires = [{ {AArch64::FeatureLOR} }] in {<br>
def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>;<br>
def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>;<br>
def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>;<br>
def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>;<br>
}<br>
<br>
-// v8.1a "Virtualization hos extensions" system registers<br>
+// v8.1a "Virtualization Host extensions" system registers<br>
// Op0 Op1 CRn CRm Op2<br>
-let Requires = [{ {AArch64::HasV8_1aOps} }] in {<br>
+let Requires = [{ {AArch64::FeatureVH} }] in {<br>
def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>;<br>
def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;<br>
def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>;<br>
@@ -1230,7 +1251,7 @@ def : RWSysReg<"ELR_EL12", 0b11,<br>
}<br>
// v8.2a registers<br>
// Op0 Op1 CRn CRm Op2<br>
-let Requires = [{ {AArch64::HasV8_2aOps} }] in<br>
+let Requires = [{ {AArch64::FeaturePsUAO} }] in<br>
def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;<br>
<br>
// v8.2a "Statistical Profiling extension" registers<br>
@@ -1267,7 +1288,7 @@ def : RWSysReg<"VSESR_EL2", 0b11, 0b<br>
<br>
// v8.3a "Pointer authentication extension" registers<br>
// Op0 Op1 CRn CRm Op2<br>
-let Requires = [{ {AArch64::HasV8_3aOps} }] in {<br>
+let Requires = [{ {AArch64::FeaturePA} }] in {<br>
def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>;<br>
def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>;<br>
def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>;<br>
@@ -1280,8 +1301,8 @@ def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b<br>
def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;<br>
}<br>
<br>
-let Requires = [{ {AArch64::HasV8_4aOps} }] in {<br>
-<br>
+// v8.4 "Secure Exception Level 2 extension"<br>
+let Requires = [{ {AArch64::FeatureSEL2} }] in {<br>
// v8.4a "Virtualization secure second stage translation" registers<br>
// Op0 Op1 CRn CRm Op2<br>
def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;<br>
@@ -1299,18 +1320,22 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11,<br>
// v8.4a "Virtualization debug state" registers<br>
// Op0 Op1 CRn CRm Op2<br>
def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;<br>
+} // FeatureSEL2<br>
<br>
// v8.4a RAS registers<br>
-// Op0 Op1 CRn CRm Op2<br>
+// Op0 Op1 CRn CRm Op2<br>
+let Requires = [{ {AArch64::FeatureRASv8_4} }] in {<br>
def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;<br>
def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;<br>
def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>;<br>
def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;<br>
def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;<br>
def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;<br>
+} // FeatureRASv8_4<br>
<br>
// v8.4a MPAM registers<br>
// Op0 Op1 CRn CRm Op2<br>
+let Requires = [{ {AArch64::FeatureMPAM} }] in {<br>
def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;<br>
def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;<br>
def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;<br>
@@ -1327,9 +1352,11 @@ def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b1<br>
def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;<br>
def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;<br>
def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;<br>
+} //FeatureMPAM<br>
<br>
-// v8.4a Activitiy monitor registers<br>
+// v8.4a Activitiy Monitor registers<br>
// Op0 Op1 CRn CRm Op2<br>
+let Requires = [{ {AArch64::FeatureAM} }] in {<br>
def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>;<br>
def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>;<br>
def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>;<br>
@@ -1378,6 +1405,7 @@ def : RWSysReg<"AMEVTYPER112_EL0", 0b11,<br>
def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>;<br>
def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>;<br>
def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;<br>
+} //FeatureAM<br>
<br>
// v8.4a Trace Extension registers<br>
//<br>
@@ -1386,19 +1414,24 @@ def : RWSysReg<"AMEVTYPER115_EL0", 0b11,<br>
// but they are already defined above.<br>
//<br>
// Op0 Op1 CRn CRm Op2<br>
+let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in {<br>
def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>;<br>
def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>;<br>
def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>;<br>
+} //FeatureTRACEV8_4<br>
<br>
// v8.4a Timining insensitivity of data processing instructions<br>
+// DIT: Data Independent Timing instructions<br>
// Op0 Op1 CRn CRm Op2<br>
+let Requires = [{ {AArch64::FeatureDIT} }] in {<br>
def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>;<br>
+} //FeatureDIT<br>
<br>
// v8.4a Enhanced Support for Nested Virtualization<br>
// Op0 Op1 CRn CRm Op2<br>
+let Requires = [{ {AArch64::FeatureNV} }] in {<br>
def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>;<br>
-<br>
-} // HasV8_4aOps<br>
+} //FeatureNV<br>
<br>
// SVE control registers<br>
// Op0 Op1 CRn CRm Op2<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Mon Dec 3 03:08:13 2018<br>
@@ -2813,28 +2813,29 @@ static const struct Extension {<br>
const char *Name;<br>
const FeatureBitset Features;<br>
} ExtensionMap[] = {<br>
- { "crc", {AArch64::FeatureCRC} },<br>
- { "sm4", {AArch64::FeatureSM4} },<br>
- { "sha3", {AArch64::FeatureSHA3} },<br>
- { "sha2", {AArch64::FeatureSHA2} },<br>
- { "aes", {AArch64::FeatureAES} },<br>
- { "crypto", {AArch64::FeatureCrypto} },<br>
- { "fp", {AArch64::FeatureFPARMv8} },<br>
- { "simd", {AArch64::FeatureNEON} },<br>
- { "ras", {AArch64::FeatureRAS} },<br>
- { "lse", {AArch64::FeatureLSE} },<br>
- { "predctrl", {AArch64::FeaturePredCtrl} },<br>
- { "ccdp", {AArch64::FeatureCacheDeepPersist} },<br>
- { "mte", {AArch64::FeatureMTE} },<br>
-<br>
- // FIXME: Unsupported extensions<br>
- { "pan", {} },<br>
- { "lor", {} },<br>
- { "rdma", {} },<br>
- { "profile", {} },<br>
+ {"crc", {AArch64::FeatureCRC}},<br>
+ {"sm4", {AArch64::FeatureSM4}},<br>
+ {"sha3", {AArch64::FeatureSHA3}},<br>
+ {"sha2", {AArch64::FeatureSHA2}},<br>
+ {"aes", {AArch64::FeatureAES}},<br>
+ {"crypto", {AArch64::FeatureCrypto}},<br>
+ {"fp", {AArch64::FeatureFPARMv8}},<br>
+ {"simd", {AArch64::FeatureNEON}},<br>
+ {"ras", {AArch64::FeatureRAS}},<br>
+ {"lse", {AArch64::FeatureLSE}},<br>
+ {"predctrl", {AArch64::FeaturePredCtrl}},<br>
+ {"ccdp", {AArch64::FeatureCacheDeepPersist}},<br>
+ {"mte", {AArch64::FeatureMTE}},<br>
+ {"tlb-rmi", {AArch64::FeatureTLB_RMI}},<br>
+ {"pan-rwv", {AArch64::FeaturePAN_RWV}},<br>
+ {"ccpp", {AArch64::FeatureCCPP}},<br>
+ // FIXME: Unsupported extensions<br>
+ {"pan", {}},<br>
+ {"lor", {}},<br>
+ {"rdma", {}},<br>
+ {"profile", {}},<br>
};<br>
<br>
-<br>
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {<br>
if (FBS[AArch64::HasV8_1aOps])<br>
Str += "ARMv8.1a";<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.2a-at.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-at.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-at.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.2a-at.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.2a-at.s Mon Dec 3 03:08:13 2018<br>
@@ -1,9 +1,11 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a %s -o - | FileCheck %s<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+pan-rwv %s -o - | FileCheck %s<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR<br>
<br>
at s1e1rp, x1<br>
at s1e1wp, x2<br>
// CHECK: at s1e1rp, x1 // encoding: [0x01,0x79,0x08,0xd5]<br>
// CHECK: at s1e1wp, x2 // encoding: [0x22,0x79,0x08,0xd5]<br>
-// ERROR: error: AT S1E1RP requires ARMv8.2a<br>
-// ERROR: error: AT S1E1WP requires ARMv8.2a<br>
+// ERROR: error: AT S1E1RP requires pan-rwv<br>
+// ERROR: error: AT S1E1WP requires pan-rwv<br>
<br>
Removed: llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s?rev=348120&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s?rev=348120&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s (removed)<br>
@@ -1,6 +0,0 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR<br>
-<br>
- mrs x3, id_aa64mmfr2_el1<br>
-// CHECK: mrs x3, ID_AA64MMFR2_EL1 // encoding: [0x43,0x07,0x38,0xd5]<br>
-// ERROR: error: expected readable system register<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.2a-persistent-memory.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-persistent-memory.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-persistent-memory.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.2a-persistent-memory.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.2a-persistent-memory.s Mon Dec 3 03:08:13 2018<br>
@@ -1,6 +1,7 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -o - %s | FileCheck %s<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccpp -o - %s | FileCheck %s<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR<br>
<br>
dc cvap, x7<br>
// CHECK: dc cvap, x7 // encoding: [0x27,0x7c,0x0b,0xd5]<br>
-// ERROR: error: DC CVAP requires ARMv8.2a<br>
+// ERROR: error: DC CVAP requires ccpp<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.3a-complex.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-complex.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-complex.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.3a-complex.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.3a-complex.s Mon Dec 3 03:08:13 2018<br>
@@ -1,43 +1,44 @@<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 -o - %s 2>%t | \<br>
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16<br>
// RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-NO-FP16 %s < %t<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 -o - %s 2>%t | \<br>
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP16<br>
// RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-FP16 %s < %t<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A<br>
-<br>
-<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16,+complxnum -o - %s 2>&1 | \<br>
+// RUN: FileCheck %s --check-prefix=FP16<br>
// ==== FCMLA vector ====<br>
// Types<br>
fcmla v0.4h, v1.4h, v2.4h, #0<br>
// FP16: fcmla v0.4h, v1.4h, v2.4h, #0 // encoding: [0x20,0xc4,0x42,0x2e]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.8h, v1.8h, v2.8h, #0<br>
// FP16: fcmla v0.8h, v1.8h, v2.8h, #0 // encoding: [0x20,0xc4,0x42,0x6e]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2s, v1.2s, v2.2s, #0<br>
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.4s, v1.4s, v2.4s, #0<br>
// CHECK: fcmla v0.4s, v1.4s, v2.4s, #0 // encoding: [0x20,0xc4,0x82,0x6e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2d, v1.2d, v2.2d, #0<br>
// CHECK: fcmla v0.2d, v1.2d, v2.2d, #0 // encoding: [0x20,0xc4,0xc2,0x6e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
<br>
// Rotations<br>
fcmla v0.2s, v1.2s, v2.2s, #0<br>
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2s, v1.2s, v2.2s, #90<br>
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xcc,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2s, v1.2s, v2.2s, #180<br>
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #180 // encoding: [0x20,0xd4,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2s, v1.2s, v2.2s, #270<br>
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xdc,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
<br>
// Invalid rotations<br>
fcmla v0.2s, v1.2s, v2.2s, #1<br>
@@ -52,28 +53,28 @@<br>
fcadd v0.4h, v1.4h, v2.4h, #90<br>
// FP16: fcadd v0.4h, v1.4h, v2.4h, #90 // encoding: [0x20,0xe4,0x42,0x2e]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcadd v0.8h, v1.8h, v2.8h, #90<br>
// FP16: fcadd v0.8h, v1.8h, v2.8h, #90 // encoding: [0x20,0xe4,0x42,0x6e]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcadd v0.2s, v1.2s, v2.2s, #90<br>
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcadd v0.4s, v1.4s, v2.4s, #90<br>
// CHECK: fcadd v0.4s, v1.4s, v2.4s, #90 // encoding: [0x20,0xe4,0x82,0x6e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcadd v0.2d, v1.2d, v2.2d, #90<br>
// CHECK: fcadd v0.2d, v1.2d, v2.2d, #90 // encoding: [0x20,0xe4,0xc2,0x6e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
<br>
// Rotations<br>
fcadd v0.2s, v1.2s, v2.2s, #90<br>
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcadd v0.2s, v1.2s, v2.2s, #270<br>
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xf4,0x82,0x2e]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
<br>
// Invalid rotations<br>
fcadd v0.2s, v1.2s, v2.2s, #1<br>
@@ -92,17 +93,17 @@<br>
fcmla v0.4h, v1.4h, v2.h[0], #0<br>
// FP16: fcmla v0.4h, v1.4h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x2f]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.8h, v1.8h, v2.h[0], #0<br>
// FP16: fcmla v0.8h, v1.8h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x6f]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2s, v1.2s, v2.s[0], #0<br>
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction<br>
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction<br>
fcmla v0.4s, v1.4s, v2.s[0], #0<br>
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #0 // encoding: [0x20,0x10,0x82,0x6f]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.2d, v1.2d, v2.d[0], #0<br>
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction<br>
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction<br>
@@ -110,26 +111,26 @@<br>
// Rotations<br>
fcmla v0.4s, v1.4s, v2.s[0], #90<br>
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #90 // encoding: [0x20,0x30,0x82,0x6f]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.4s, v1.4s, v2.s[0], #180<br>
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #180 // encoding: [0x20,0x50,0x82,0x6f]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.4s, v1.4s, v2.s[0], #270<br>
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #270 // encoding: [0x20,0x70,0x82,0x6f]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
<br>
// Valid indices<br>
fcmla v0.4h, v1.4h, v2.h[1], #0<br>
// FP16: fcmla v0.4h, v1.4h, v2.h[1], #0 // encoding: [0x20,0x10,0x62,0x2f]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.8h, v1.8h, v2.h[3], #0<br>
// FP16: fcmla v0.8h, v1.8h, v2.h[3], #0 // encoding: [0x20,0x18,0x62,0x6f]<br>
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16<br>
-// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
fcmla v0.4s, v1.4s, v2.s[1], #0<br>
// CHECK: fcmla v0.4s, v1.4s, v2.s[1], #0 // encoding: [0x20,0x18,0x82,0x6f]<br>
-// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a<br>
+// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: complxnum<br>
<br>
// Invalid indices<br>
fcmla v0.4h, v1.4h, v2.h[2], #0<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.3a-js.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-js.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-js.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.3a-js.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.3a-js.s Mon Dec 3 03:08:13 2018<br>
@@ -1,10 +1,20 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t<br>
-// RUN: FileCheck --check-prefix=CHECK-REQ < %t %s<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fp-armv8 < %s 2> %t<br>
-// RUN: FileCheck --check-prefix=CHECK-NOFP < %t %s<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \<br>
+// RUN: FileCheck %s<br>
+<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+jsconv -o - %s 2>&1 | \<br>
+// RUN: FileCheck %s<br>
+<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s 2>&1 | \<br>
+// RUN: FileCheck --check-prefix=CHECK-JS %s<br>
+<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+jsconv,-fp-armv8 -o - %s 2>&1 |\<br>
+// RUN: FileCheck --check-prefix=CHECK-REQ %s<br>
<br>
fjcvtzs w0, d0<br>
// CHECK: fjcvtzs w0, d0 // encoding: [0x00,0x00,0x7e,0x1e]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
-// CHECK-NOFP: error: instruction requires: fp-armv8<br>
+<br>
+// CHECK-JS: error: instruction requires: jsconv<br>
+<br>
+// NOJS: error: instruction requires: jsconv<br>
+<br>
+// CHECK-REQ: error: instruction requires: fp-armv8 jsconv<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.3a-signed-pointer.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-signed-pointer.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-signed-pointer.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.3a-signed-pointer.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.3a-signed-pointer.s Mon Dec 3 03:08:13 2018<br>
@@ -1,7 +1,11 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2> %t | FileCheck %s<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t<br>
-// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \<br>
+// RUN: FileCheck --check-prefixes=CHECK,ALL %s<br>
<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s -o - > %t.1 2>%t.2<br>
+// RUN: FileCheck --check-prefixes=ALL,NOENC %s < %t.1<br>
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t.2<br>
+<br>
+// ALL: .text<br>
mrs x0, apiakeylo_el1<br>
mrs x0, apiakeyhi_el1<br>
mrs x0, apibkeylo_el1<br>
@@ -12,28 +16,39 @@<br>
mrs x0, apdbkeyhi_el1<br>
mrs x0, apgakeylo_el1<br>
mrs x0, apgakeyhi_el1<br>
-<br>
-// CHECK: mrs x0, APIAKeyLo_EL1 // encoding: [0x00,0x21,0x38,0xd5]<br>
-// CHECK: mrs x0, APIAKeyHi_EL1 // encoding: [0x20,0x21,0x38,0xd5]<br>
-// CHECK: mrs x0, APIBKeyLo_EL1 // encoding: [0x40,0x21,0x38,0xd5]<br>
-// CHECK: mrs x0, APIBKeyHi_EL1 // encoding: [0x60,0x21,0x38,0xd5]<br>
-// CHECK: mrs x0, APDAKeyLo_EL1 // encoding: [0x00,0x22,0x38,0xd5]<br>
-// CHECK: mrs x0, APDAKeyHi_EL1 // encoding: [0x20,0x22,0x38,0xd5]<br>
-// CHECK: mrs x0, APDBKeyLo_EL1 // encoding: [0x40,0x22,0x38,0xd5]<br>
-// CHECK: mrs x0, APDBKeyHi_EL1 // encoding: [0x60,0x22,0x38,0xd5]<br>
-// CHECK: mrs x0, APGAKeyLo_EL1 // encoding: [0x00,0x23,0x38,0xd5]<br>
-// CHECK: mrs x0, APGAKeyHi_EL1 // encoding: [0x20,0x23,0x38,0xd5]<br>
+// ALL-EMPTY:<br>
+// ALL-EMPTY:<br>
+// CHECK-NEXT: mrs x0, APIAKeyLo_EL1 // encoding: [0x00,0x21,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APIAKeyHi_EL1 // encoding: [0x20,0x21,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APIBKeyLo_EL1 // encoding: [0x40,0x21,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APIBKeyHi_EL1 // encoding: [0x60,0x21,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APDAKeyLo_EL1 // encoding: [0x00,0x22,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APDAKeyHi_EL1 // encoding: [0x20,0x22,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APDBKeyLo_EL1 // encoding: [0x40,0x22,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APDBKeyHi_EL1 // encoding: [0x60,0x22,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APGAKeyLo_EL1 // encoding: [0x00,0x23,0x38,0xd5]<br>
+// CHECK-NEXT: mrs x0, APGAKeyHi_EL1 // encoding: [0x20,0x23,0x38,0xd5]<br>
<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apiakeylo_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apiakeyhi_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apibkeylo_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apibkeyhi_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apdakeylo_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apdakeyhi_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apdbkeylo_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apdbkeyhi_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apgakeylo_el1<br>
// CHECK-REQ: error: expected readable system register<br>
+// CHECK-REQ-NEXT: mrs x0, apgakeyhi_el1<br>
<br>
msr apiakeylo_el1, x0<br>
msr apiakeyhi_el1, x0<br>
@@ -45,191 +60,249 @@<br>
msr apdbkeyhi_el1, x0<br>
msr apgakeylo_el1, x0<br>
msr apgakeyhi_el1, x0<br>
-<br>
-// CHECK: msr APIAKeyLo_EL1, x0 // encoding: [0x00,0x21,0x18,0xd5]<br>
-// CHECK: msr APIAKeyHi_EL1, x0 // encoding: [0x20,0x21,0x18,0xd5]<br>
-// CHECK: msr APIBKeyLo_EL1, x0 // encoding: [0x40,0x21,0x18,0xd5]<br>
-// CHECK: msr APIBKeyHi_EL1, x0 // encoding: [0x60,0x21,0x18,0xd5]<br>
-// CHECK: msr APDAKeyLo_EL1, x0 // encoding: [0x00,0x22,0x18,0xd5]<br>
-// CHECK: msr APDAKeyHi_EL1, x0 // encoding: [0x20,0x22,0x18,0xd5]<br>
-// CHECK: msr APDBKeyLo_EL1, x0 // encoding: [0x40,0x22,0x18,0xd5]<br>
-// CHECK: msr APDBKeyHi_EL1, x0 // encoding: [0x60,0x22,0x18,0xd5]<br>
-// CHECK: msr APGAKeyLo_EL1, x0 // encoding: [0x00,0x23,0x18,0xd5]<br>
-// CHECK: msr APGAKeyHi_EL1, x0 // encoding: [0x20,0x23,0x18,0xd5]<br>
+// ALL-EMPTY:<br>
+// ALL-EMPTY:<br>
+// CHECK-NEXT: msr APIAKeyLo_EL1, x0 // encoding: [0x00,0x21,0x18,0xd5]<br>
+// CHECK-NEXT: msr APIAKeyHi_EL1, x0 // encoding: [0x20,0x21,0x18,0xd5]<br>
+// CHECK-NEXT: msr APIBKeyLo_EL1, x0 // encoding: [0x40,0x21,0x18,0xd5]<br>
+// CHECK-NEXT: msr APIBKeyHi_EL1, x0 // encoding: [0x60,0x21,0x18,0xd5]<br>
+// CHECK-NEXT: msr APDAKeyLo_EL1, x0 // encoding: [0x00,0x22,0x18,0xd5]<br>
+// CHECK-NEXT: msr APDAKeyHi_EL1, x0 // encoding: [0x20,0x22,0x18,0xd5]<br>
+// CHECK-NEXT: msr APDBKeyLo_EL1, x0 // encoding: [0x40,0x22,0x18,0xd5]<br>
+// CHECK-NEXT: msr APDBKeyHi_EL1, x0 // encoding: [0x60,0x22,0x18,0xd5]<br>
+// CHECK-NEXT: msr APGAKeyLo_EL1, x0 // encoding: [0x00,0x23,0x18,0xd5]<br>
+// CHECK-NEXT: msr APGAKeyHi_EL1, x0 // encoding: [0x20,0x23,0x18,0xd5]<br>
<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apiakeylo_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apiakeyhi_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apibkeylo_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apibkeyhi_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apdakeylo_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apdakeyhi_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apdbkeylo_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apdbkeyhi_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apgakeylo_el1, x0<br>
// CHECK-REQ: error: expected writable system register or pstate<br>
+// CHECK-REQ-NEXT: msr apgakeyhi_el1, x0<br>
<br>
+// ALL-EMPTY:<br>
+// ALL-EMPTY:<br>
paciasp<br>
-// CHECK: paciasp // encoding: [0x3f,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: paciasp // encoding: [0x3f,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: paciasp<br>
autiasp<br>
-// CHECK: autiasp // encoding: [0xbf,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autiasp // encoding: [0xbf,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: autiasp<br>
paciaz<br>
-// CHECK: paciaz // encoding: [0x1f,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: paciaz // encoding: [0x1f,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: paciaz<br>
autiaz<br>
-// CHECK: autiaz // encoding: [0x9f,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autiaz // encoding: [0x9f,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: autiaz<br>
pacia1716<br>
-// CHECK: pacia1716 // encoding: [0x1f,0x21,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacia1716 // encoding: [0x1f,0x21,0x03,0xd5]<br>
+// NOENC-NEXT: pacia1716<br>
autia1716<br>
-// CHECK: autia1716 // encoding: [0x9f,0x21,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autia1716 // encoding: [0x9f,0x21,0x03,0xd5]<br>
+// NOENC-NEXT: autia1716<br>
pacibsp<br>
-// CHECK: pacibsp // encoding: [0x7f,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacibsp // encoding: [0x7f,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: pacibsp<br>
autibsp<br>
-// CHECK: autibsp // encoding: [0xff,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autibsp // encoding: [0xff,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: autibsp<br>
pacibz<br>
-// CHECK: pacibz // encoding: [0x5f,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacibz // encoding: [0x5f,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: pacibz<br>
autibz<br>
-// CHECK: autibz // encoding: [0xdf,0x23,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autibz // encoding: [0xdf,0x23,0x03,0xd5]<br>
+// NOENC-NEXT: autibz<br>
pacib1716<br>
-// CHECK: pacib1716 // encoding: [0x5f,0x21,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacib1716 // encoding: [0x5f,0x21,0x03,0xd5]<br>
+// NOENC-NEXT: pacib1716<br>
autib1716<br>
-// CHECK: autib1716 // encoding: [0xdf,0x21,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autib1716 // encoding: [0xdf,0x21,0x03,0xd5]<br>
+// NOENC-NEXT: autib1716<br>
xpaclri<br>
-// CHECK: xpaclri // encoding: [0xff,0x20,0x03,0xd5]<br>
-// CHECK-REQ-NOT: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: xpaclri // encoding: [0xff,0x20,0x03,0xd5]<br>
+// NOENC-NEXT: xpaclri<br>
<br>
+// ALL-EMPTY:<br>
pacia x0, x1<br>
-// CHECK: pacia x0, x1 // encoding: [0x20,0x00,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacia x0, x1 // encoding: [0x20,0x00,0xc1,0xda]<br>
+// CHECK-REQ-NEXT: ^<br>
+// CHECK-REQ-NEXT: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacia x0, x1<br>
autia x0, x1<br>
-// CHECK: autia x0, x1 // encoding: [0x20,0x10,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autia x0, x1 // encoding: [0x20,0x10,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autia x0, x1<br>
pacda x0, x1<br>
-// CHECK: pacda x0, x1 // encoding: [0x20,0x08,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacda x0, x1 // encoding: [0x20,0x08,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacda x0, x1<br>
autda x0, x1<br>
-// CHECK: autda x0, x1 // encoding: [0x20,0x18,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autda x0, x1 // encoding: [0x20,0x18,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autda x0, x1<br>
pacib x0, x1<br>
-// CHECK: pacib x0, x1 // encoding: [0x20,0x04,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacib x0, x1 // encoding: [0x20,0x04,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacib x0, x1<br>
autib x0, x1<br>
-// CHECK: autib x0, x1 // encoding: [0x20,0x14,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autib x0, x1 // encoding: [0x20,0x14,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autib x0, x1<br>
pacdb x0, x1<br>
-// CHECK: pacdb x0, x1 // encoding: [0x20,0x0c,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacdb x0, x1 // encoding: [0x20,0x0c,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacdb x0, x1<br>
autdb x0, x1<br>
-// CHECK: autdb x0, x1 // encoding: [0x20,0x1c,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autdb x0, x1 // encoding: [0x20,0x1c,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autdb x0, x1<br>
pacga x0, x1, x2<br>
-// CHECK: pacga x0, x1, x2 // encoding: [0x20,0x30,0xc2,0x9a]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacga x0, x1, x2 // encoding: [0x20,0x30,0xc2,0x9a]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacga x0, x1, x2<br>
paciza x0<br>
-// CHECK: paciza x0 // encoding: [0xe0,0x23,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: paciza x0 // encoding: [0xe0,0x23,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: paciza x0<br>
autiza x0<br>
-// CHECK: autiza x0 // encoding: [0xe0,0x33,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autiza x0 // encoding: [0xe0,0x33,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autiza x0<br>
pacdza x0<br>
-// CHECK: pacdza x0 // encoding: [0xe0,0x2b,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacdza x0 // encoding: [0xe0,0x2b,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacdza x0<br>
autdza x0<br>
-// CHECK: autdza x0 // encoding: [0xe0,0x3b,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autdza x0 // encoding: [0xe0,0x3b,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autdza x0<br>
pacizb x0<br>
-// CHECK: pacizb x0 // encoding: [0xe0,0x27,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacizb x0 // encoding: [0xe0,0x27,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacizb x0<br>
autizb x0<br>
-// CHECK: autizb x0 // encoding: [0xe0,0x37,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autizb x0 // encoding: [0xe0,0x37,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autizb x0<br>
pacdzb x0<br>
-// CHECK: pacdzb x0 // encoding: [0xe0,0x2f,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: pacdzb x0 // encoding: [0xe0,0x2f,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: pacdzb x0<br>
autdzb x0<br>
-// CHECK: autdzb x0 // encoding: [0xe0,0x3f,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: autdzb x0 // encoding: [0xe0,0x3f,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: autdzb x0<br>
xpaci x0<br>
-// CHECK: xpaci x0 // encoding: [0xe0,0x43,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: xpaci x0 // encoding: [0xe0,0x43,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: xpaci x0<br>
xpacd x0<br>
-// CHECK: xpacd x0 // encoding: [0xe0,0x47,0xc1,0xda]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: xpacd x0 // encoding: [0xe0,0x47,0xc1,0xda]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: xpacd x0<br>
<br>
braa x0, x1<br>
-// CHECK: braa x0, x1 // encoding: [0x01,0x08,0x1f,0xd7]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-EMPTY:<br>
+// CHECK-NEXT: braa x0, x1 // encoding: [0x01,0x08,0x1f,0xd7]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: braa x0, x1<br>
brab x0, x1<br>
-// CHECK: brab x0, x1 // encoding: [0x01,0x0c,0x1f,0xd7]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: brab x0, x1 // encoding: [0x01,0x0c,0x1f,0xd7]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: brab x0, x1<br>
blraa x0, x1<br>
-// CHECK: blraa x0, x1 // encoding: [0x01,0x08,0x3f,0xd7]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: blraa x0, x1 // encoding: [0x01,0x08,0x3f,0xd7]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: blraa x0, x1<br>
blrab x0, x1<br>
-// CHECK: blrab x0, x1 // encoding: [0x01,0x0c,0x3f,0xd7]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: blrab x0, x1 // encoding: [0x01,0x0c,0x3f,0xd7]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: blrab x0, x1<br>
<br>
braaz x0<br>
-// CHECK: braaz x0 // encoding: [0x1f,0x08,0x1f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-EMPTY:<br>
+// CHECK-NEXT: braaz x0 // encoding: [0x1f,0x08,0x1f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: braaz x0<br>
brabz x0<br>
-// CHECK: brabz x0 // encoding: [0x1f,0x0c,0x1f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: brabz x0 // encoding: [0x1f,0x0c,0x1f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: brabz x0<br>
blraaz x0<br>
-// CHECK: blraaz x0 // encoding: [0x1f,0x08,0x3f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: blraaz x0 // encoding: [0x1f,0x08,0x3f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: blraaz x0<br>
blrabz x0<br>
-// CHECK: blrabz x0 // encoding: [0x1f,0x0c,0x3f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: blrabz x0 // encoding: [0x1f,0x0c,0x3f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: blrabz x0<br>
retaa<br>
-// CHECK: retaa // encoding: [0xff,0x0b,0x5f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: retaa // encoding: [0xff,0x0b,0x5f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: retaa<br>
retab<br>
-// CHECK: retab // encoding: [0xff,0x0f,0x5f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: retab // encoding: [0xff,0x0f,0x5f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: retab<br>
eretaa<br>
-// CHECK: eretaa // encoding: [0xff,0x0b,0x9f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: eretaa // encoding: [0xff,0x0b,0x9f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: eretaa<br>
eretab<br>
-// CHECK: eretab // encoding: [0xff,0x0f,0x9f,0xd6]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: eretab // encoding: [0xff,0x0f,0x9f,0xd6]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: eretab<br>
ldraa x0, [x1, 4088]<br>
-// CHECK: ldraa x0, [x1, #4088] // encoding: [0x20,0xf4,0x3f,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldraa x0, [x1, #4088] // encoding: [0x20,0xf4,0x3f,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldraa x0, [x1, 4088]<br>
ldraa x0, [x1, -4096]<br>
-// CHECK: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldraa x0, [x1, -4096]<br>
ldrab x0, [x1, 4088]<br>
-// CHECK: ldrab x0, [x1, #4088] // encoding: [0x20,0xf4,0xbf,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldrab x0, [x1, #4088] // encoding: [0x20,0xf4,0xbf,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldrab x0, [x1, 4088]<br>
ldrab x0, [x1, -4096]<br>
-// CHECK: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldrab x0, [x1, -4096]<br>
ldraa x0, [x1, 4088]!<br>
-// CHECK: ldraa x0, [x1, #4088]! // encoding: [0x20,0xfc,0x3f,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldraa x0, [x1, #4088]! // encoding: [0x20,0xfc,0x3f,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldraa x0, [x1, 4088]!<br>
ldraa x0, [x1, -4096]!<br>
-// CHECK: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldraa x0, [x1, -4096]!<br>
ldrab x0, [x1, 4088]!<br>
-// CHECK: ldrab x0, [x1, #4088]! // encoding: [0x20,0xfc,0xbf,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldrab x0, [x1, #4088]! // encoding: [0x20,0xfc,0xbf,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldrab x0, [x1, 4088]!<br>
ldrab x0, [x1, -4096]!<br>
-// CHECK: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldrab x0, [x1, -4096]!<br>
ldraa x0, [x1]<br>
-// CHECK: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldraa x0, [x1]<br>
ldrab x0, [x1]<br>
-// CHECK: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8]<br>
-// CHECK-REQ: error: instruction requires: armv8.3a<br>
+// CHECK-NEXT: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8]<br>
+// CHECK-REQ: error: instruction requires: pa<br>
+// CHECK-REQ-NEXT: ldrab x0, [x1]<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.4a-flag.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-flag.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-flag.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.4a-flag.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.4a-flag.s Mon Dec 3 03:08:13 2018<br>
@@ -1,5 +1,14 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a %s -o - | \<br>
+// RUN: FileCheck %s<br>
+<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fmi %s -o - 2>&1 | \<br>
+// RUN: FileCheck %s<br>
+<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a %s -o - 2>&1 | \<br>
+// RUN: FileCheck %s --check-prefix=ERROR<br>
+<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-fmi %s -o - 2>&1 | \<br>
+// RUN: FileCheck %s --check-prefix=ERROR<br>
<br>
//------------------------------------------------------------------------------<br>
// Armv8.4-A flag manipulation instructions<br>
@@ -21,24 +30,24 @@<br>
//CHECK-NEXT: rmif x1, #63, #15 // encoding: [0x2f,0x84,0x1f,0xba]<br>
//CHECK-NEXT: rmif xzr, #63, #15 // encoding: [0xef,0x87,0x1f,0xba]<br>
<br>
-//CHECK-ERROR: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: cfinv<br>
-//CHECK-ERROR-NEXT: ^<br>
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: setf8 w1<br>
-//CHECK-ERROR-NEXT: ^<br>
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: setf8 wzr<br>
-//CHECK-ERROR-NEXT: ^<br>
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: setf16 w1<br>
-//CHECK-ERROR-NEXT: ^<br>
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: setf16 wzr<br>
-//CHECK-ERROR-NEXT: ^<br>
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: rmif x1, #63, #15<br>
-//CHECK-ERROR-NEXT: ^<br>
-//CHECK-ERROR-NEXT: error: instruction requires: armv8.4a<br>
-//CHECK-ERROR-NEXT: rmif xzr, #63, #15<br>
-//CHECK-ERROR-NEXT: ^<br>
+//ERROR: error: instruction requires: fmi<br>
+//ERROR-NEXT: cfinv<br>
+//ERROR-NEXT: ^<br>
+//ERROR-NEXT: error: instruction requires: fmi<br>
+//ERROR-NEXT: setf8 w1<br>
+//ERROR-NEXT: ^<br>
+//ERROR-NEXT: error: instruction requires: fmi<br>
+//ERROR-NEXT: setf8 wzr<br>
+//ERROR-NEXT: ^<br>
+//ERROR-NEXT: error: instruction requires: fmi<br>
+//ERROR-NEXT: setf16 w1<br>
+//ERROR-NEXT: ^<br>
+//ERROR-NEXT: error: instruction requires: fmi<br>
+//ERROR-NEXT: setf16 wzr<br>
+//ERROR-NEXT: ^<br>
+//ERROR-NEXT: error: instruction requires: fmi<br>
+//ERROR-NEXT: rmif x1, #63, #15<br>
+//ERROR-NEXT: ^<br>
+//ERROR-NEXT: error: instruction requires: fmi<br>
+//ERROR-NEXT: rmif xzr, #63, #15<br>
+//ERROR-NEXT: ^<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.4a-ldst.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-ldst.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-ldst.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.4a-ldst.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.4a-ldst.s Mon Dec 3 03:08:13 2018<br>
@@ -1,5 +1,8 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - %s | FileCheck %s<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a,+rcpc-immo -o - %s 2>&1 | FileCheck %s<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-rcpc-immo -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84<br>
<br>
//------------------------------------------------------------------------------<br>
// Armv8.4-A LDAPR and STLR instructions with immediate offsets<br>
@@ -140,168 +143,168 @@ ldapur x14, [sp, #9]<br>
//CHECK-NEXT: ldapur x13, [x4, #255] // encoding: [0x8d,0xf0,0x4f,0xd9]<br>
//CHECK-NEXT: ldapur x14, [sp, #9] // encoding: [0xee,0x93,0x40,0xd9]<br>
<br>
-//CHECK-NO-V84: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLURB WZR, [X10]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLURB W1, [X10]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLURB W1, [X10, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: stlurb w2, [x11, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLURB W3, [SP, #-3]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapurb wzr, [x12]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapurb w4, [x12]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapurb w4, [x12, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURB W5, [X13, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURB W6, [SP, #-2]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSB W7, [X14]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSB W7, [X14, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursb w8, [x15, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursb w9, [sp, #-1]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSB X0, [X16]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSB X0, [X16, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSB X1, [X17, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursb x2, [sp, #0]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursb x2, [sp]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: stlurh w10, [x18]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: stlurh w10, [x18, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLURH W11, [X19, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLURH W12, [SP, #1]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURH W13, [X20]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURH W13, [X20, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapurh w14, [x21, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURH W15, [SP, #2]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSH W16, [X22]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSH W16, [X22, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSH W17, [X23, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursh w18, [sp, #3]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursh x3, [x24]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursh x3, [x24, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSH X4, [X25, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSH X5, [SP, #4]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLUR W19, [X26]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLUR W19, [X26, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: stlur w20, [x27, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLUR W21, [SP, #5]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPUR W22, [X28]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPUR W22, [X28, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPUR W23, [X29, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapur w24, [sp, #6]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursw x6, [x30]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapursw x6, [x30, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSW X7, [X0, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPURSW X8, [SP, #7]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLUR X9, [X1]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLUR X9, [X1, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: stlur x10, [x2, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: STLUR X11, [SP, #8]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPUR X12, [X3]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPUR X12, [X3, #-256]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: LDAPUR X13, [X4, #255]<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: instruction requires: armv8.4a<br>
+//CHECK-NO-V84-NEXT: error: instruction requires: rcpc-immo<br>
//CHECK-NO-V84-NEXT: ldapur x14, [sp, #9]<br>
//CHECK-NO-V84-NEXT: ^<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.4a-tlb.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-tlb.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-tlb.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.4a-tlb.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.4a-tlb.s Mon Dec 3 03:08:13 2018<br>
@@ -1,6 +1,9 @@<br>
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK<br>
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+tlb-rmi < %s 2> %t | FileCheck %s --check-prefix=CHECK<br>
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s<br>
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-tlb-rmi < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84<br>
<br>
// Outer shareable TLB maintenance instructions:<br>
tlbi vmalle1os<br>
@@ -45,55 +48,55 @@ tlbi vae1os, sp<br>
//CHECK-ERROR-NEXT: tlbi vae1os, sp<br>
//CHECK-ERROR-NEXT: ^<br>
<br>
-//CHECK-NO-V84: error: TLBI VMALLE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84: error: TLBI VMALLE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vmalle1os<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vae1os, xzr<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vae1os, x0<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi aside1os, x1<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vaae1os, x2<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vale1os, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vaale1os, x4<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ipas2e1os, x5<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ipas2le1os, x6<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vae2os, x7<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vale2os, x8<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vmalls12e1os<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vae3os, x9<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi vale3os, x10<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi alle2os<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi alle1os<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi alle3os<br>
//CHECK-NO-V84-NEXT: ^<br>
<br>
@@ -168,96 +171,96 @@ tlbi rvae1, sp<br>
//CHECK-ERROR-NEXT: tlbi rvae1, sp<br>
//CHECK-ERROR-NEXT: ^<br>
<br>
-//CHECK-NO-V84: error: TLBI RVAE1 requires ARMv8.4a<br>
+//CHECK-NO-V84: error: TLBI RVAE1 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae1, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvaae1, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale1, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvaale1, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE1IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE1IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae1is, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvaae1is, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale1is, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvaale1is, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae1os, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvaae1os, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale1os, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvaale1os, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ripas2e1is, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ripas2le1is, x3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ripas2e1, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ripas2le1, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ripas2e1os, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi ripas2le1os, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae2, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale2, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae2is, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale2is, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae2os, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale2os, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae3, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale3, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae3is, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale3is, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvae3os, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale3os, X3<br>
//CHECK-NO-V84-NEXT: ^<br>
-//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a<br>
+//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires tlb-rmi<br>
//CHECK-NO-V84-NEXT: tlbi rvale3os, XZR<br>
//CHECK-NO-V84-NEXT: ^<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/armv8.4a-trace.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-trace.s?rev=348121&r1=348120&r2=348121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-trace.s?rev=348121&r1=348120&r2=348121&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AArch64/armv8.4a-trace.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/armv8.4a-trace.s Mon Dec 3 03:08:13 2018<br>
@@ -1,5 +1,14 @@<br>
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK<br>
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - 2>&1 %s | \<br>
+// RUN: FileCheck %s<br>
+<br>
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+tracev8.4 -o - 2>&1 %s | \<br>
+// RUN: FileCheck %s<br>
+<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | \<br>
+// RUN: FileCheck %s --check-prefix=CHECK-ERROR<br>
+<br>
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-tracev8.4 -o - %s 2>&1 | \<br>
+// RUN: FileCheck %s --check-prefixes NOFEATURE,CHECK-ERROR<br>
<br>
//------------------------------------------------------------------------------<br>
// ARMV8.4-A Debug, Trace and PMU Extensions<br>
@@ -45,4 +54,4 @@ tsb csync<br>
//CHECK-ERROR: mrs x0, TRFCR_EL12<br>
//CHECK-ERROR: ^<br>
<br>
-//CHECK-ERROR: error: instruction requires: armv8.4a<br>
+//CHECK-ERROR: error: instruction requires: tracev8.4<br>
<br>
<br>
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