<div dir="ltr"><div dir="ltr"><div>Thanks - if this is a blocker, feel free to revert.</div><div><br></div><div>We're missing all of the obvious shift simplifications at DAG node creation time. Those are just in the DAGCombiner. So if we process some other node before the bogus shift, we have this danger. <br></div><div><br></div><div>The solution will be similar to:</div><div><a href="https://reviews.llvm.org/rL347210">https://reviews.llvm.org/rL347210</a><br></div><div><br></div><div>We should be simplifying all shift nodes like this before they are ever created.<br></div></div></div><br><div class="gmail_quote"><div dir="ltr">On Fri, Nov 23, 2018 at 6:15 AM Mikael Holmén <<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Sanjay,<br>
<br>
The following:<br>
<br>
llc -o - bbi-21386.ll<br>
<br>
hits an assertion with this commit:<br>
<br>
.text<br>
.file "bbi-21386.ll"<br>
llc: ../include/llvm/ADT/APInt.h:979: void <br>
llvm::APInt::lshrInPlace(unsigned int): Assertion `ShiftAmt <= BitWidth <br>
&& "Invalid shift amount"' failed.<br>
Stack dump:<br>
0. Program arguments: build-all/bin/llc -o - bbi-21386.ll<br>
1. Running pass 'Function Pass Manager' on module 'bbi-21386.ll'.<br>
2. Running pass 'X86 DAG->DAG Instruction Selection' on function '@f'<br>
#0 0x0000000002180d44 PrintStackTraceSignalHandler(void*) <br>
(build-all/bin/llc+0x2180d44)<br>
#1 0x000000000217ee70 llvm::sys::RunSignalHandlers() <br>
(build-all/bin/llc+0x217ee70)<br>
#2 0x00000000021810a8 SignalHandler(int) (build-all/bin/llc+0x21810a8)<br>
#3 0x00007f6d61e9f330 __restore_rt <br>
(/lib/x86_64-linux-gnu/libpthread.so.0+0x10330)<br>
#4 0x00007f6d60a8ec37 gsignal <br>
/build/eglibc-ripdx6/eglibc-2.19/signal/../nptl/sysdeps/unix/sysv/linux/raise.c:56:0<br>
#5 0x00007f6d60a92028 abort <br>
/build/eglibc-ripdx6/eglibc-2.19/stdlib/abort.c:91:0<br>
#6 0x00007f6d60a87bf6 __assert_fail_base <br>
/build/eglibc-ripdx6/eglibc-2.19/assert/assert.c:92:0<br>
#7 0x00007f6d60a87ca2 (/lib/x86_64-linux-gnu/libc.so.6+0x2fca2)<br>
#8 0x0000000001ee1491 (anonymous <br>
namespace)::DAGCombiner::visitXOR(llvm::SDNode*) <br>
(build-all/bin/llc+0x1ee1491)<br>
#9 0x0000000001eabdd2 (anonymous <br>
namespace)::DAGCombiner::visit(llvm::SDNode*) (build-all/bin/llc+0x1eabdd2)<br>
#10 0x0000000001ea876c (anonymous <br>
namespace)::DAGCombiner::combine(llvm::SDNode*) <br>
(build-all/bin/llc+0x1ea876c)<br>
#11 0x0000000001ea7f48 llvm::SelectionDAG::Combine(llvm::CombineLevel, <br>
llvm::AAResults*, llvm::CodeGenOpt::Level) (build-all/bin/llc+0x1ea7f48)<br>
#12 0x000000000203384a llvm::SelectionDAGISel::CodeGenAndEmitDAG() <br>
(build-all/bin/llc+0x203384a)<br>
#13 0x0000000002031d23 <br>
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) <br>
(build-all/bin/llc+0x2031d23)<br>
#14 0x000000000202de9c <br>
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) <br>
(build-all/bin/llc+0x202de9c)<br>
#15 0x00000000012d5eee (anonymous <br>
namespace)::X86DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) <br>
(build-all/bin/llc+0x12d5eee)<br>
#16 0x000000000184af0d <br>
llvm::MachineFunctionPass::runOnFunction(llvm::Function&) <br>
(build-all/bin/llc+0x184af0d)<br>
#17 0x0000000001b8939d <br>
llvm::FPPassManager::runOnFunction(llvm::Function&) <br>
(build-all/bin/llc+0x1b8939d)<br>
#18 0x0000000001b89658 llvm::FPPassManager::runOnModule(llvm::Module&) <br>
(build-all/bin/llc+0x1b89658)<br>
#19 0x0000000001b89aba llvm::legacy::PassManagerImpl::run(llvm::Module&) <br>
(build-all/bin/llc+0x1b89aba)<br>
#20 0x0000000000726be5 compileModule(char**, llvm::LLVMContext&) <br>
(build-all/bin/llc+0x726be5)<br>
#21 0x0000000000724330 main (build-all/bin/llc+0x724330)<br>
#22 0x00007f6d60a79f45 __libc_start_main <br>
/build/eglibc-ripdx6/eglibc-2.19/csu/libc-start.c:321:0<br>
#23 0x00000000007223aa _start (build-all/bin/llc+0x7223aa)<br>
Abort<br>
<br>
I know the input shift is UB but<br>
<br>
%shr = lshr i32 %a, 33<br>
<br>
but shouldn't crash anyway.<br>
<br>
/Mikael<br>
<br>
On 11/22/18 8:24 PM, Sanjay Patel via llvm-commits wrote:<br>
> Author: spatel<br>
> Date: Thu Nov 22 11:24:10 2018<br>
> New Revision: 347478<br>
> <br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=347478&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=347478&view=rev</a><br>
> Log:<br>
> [DAGCombiner] form 'not' ops ahead of shifts (PR39657)<br>
> <br>
> We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'),<br>
> but that would not matter without this patch because DAGCombiner was<br>
> reversing that transform. I think we need this transform in the backend<br>
> regardless of what happens in IR to catch cases where the shift-xor<br>
> is formed late from GEP or other ops.<br>
> <br>
> <a href="https://rise4fun.com/Alive/NC1" rel="noreferrer" target="_blank">https://rise4fun.com/Alive/NC1</a><br>
> <br>
> Name: shl<br>
> Pre: (-1 << C2) == C1<br>
> %shl = shl i8 %x, C2<br>
> %r = xor i8 %shl, C1<br>
> =><br>
> %not = xor i8 %x, -1<br>
> %r = shl i8 %not, C2<br>
> <br>
> Name: shr<br>
> Pre: (-1 u>> C2) == C1<br>
> %sh = lshr i8 %x, C2<br>
> %r = xor i8 %sh, C1<br>
> =><br>
> %not = xor i8 %x, -1<br>
> %r = lshr i8 %not, C2<br>
> <br>
> <a href="https://bugs.llvm.org/show_bug.cgi?id=39657" rel="noreferrer" target="_blank">https://bugs.llvm.org/show_bug.cgi?id=39657</a><br>
> <br>
> Modified:<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> llvm/trunk/test/CodeGen/AArch64/xor.ll<br>
> llvm/trunk/test/CodeGen/ARM/pr36577.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll<br>
> llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll<br>
> llvm/trunk/test/CodeGen/X86/not-and-simplify.ll<br>
> llvm/trunk/test/CodeGen/X86/xor.ll<br>
> <br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov 22 11:24:10 2018<br>
> @@ -6133,6 +6133,23 @@ SDValue DAGCombiner::visitXOR(SDNode *N)<br>
> return DAG.getNode(ISD::AND, DL, VT, NotX, N1);<br>
> }<br>
> <br>
> + if ((N0Opcode == ISD::SRL || N0Opcode == ISD::SHL) && N0.hasOneUse()) {<br>
> + ConstantSDNode *XorC = isConstOrConstSplat(N1);<br>
> + ConstantSDNode *ShiftC = isConstOrConstSplat(N0.getOperand(1));<br>
> + if (XorC && ShiftC) {<br>
> + APInt Ones = APInt::getAllOnesValue(VT.getScalarSizeInBits());<br>
> + Ones = N0Opcode == ISD::SHL ? Ones.shl(ShiftC->getZExtValue())<br>
> + : Ones.lshr(ShiftC->getZExtValue());<br>
> + if (XorC->getAPIntValue() == Ones) {<br>
> + // If the xor constant is a shifted -1, do a 'not' before the shift:<br>
> + // xor (X << ShiftC), XorC --> (not X) << ShiftC<br>
> + // xor (X >> ShiftC), XorC --> (not X) >> ShiftC<br>
> + SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);<br>
> + return DAG.getNode(N0Opcode, DL, VT, Not, N0.getOperand(1));<br>
> + }<br>
> + }<br>
> + }<br>
> +<br>
> // fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs X)<br>
> if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {<br>
> SDValue A = N0Opcode == ISD::ADD ? N0 : N1;<br>
> @@ -6196,6 +6213,10 @@ SDValue DAGCombiner::visitXOR(SDNode *N)<br>
> /// Handle transforms common to the three shifts, when the shift amount is a<br>
> /// constant.<br>
> SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {<br>
> + // Do not turn a 'not' into a regular xor.<br>
> + if (isBitwiseNot(N->getOperand(0)))<br>
> + return SDValue();<br>
> +<br>
> SDNode *LHS = N->getOperand(0).getNode();<br>
> if (!LHS->hasOneUse()) return SDValue();<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/AArch64/xor.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/xor.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/xor.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AArch64/xor.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/AArch64/xor.ll Thu Nov 22 11:24:10 2018<br>
> @@ -4,9 +4,8 @@<br>
> define i32 @PR39657(i8* %p, i64 %x) {<br>
> ; CHECK-LABEL: PR39657:<br>
> ; CHECK: // %bb.0:<br>
> -; CHECK-NEXT: lsl x8, x1, #2<br>
> -; CHECK-NEXT: eor x8, x8, #0xfffffffffffffffc<br>
> -; CHECK-NEXT: ldr w0, [x0, x8]<br>
> +; CHECK-NEXT: mvn x8, x1<br>
> +; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]<br>
> ; CHECK-NEXT: ret<br>
> %sh = shl i64 %x, 2<br>
> %mul = xor i64 %sh, -4<br>
> <br>
> Modified: llvm/trunk/test/CodeGen/ARM/pr36577.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr36577.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr36577.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/ARM/pr36577.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/ARM/pr36577.ll Thu Nov 22 11:24:10 2018<br>
> @@ -9,12 +9,11 @@<br>
> <br>
> ; CHECK-LABEL: pr36577<br>
> ; CHECK: ldrh r0, [r0]<br>
> -; CHECK: bic r0, r1, r0, lsr #5<br>
> -; CHECK: mvn r1, #7<br>
> -; CHECK: orr r0, r0, r1<br>
> +; CHECK: mvn r0, r0, lsr #7<br>
> +; CHECK: orr r0, r1, r0, lsl #2<br>
> ; CHECK-T2: ldrh r0, [r0]<br>
> -; CHECK-T2: bic.w r0, r1, r0, lsr #5<br>
> -; CHECK-T2: orn r0, r0, #7<br>
> +; CHECK-T2: mvn.w r0, r0, lsr #7<br>
> +; CHECK-T2: orr.w r0, r1, r0, lsl #2<br>
> define dso_local arm_aapcscc i32** @pr36577() {<br>
> entry:<br>
> %0 = load i16, i16* @a, align 2<br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll Thu Nov 22 11:24:10 2018<br>
> @@ -147,9 +147,8 @@ define signext i32 @zeroEqualityTest05()<br>
> ; CHECK-NEXT: li 4, -1<br>
> ; CHECK-NEXT: isel 5, 4, 3, 0<br>
> ; CHECK-NEXT: .LBB4_3: # %endblock<br>
> -; CHECK-NEXT: srwi 3, 5, 31<br>
> -; CHECK-NEXT: xori 3, 3, 1<br>
> -; CHECK-NEXT: clrldi 3, 3, 32<br>
> +; CHECK-NEXT: nor 3, 5, 5<br>
> +; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31<br>
> ; CHECK-NEXT: blr<br>
> %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer2 to i8*), i64 16)<br>
> %call.lobit = lshr i32 %call, 31<br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll Thu Nov 22 11:24:10 2018<br>
> @@ -36,8 +36,8 @@ define zeroext i1 @test2(%class.PB2* %s_<br>
> ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28<br>
> ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28<br>
> ; CHECK-NEXT: sub 3, 4, 3<br>
> +; CHECK-NEXT: not 3, 3<br>
> ; CHECK-NEXT: rldicl 3, 3, 1, 63<br>
> -; CHECK-NEXT: xori 3, 3, 1<br>
> ; CHECK-NEXT: blr<br>
> entry:<br>
> %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*<br>
> @@ -81,8 +81,8 @@ define zeroext i1 @test4(%class.PB2* %s_<br>
> ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28<br>
> ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28<br>
> ; CHECK-NEXT: sub 3, 3, 4<br>
> +; CHECK-NEXT: not 3, 3<br>
> ; CHECK-NEXT: rldicl 3, 3, 1, 63<br>
> -; CHECK-NEXT: xori 3, 3, 1<br>
> ; CHECK-NEXT: blr<br>
> entry:<br>
> %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*<br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll Thu Nov 22 11:24:10 2018<br>
> @@ -39,8 +39,8 @@ entry:<br>
> define signext i32 @test_igesll_z(i64 %a) {<br>
> ; CHECK-LABEL: test_igesll_z:<br>
> ; CHECK: # %bb.0: # %entry<br>
> +; CHECK-NEXT: not r3, r3<br>
> ; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
> -; CHECK-NEXT: xori r3, r3, 1<br>
> ; CHECK-NEXT: blr<br>
> entry:<br>
> %cmp = icmp sgt i64 %a, -1<br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i32 %conv2<br>
> ; CHECK-LABEL: test_igeuc:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -65,8 +65,8 @@ entry:<br>
> ret void<br>
> ; CHECK_LABEL: test_igeuc_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i32 %conv<br>
> ; CHECK-LABEL: test_igeui:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -64,8 +64,8 @@ entry:<br>
> ret void<br>
> ; CHECK_LABEL: test_igeuc_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i32 %conv2<br>
> ; CHECK-LABEL: test_igeus:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -64,8 +64,8 @@ entry:<br>
> ret void<br>
> ; CHECK_LABEL: test_igeus_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i32 %conv2<br>
> ; CHECK-LABEL: test_ileuc:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -67,8 +67,8 @@ entry:<br>
> ret void<br>
> ; CHECK-LABEL: test_ileuc_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i32 %sub<br>
> ; CHECK-LABEL: test_ileui:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -67,8 +67,8 @@ entry:<br>
> ret void<br>
> ; CHECK-LABEL: test_ileui_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i32 %conv2<br>
> ; CHECK-LABEL: test_ileus:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK-NEXT: blr<br>
> }<br>
> <br>
> @@ -67,8 +67,8 @@ entry:<br>
> ret void<br>
> ; CHECK-LABEL: test_ileus_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i64 %conv3<br>
> ; CHECK-LABEL: test_llgeuc:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -64,8 +64,8 @@ entry:<br>
> ret void<br>
> ; CHECK_LABEL: test_llgeuc_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i64 %conv1<br>
> ; CHECK-LABEL: test_llgeui:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -64,8 +64,8 @@ entry:<br>
> ret void<br>
> ; CHECK_LABEL: test_igeuc_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i64 %conv3<br>
> ; CHECK-LABEL: test_llgeus:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -64,8 +64,8 @@ entry:<br>
> ret void<br>
> ; CHECK_LABEL: test_llgeus_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r3, r4<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i64 %conv3<br>
> ; CHECK-LABEL: test_llleuc:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK-NEXT: blr<br>
> }<br>
> <br>
> @@ -67,8 +67,8 @@ entry:<br>
> ret void<br>
> ; CHECK-LABEL: test_llleuc_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i64 %conv1<br>
> ; CHECK-LABEL: test_llleui:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -67,8 +67,8 @@ entry:<br>
> ret void<br>
> ; CHECK-LABEL: test_llleui_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll Thu Nov 22 11:24:10 2018<br>
> @@ -15,8 +15,8 @@ entry:<br>
> ret i64 %conv3<br>
> ; CHECK-LABEL: test_llleus:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK-NEXT: xori r3, [[REG2]], 1<br>
> +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> @@ -67,8 +67,8 @@ entry:<br>
> ret void<br>
> ; CHECK-LABEL: test_llleus_store:<br>
> ; CHECK: sub [[REG1:r[0-9]+]], r4, r3<br>
> -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63<br>
> -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1<br>
> +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]<br>
> +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63<br>
> ; CHECK: blr<br>
> }<br>
> <br>
> <br>
> Modified: llvm/trunk/test/CodeGen/X86/not-and-simplify.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/not-and-simplify.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/not-and-simplify.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/X86/not-and-simplify.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/not-and-simplify.ll Thu Nov 22 11:24:10 2018<br>
> @@ -8,8 +8,8 @@ define i32 @shrink_xor_constant1(i32 %x)<br>
> ; ALL-LABEL: shrink_xor_constant1:<br>
> ; ALL: # %bb.0:<br>
> ; ALL-NEXT: movl %edi, %eax<br>
> +; ALL-NEXT: notl %eax<br>
> ; ALL-NEXT: shrl $31, %eax<br>
> -; ALL-NEXT: xorl $1, %eax<br>
> ; ALL-NEXT: retq<br>
> %sh = lshr i32 %x, 31<br>
> %not = xor i32 %sh, -1<br>
> @@ -35,8 +35,8 @@ define i8 @shrink_xor_constant2(i8 %x) {<br>
> ; ALL-LABEL: shrink_xor_constant2:<br>
> ; ALL: # %bb.0:<br>
> ; ALL-NEXT: movl %edi, %eax<br>
> +; ALL-NEXT: notb %al<br>
> ; ALL-NEXT: shlb $5, %al<br>
> -; ALL-NEXT: xorb $-32, %al<br>
> ; ALL-NEXT: # kill: def $al killed $al killed $eax<br>
> ; ALL-NEXT: retq<br>
> %sh = shl i8 %x, 5<br>
> <br>
> Modified: llvm/trunk/test/CodeGen/X86/xor.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=347478&r1=347477&r2=347478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=347478&r1=347477&r2=347478&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/X86/xor.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/xor.ll Thu Nov 22 11:24:10 2018<br>
> @@ -493,18 +493,18 @@ define %struct.ref_s* @test12(%<a href="http://struct.re" rel="noreferrer" target="_blank">struct.re</a><br>
> ;<br>
> ; X64-LIN-LABEL: test12:<br>
> ; X64-LIN: # %bb.0:<br>
> -; X64-LIN-NEXT: xorq $-1, %rdx<br>
> -; X64-LIN-NEXT: shlq $32, %rdx<br>
> -; X64-LIN-NEXT: sarq $28, %rdx<br>
> -; X64-LIN-NEXT: leaq (%rdx,%rdi), %rax<br>
> +; X64-LIN-NEXT: notl %edx<br>
> +; X64-LIN-NEXT: movslq %edx, %rax<br>
> +; X64-LIN-NEXT: shlq $4, %rax<br>
> +; X64-LIN-NEXT: addq %rdi, %rax<br>
> ; X64-LIN-NEXT: retq<br>
> ;<br>
> ; X64-WIN-LABEL: test12:<br>
> ; X64-WIN: # %bb.0:<br>
> -; X64-WIN-NEXT: xorq $-1, %r8<br>
> -; X64-WIN-NEXT: shlq $32, %r8<br>
> -; X64-WIN-NEXT: sarq $28, %r8<br>
> -; X64-WIN-NEXT: leaq (%r8,%rcx), %rax<br>
> +; X64-WIN-NEXT: notl %r8d<br>
> +; X64-WIN-NEXT: movslq %r8d, %rax<br>
> +; X64-WIN-NEXT: shlq $4, %rax<br>
> +; X64-WIN-NEXT: addq %rcx, %rax<br>
> ; X64-WIN-NEXT: retq<br>
> %neg = shl i64 %intval, 32<br>
> %sext = xor i64 %neg, -4294967296<br>
> @@ -518,23 +518,20 @@ define i32 @PR39657(i8* %p, i64 %x) {<br>
> ; X32: # %bb.0:<br>
> ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
> ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>
> -; X32-NEXT: shll $2, %ecx<br>
> -; X32-NEXT: xorl $-4, %ecx<br>
> -; X32-NEXT: movl (%eax,%ecx), %eax<br>
> +; X32-NEXT: notl %ecx<br>
> +; X32-NEXT: movl (%eax,%ecx,4), %eax<br>
> ; X32-NEXT: retl<br>
> ;<br>
> ; X64-LIN-LABEL: PR39657:<br>
> ; X64-LIN: # %bb.0:<br>
> -; X64-LIN-NEXT: shlq $2, %rsi<br>
> -; X64-LIN-NEXT: xorq $-4, %rsi<br>
> -; X64-LIN-NEXT: movl (%rdi,%rsi), %eax<br>
> +; X64-LIN-NEXT: notq %rsi<br>
> +; X64-LIN-NEXT: movl (%rdi,%rsi,4), %eax<br>
> ; X64-LIN-NEXT: retq<br>
> ;<br>
> ; X64-WIN-LABEL: PR39657:<br>
> ; X64-WIN: # %bb.0:<br>
> -; X64-WIN-NEXT: shlq $2, %rdx<br>
> -; X64-WIN-NEXT: xorq $-4, %rdx<br>
> -; X64-WIN-NEXT: movl (%rcx,%rdx), %eax<br>
> +; X64-WIN-NEXT: notq %rdx<br>
> +; X64-WIN-NEXT: movl (%rcx,%rdx,4), %eax<br>
> ; X64-WIN-NEXT: retq<br>
> %sh = shl i64 %x, 2<br>
> %mul = xor i64 %sh, -4<br>
> <br>
> <br>
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> <br>
</blockquote></div>