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<p style="margin-top:0;margin-bottom:0">Hey Evgenii,</p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">Pushed through a minor bug fix in <span>r345962</span> for this - thanks for pinging me.</p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">Cheers,</p>
<p style="margin-top:0;margin-bottom:0">-Neil.<br>
</p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Evgenii Stepanov <eugeni.stepanov@gmail.com><br>
<b>Sent:</b> 01 November 2018 18:27:40<br>
<b>To:</b> Henning, Neil<br>
<b>Cc:</b> LLVM Commits<br>
<b>Subject:</b> Re: [llvm] r345710 - [AMDGPU] support image load/store a16</font>
<div> </div>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Hi Neil,<br>
<br>
I think this breakage is yours:<br>
<br>
<a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/7464/steps/check-llvm%20ubsan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/7464/steps/check-llvm%20ubsan/logs/stdio</a><br>
<br>
lib/Target/AMDGPU/SIISelLowering.cpp:8805:20: runtime error: shift<br>
exponent 32 is too large for 32-bit type 'int'<br>
#0 0xbdb9b3 in<br>
llvm::SITargetLowering::adjustWritemask(llvm::MachineSDNode*&,<br>
llvm::SelectionDAG&) const<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:8805:20<br>
#1 0xbdcb90 in<br>
llvm::SITargetLowering::PostISelFolding(llvm::MachineSDNode*,<br>
llvm::SelectionDAG&) const<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:8943:12<br>
#2 0xc5c944 in (anonymous<br>
namespace)::AMDGPUDAGToDAGISel::PostprocessISelDAG()<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:2137:34<br>
#3 0x28217c9 in llvm::SelectionDAGISel::DoInstructionSelection()<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1117:3<br>
#4 0x281fef5 in llvm::SelectionDAGISel::CodeGenAndEmitDAG()<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:907:5<br>
#5 0x281e5d0 in<br>
llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction,<br>
true, false, void>, false, true>,<br>
llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction,<br>
true, false, void>, false, true>, bool&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:668:3<br>
#6 0x281bca5 in<br>
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1783:7<br>
#7 0x2817586 in<br>
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:470:3<br>
#8 0x1dd321d in<br>
llvm::MachineFunctionPass::runOnFunction(llvm::Function&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/CodeGen/MachineFunctionPass.cpp:74:13<br>
#9 0x2243963 in<br>
llvm::FPPassManager::runOnFunction(llvm::Function&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/IR/LegacyPassManager.cpp:1644:27<br>
#10 0x19ac2bb in RunPassOnSCC<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/Analysis/CallGraphSCCPass.cpp:178:25<br>
#11 0x19ac2bb in RunAllPassesOnSCC<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/Analysis/CallGraphSCCPass.cpp:442<br>
#12 0x19ac2bb in (anonymous<br>
namespace)::CGPassManager::runOnModule(llvm::Module&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/Analysis/CallGraphSCCPass.cpp:498<br>
#13 0x2244447 in runOnModule<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/IR/LegacyPassManager.cpp:1744:27<br>
#14 0x2244447 in llvm::legacy::PassManagerImpl::run(llvm::Module&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/lib/IR/LegacyPassManager.cpp:1857<br>
#15 0x7b3451 in compileModule(char**, llvm::LLVMContext&)<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/tools/llc/llc.cpp:597:8<br>
#16 0x7b09eb in main<br>
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/tools/llc/llc.cpp:351:22<br>
<br>
<br>
On Wed, Oct 31, 2018 at 3:37 AM Neil Henning via llvm-commits<br>
<llvm-commits@lists.llvm.org> wrote:<br>
><br>
> Author: sheredom<br>
> Date: Wed Oct 31 03:34:48 2018<br>
> New Revision: 345710<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=345710&view=rev">http://llvm.org/viewvc/llvm-project?rev=345710&view=rev</a><br>
> Log:<br>
> [AMDGPU] support image load/store a16<br>
><br>
> Our a16 support was only enabled for sample/gather and buffer<br>
> load/store, but not for image load/store operations (which take an i16<br>
> as the pixel index rather than a half).<br>
><br>
> Fix our isel lowering and add test cases to prove it out.<br>
><br>
> Differential Revision: <a href="https://reviews.llvm.org/D53750">https://reviews.llvm.org/D53750</a><br>
><br>
> Added:<br>
> llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll<br>
> llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll<br>
> llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll<br>
> llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll<br>
> llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll<br>
> Modified:<br>
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
> llvm/trunk/test/MC/AMDGPU/mimg.s<br>
><br>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=345710&r1=345709&r2=345710&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=345710&r1=345709&r2=345710&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Wed Oct 31 03:34:48 2018<br>
> @@ -4726,9 +4726,11 @@ SDValue SITargetLowering::lowerImage(SDV<br>
> // Check for 16 bit addresses and pack if true.<br>
> unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;<br>
> MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType();<br>
> - if (VAddrVT.getScalarType() == MVT::f16 &&<br>
> + const MVT VAddrScalarVT = VAddrVT.getScalarType();<br>
> + if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&<br>
> ST->hasFeature(AMDGPU::FeatureR128A16)) {<br>
> IsA16 = true;<br>
> + const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;<br>
> for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {<br>
> SDValue AddrLo, AddrHi;<br>
> // Push back extra arguments.<br>
> @@ -4747,7 +4749,7 @@ SDValue SITargetLowering::lowerImage(SDV<br>
> AddrHi = Op.getOperand(i + 1);<br>
> i++;<br>
> }<br>
> - AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f16,<br>
> + AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,<br>
> {AddrLo, AddrHi});<br>
> AddrLo = DAG.getBitcast(MVT::i32, AddrLo);<br>
> }<br>
><br>
> Added: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll?rev=345710&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll?rev=345710&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll Wed Oct 31 03:34:48 2018<br>
> @@ -0,0 +1,530 @@<br>
> +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_2d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %t = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_3d:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %r = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_cube:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1darray:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %slice = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_2darray:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_2dmsaa:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %fragid = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_2darraymsaa:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %fragid = extractelement <2 x i16> %coords_hi, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_mip_1d:<br>
> +; GCN: image_load_mip v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %mip = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_mip_2d:<br>
> +; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_mip_3d:<br>
> +; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %r = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_mip_cube:<br>
> +; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_mip_1darray:<br>
> +; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %slice = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_mip_2darray:<br>
> +; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1d:<br>
> +; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_2d:<br>
> +; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %t = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_3d:<br>
> +; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %r = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_cube:<br>
> +; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1darray:<br>
> +; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %slice = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_2darray:<br>
> +; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_2dmsaa:<br>
> +; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %fragid = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_2darraymsaa:<br>
> +; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %fragid = extractelement <2 x i16> %coords_hi, i32 1<br>
> + call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_mip_1d:<br>
> +; GCN: image_store_mip v[0:3], v4, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %mip = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_mip_2d:<br>
> +; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_mip_3d:<br>
> +; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %r = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 1<br>
> + call void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_mip_cube:<br>
> +; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 1<br>
> + call void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_mip_1darray:<br>
> +; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %slice = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_mip_2darray:<br>
> +; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %t = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %slice = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %mip = extractelement <2 x i16> %coords_hi, i32 1<br>
> + call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_1d:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_2d:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_3d:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_cube:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_1darray:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_2darray:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_2dmsaa:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_2darraymsaa:<br>
> +; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}<br>
> +define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1d_V1:<br>
> +; GCN: image_load v0, v0, s[0:7] dmask:0x8 unorm a16<br>
> +define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret float %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1d_V2:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm a16<br>
> +define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <2 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1d_V1:<br>
> +; GCN: image_store v0, v1, s[0:7] dmask:0x2 unorm a16<br>
> +define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1d_V2:<br>
> +; GCN: image_store v[0:1], v2, s[0:7] dmask:0xc unorm a16<br>
> +define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1d_glc:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc a16{{$}}<br>
> +define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1d_slc:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc a16{{$}}<br>
> +define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load_1d_glc_slc:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc a16{{$}}<br>
> +define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1d_glc:<br>
> +; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc a16{{$}}<br>
> +define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1d_slc:<br>
> +; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc a16{{$}}<br>
> +define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store_1d_glc_slc:<br>
> +; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc a16{{$}}<br>
> +define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %s = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}getresinfo_dmask0:<br>
> +; GCN-NOT: image<br>
> +; GCN: ; return to shader part epilog<br>
> +define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) #0 {<br>
> +main_body:<br>
> + %mip = extractelement <2 x i16> %coords, i32 0<br>
> + %r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %r<br>
> +}<br>
> +<br>
> +declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +<br>
> +declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1<br>
> +<br>
> +declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +<br>
> +declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0<br>
> +<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +<br>
> +declare float @llvm.amdgcn.image.load.1d.f32.i16(i32, i16, <8 x i32>, i32, i32) #1<br>
> +declare float @llvm.amdgcn.image.load.2d.f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1<br>
> +declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32, i16, <8 x i32>, i32, i32) #1<br>
> +declare void @llvm.amdgcn.image.store.1d.f32.i16(float, i32, i16, <8 x i32>, i32, i32) #0<br>
> +declare void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float>, i32, i16, <8 x i32>, i32, i32) #0<br>
> +<br>
> +attributes #0 = { nounwind }<br>
> +attributes #1 = { nounwind readonly }<br>
> +attributes #2 = { nounwind readnone }<br>
><br>
> Added: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll?rev=345710&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll?rev=345710&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll Wed Oct 31 03:34:48 2018<br>
> @@ -0,0 +1,128 @@<br>
> +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s<br>
> +<br>
> +; GCN-LABEL: {{^}}load.f16.1d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v2f16.1d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v2f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v3f16.1d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v3f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v4f16.1d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.f16.2d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v2f16.2d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v2f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v3f16.2d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v3f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v4f16.2d:<br>
> +; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v4f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.f16.3d:<br>
> +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x1 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v2f16.3d:<br>
> +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v2f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v3f16.3d:<br>
> +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v3f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v4f16.3d:<br>
> +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm a16 d16<br>
> +define amdgpu_ps <4 x half> @load.v4f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x half> %v<br>
> +}<br>
> +<br>
> +declare <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32, i16, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2<br>
> +<br>
> +attributes #0 = { nounwind }<br>
> +attributes #1 = { nounwind readonly }<br>
><br>
> Added: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll?rev=345710&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll?rev=345710&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll Wed Oct 31 03:34:48 2018<br>
> @@ -0,0 +1,128 @@<br>
> +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s<br>
> +<br>
> +; GCN-LABEL: {{^}}load.f32.1d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x1 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v2f32.1d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x3 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v3f32.1d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x7 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v4f32.1d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.f32.2d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x1 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v2f32.2d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x3 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v3f32.2d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x7 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v4f32.2d:<br>
> +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.f32.3d:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x1 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v2f32.3d:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x3 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v3f32.3d:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x7 unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}load.v4f32.3d:<br>
> +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps <4 x float> @load.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret <4 x float> %v<br>
> +}<br>
> +<br>
> +declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #2<br>
> +declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2<br>
> +<br>
> +attributes #0 = { nounwind }<br>
> +attributes #1 = { nounwind readonly }<br>
><br>
> Added: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll?rev=345710&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll?rev=345710&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll Wed Oct 31 03:34:48 2018<br>
> @@ -0,0 +1,140 @@<br>
> +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s<br>
> +<br>
> +; GCN-LABEL: {{^}}store.f16.1d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16<br>
> +define amdgpu_ps void @store.f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v2f16.1d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16<br>
> +define amdgpu_ps void @store.v2f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v3f16.1d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16<br>
> +define amdgpu_ps void @store.v3f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v4f16.1d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16<br>
> +define amdgpu_ps void @store.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.f16.2d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16<br>
> +define amdgpu_ps void @store.f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v2f16.2d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16<br>
> +define amdgpu_ps void @store.v2f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v3f16.2d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16<br>
> +define amdgpu_ps void @store.v3f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v4f16.2d:<br>
> +; GCN: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16<br>
> +define amdgpu_ps void @store.v4f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.f16.3d:<br>
> +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x1 unorm a16 d16<br>
> +define amdgpu_ps void @store.f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v2f16.3d:<br>
> +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm a16 d16<br>
> +define amdgpu_ps void @store.v2f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v3f16.3d:<br>
> +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 unorm a16 d16<br>
> +define amdgpu_ps void @store.v3f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v4f16.3d:<br>
> +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0xf unorm a16 d16<br>
> +define amdgpu_ps void @store.v4f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + %bitcast = bitcast <2 x i32> %val to <4 x half><br>
> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +declare void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half>, i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half>, i32, i16, i16, <8 x i32>, i32, i32) #2<br>
> +declare void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2<br>
> +<br>
> +attributes #0 = { nounwind }<br>
> +attributes #1 = { nounwind readonly }<br>
><br>
> Added: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll?rev=345710&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll?rev=345710&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll Wed Oct 31 03:34:48 2018<br>
> @@ -0,0 +1,128 @@<br>
> +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s<br>
> +<br>
> +; GCN-LABEL: {{^}}store.f32.1d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16<br>
> +define amdgpu_ps void @store.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v2f32.1d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x3 unorm a16<br>
> +define amdgpu_ps void @store.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v3f32.1d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x7 unorm a16<br>
> +define amdgpu_ps void @store.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v4f32.1d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.f32.2d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16<br>
> +define amdgpu_ps void @store.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v2f32.2d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x3 unorm a16<br>
> +define amdgpu_ps void @store.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v3f32.2d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x7 unorm a16<br>
> +define amdgpu_ps void @store.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v4f32.2d:<br>
> +; GCN: image_store v[1:4], v0, s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords, i32 0<br>
> + %y = extractelement <2 x i16> %coords, i32 1<br>
> + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.f32.3d:<br>
> +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x1 unorm a16<br>
> +define amdgpu_ps void @store.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v2f32.3d:<br>
> +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x3 unorm a16<br>
> +define amdgpu_ps void @store.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v3f32.3d:<br>
> +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x7 unorm a16<br>
> +define amdgpu_ps void @store.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +; GCN-LABEL: {{^}}store.v4f32.3d:<br>
> +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm a16<br>
> +define amdgpu_ps void @store.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {<br>
> +main_body:<br>
> + %x = extractelement <2 x i16> %coords_lo, i32 0<br>
> + %y = extractelement <2 x i16> %coords_lo, i32 1<br>
> + %z = extractelement <2 x i16> %coords_hi, i32 0<br>
> + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)<br>
> + ret void<br>
> +}<br>
> +<br>
> +declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #2<br>
> +declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #2<br>
> +declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2<br>
> +<br>
> +attributes #0 = { nounwind }<br>
> +attributes #1 = { nounwind readonly }<br>
><br>
> Modified: llvm/trunk/test/MC/AMDGPU/mimg.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/mimg.s?rev=345710&r1=345709&r2=345710&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/mimg.s?rev=345710&r1=345709&r2=345710&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/AMDGPU/mimg.s (original)<br>
> +++ llvm/trunk/test/MC/AMDGPU/mimg.s Wed Oct 31 03:34:48 2018<br>
> @@ -158,6 +158,84 @@ image_load v[5:7], v[1:4], s[8:15] dmask<br>
> // GFX9: image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80]<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> +// Image Load/Store: a16<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +image_load v5, v[1:2], s[8:15] unorm a16<br>
> +// GFX9: image_load v5, v[1:2], s[8:15] unorm a16 ; encoding: [0x00,0x90,0x00,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_load v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16<br>
> +// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 ; encoding: [0x00,0x93,0x00,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_load v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16<br>
> +// GFX9: image_load v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 ; encoding: [0x00,0x97,0x00,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_load v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16<br>
> +// GFX9: image_load v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v5, v[1:2], s[8:15] unorm a16<br>
> +// GFX9: image_store v5, v[1:2], s[8:15] unorm a16 ; encoding: [0x00,0x90,0x20,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16<br>
> +// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 ; encoding: [0x00,0x93,0x20,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16<br>
> +// GFX9: image_store v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 ; encoding: [0x00,0x97,0x20,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16<br>
> +// GFX9: image_store v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +/===----------------------------------------------------------------------===//<br>
> +// Image Load/Store: a16 & d16<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +image_load v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16<br>
> +// GFX9: image_load v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 ; encoding: [0x00,0x93,0x00,0xf0,0x01,0x05,0x02,0x80]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_load v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16<br>
> +// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 ; encoding: [0x00,0x97,0x00,0xf0,0x01,0x05,0x02,0x80]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_load v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16<br>
> +// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 ; encoding: [0x00,0x9f,0x00,0xf0,0x01,0x05,0x02,0x80]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16<br>
> +// GFX9: image_store v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 ; encoding: [0x00,0x93,0x20,0xf0,0x01,0x05,0x02,0x80]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16<br>
> +// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 ; encoding: [0x00,0x97,0x20,0xf0,0x01,0x05,0x02,0x80]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +image_store v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16<br>
> +// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 ; encoding: [0x00,0x9f,0x20,0xf0,0x01,0x05,0x02,0x80]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> // Image Load/Store: PCK variants<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> @@ -193,6 +271,11 @@ image_load_mip_pck v5, v[1:4], s[8:15] d<br>
> // NOVI: error: invalid operand for instruction<br>
> // NOGFX9: error: invalid operand for instruction<br>
><br>
> +image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 a16<br>
> +// GFX9: image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 a16 ; encoding: [0x00,0x81,0x10,0xf0,0x01,0x05,0x02,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm<br>
> // GCN: image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]<br>
><br>
> @@ -216,6 +299,11 @@ image_store_mip_pck v252, v[2:5], s[12:1<br>
> // NOVI: error: invalid operand for instruction<br>
> // NOGFX9: error: invalid operand for instruction<br>
><br>
> +image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16<br>
> +// GFX9: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00]<br>
> +// NOSICI: error: a16 modifier is not supported on this GPU<br>
> +// NOVI: error: a16 modifier is not supported on this GPU<br>
> +<br>
> //===----------------------------------------------------------------------===//<br>
> // Image Sample<br>
> //===----------------------------------------------------------------------===//<br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> llvm-commits@lists.llvm.org<br>
> <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
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