<div dir="ltr">I've reverted this commit, it was causing buildbot failures like <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/25404/steps/check-llvm%20msan/logs/stdio">this</a>.</div><br><div class="gmail_quote"><div dir="ltr">On Thu, Oct 25, 2018 at 2:12 PM David Greene via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: greened<br>
Date: Thu Oct 25 14:10:39 2018<br>
New Revision: 345315<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=345315&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=345315&view=rev</a><br>
Log:<br>
[AArch64] Create proper memoperand for multi-vector stores<br>
<br>
Include all of the store's source vector operands when creating the<br>
MachineMemOperand. Previously, we were missing the first operand,<br>
making the store size seem smaller than it really is.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D52816" rel="noreferrer" target="_blank">https://reviews.llvm.org/D52816</a><br>
<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/AArch64/multi-vector-store-size.ll<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=345315&r1=345314&r2=345315&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=345315&r1=345314&r2=345315&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Oct 25 14:10:39 2018<br>
@@ -7972,7 +7972,7 @@ bool AArch64TargetLowering::getTgtMemInt<br>
Info.opc = ISD::INTRINSIC_VOID;<br>
// Conservatively set memVT to the entire set of vectors stored.<br>
unsigned NumElts = 0;<br>
- for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {<br>
+ for (unsigned ArgI = 0, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {<br>
Type *ArgTy = I.getArgOperand(ArgI)->getType();<br>
if (!ArgTy->isVectorTy())<br>
break;<br>
<br>
Added: llvm/trunk/test/CodeGen/AArch64/multi-vector-store-size.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/multi-vector-store-size.ll?rev=345315&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/multi-vector-store-size.ll?rev=345315&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/multi-vector-store-size.ll (added)<br>
+++ llvm/trunk/test/CodeGen/AArch64/multi-vector-store-size.ll Thu Oct 25 14:10:39 2018<br>
@@ -0,0 +1,164 @@<br>
+; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=isel < %s | FileCheck %s<br>
+<br>
+declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)<br>
+<br>
+declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)<br>
+<br>
+declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)<br>
+declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)<br>
+declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)<br>
+<br>
+define void @addstx(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {<br>
+ %al = load <4 x float>, <4 x float>* %a<br>
+ %bl = load <4 x float>, <4 x float>* %b<br>
+ %cl = load <4 x float>, <4 x float>* %c<br>
+ %dl = load <4 x float>, <4 x float>* %d<br>
+<br>
+ %ar = fadd <4 x float> %al, %bl<br>
+ %br = fadd <4 x float> %bl, %cl<br>
+ %cr = fadd <4 x float> %cl, %dl<br>
+ %dr = fadd <4 x float> %dl, %al<br>
+<br>
+; The sizes below are conservative. AArch64TargetLowering<br>
+; conservatively assumes the entire vector is stored.<br>
+ tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)<br>
+; CHECK: ST2Twov4s {{.*}} :: (store 32 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)<br>
+; CHECK: ST3Threev4s {{.*}} :: (store 48 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)<br>
+; CHECK: ST4Fourv4s {{.*}} :: (store 64 {{.*}})<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+define void @addst1x(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {<br>
+ %al = load <4 x float>, <4 x float>* %a<br>
+ %bl = load <4 x float>, <4 x float>* %b<br>
+ %cl = load <4 x float>, <4 x float>* %c<br>
+ %dl = load <4 x float>, <4 x float>* %d<br>
+<br>
+ %ar = fadd <4 x float> %al, %bl<br>
+ %br = fadd <4 x float> %bl, %cl<br>
+ %cr = fadd <4 x float> %cl, %dl<br>
+ %dr = fadd <4 x float> %dl, %al<br>
+<br>
+; The sizes below are conservative. AArch64TargetLowering<br>
+; conservatively assumes the entire vector is stored.<br>
+ tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)<br>
+; CHECK: ST1Twov4s {{.*}} :: (store 32 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)<br>
+; CHECK: ST1Threev4s {{.*}} :: (store 48 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)<br>
+; CHECK: ST1Fourv4s {{.*}} :: (store 64 {{.*}})<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+define void @addstxlane(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {<br>
+ %al = load <4 x float>, <4 x float>* %a<br>
+ %bl = load <4 x float>, <4 x float>* %b<br>
+ %cl = load <4 x float>, <4 x float>* %c<br>
+ %dl = load <4 x float>, <4 x float>* %d<br>
+<br>
+ %ar = fadd <4 x float> %al, %bl<br>
+ %br = fadd <4 x float> %bl, %cl<br>
+ %cr = fadd <4 x float> %cl, %dl<br>
+ %dr = fadd <4 x float> %dl, %al<br>
+<br>
+; The sizes below are conservative. AArch64TargetLowering<br>
+; conservatively assumes the entire vector is stored.<br>
+ tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)<br>
+; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)<br>
+; CHECK: ST3i32 {{.*}} :: (store 48 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)<br>
+; CHECK: ST4i32 {{.*}} :: (store 64 {{.*}})<br>
+<br>
+ ret void<br>
+}<br>
+; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=isel < %s | FileCheck %s<br>
+<br>
+declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)<br>
+<br>
+declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)<br>
+declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)<br>
+<br>
+declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)<br>
+declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)<br>
+declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)<br>
+<br>
+define void @addstx(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {<br>
+ %al = load <4 x float>, <4 x float>* %a<br>
+ %bl = load <4 x float>, <4 x float>* %b<br>
+ %cl = load <4 x float>, <4 x float>* %c<br>
+ %dl = load <4 x float>, <4 x float>* %d<br>
+<br>
+ %ar = fadd <4 x float> %al, %bl<br>
+ %br = fadd <4 x float> %bl, %cl<br>
+ %cr = fadd <4 x float> %cl, %dl<br>
+ %dr = fadd <4 x float> %dl, %al<br>
+<br>
+; The sizes below are conservative. AArch64TargetLowering<br>
+; conservatively assumes the entiew vector is stored.<br>
+ tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)<br>
+; CHECK: ST2Twov4s {{.*}} :: (store 32 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)<br>
+; CHECK: ST3Threev4s {{.*}} :: (store 48 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)<br>
+; CHECK: ST4Fourv4s {{.*}} :: (store 64 {{.*}})<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+define void @addst1x(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {<br>
+ %al = load <4 x float>, <4 x float>* %a<br>
+ %bl = load <4 x float>, <4 x float>* %b<br>
+ %cl = load <4 x float>, <4 x float>* %c<br>
+ %dl = load <4 x float>, <4 x float>* %d<br>
+<br>
+ %ar = fadd <4 x float> %al, %bl<br>
+ %br = fadd <4 x float> %bl, %cl<br>
+ %cr = fadd <4 x float> %cl, %dl<br>
+ %dr = fadd <4 x float> %dl, %al<br>
+<br>
+; The sizes below are conservative. AArch64TargetLowering<br>
+; conservatively assumes the entiew vector is stored.<br>
+ tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)<br>
+; CHECK: ST1Twov4s {{.*}} :: (store 32 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)<br>
+; CHECK: ST1Threev4s {{.*}} :: (store 48 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)<br>
+; CHECK: ST1Fourv4s {{.*}} :: (store 64 {{.*}})<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+define void @addstxlane(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {<br>
+ %al = load <4 x float>, <4 x float>* %a<br>
+ %bl = load <4 x float>, <4 x float>* %b<br>
+ %cl = load <4 x float>, <4 x float>* %c<br>
+ %dl = load <4 x float>, <4 x float>* %d<br>
+<br>
+ %ar = fadd <4 x float> %al, %bl<br>
+ %br = fadd <4 x float> %bl, %cl<br>
+ %cr = fadd <4 x float> %cl, %dl<br>
+ %dr = fadd <4 x float> %dl, %al<br>
+<br>
+; The sizes below are conservative. AArch64TargetLowering<br>
+; conservatively assumes the entiew vector is stored.<br>
+ tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)<br>
+; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)<br>
+; CHECK: ST3i32 {{.*}} :: (store 48 {{.*}})<br>
+ tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)<br>
+; CHECK: ST4i32 {{.*}} :: (store 64 {{.*}})<br>
+<br>
+ ret void<br>
+}<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>