<div dir="ltr">Nevermind. Just realized this is a big-endian machine.<div><br></div><div>-Nirav</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Oct 17, 2018 at 10:18 AM, Nirav Davé <span dir="ltr"><<a href="mailto:niravd@google.com" target="_blank">niravd@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Wait, i40 is legal with a 16-bit byte? That seems wrong to me. Shouldn't the a "byte" be the minimal (or part of the minimal) access size? I wonder if you actually want an 8-bit byte but double-byte addressing. <div><br></div><div>Regardless, restricting this optimization to only byte-multiples seems like the way to go then. </div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Oct 17, 2018 at 2:34 AM, Mikael Holmén <span dir="ltr"><<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<span><br>
On 10/16/2018 10:28 PM, Nirav Davé wrote:<br>
> I thought the current state of non-8-bit bytes was not yet viable as <br>
> things were baked in pretty hard.<br>
<br>
</span>Yes there are many "* 8", "/ 8", ">> 3" etc in-tree that are connected <br>
to the byte size, but we've changed most of them in our clone and <br>
generalized things so we use the bytesize that we've added to the <br>
DataLayout instead. It works :)<br>
<br>
Every now and then there pops up a new hardcoded 8, 3 or similar in-tree <br>
that we must deal with but most of the time we notice that pretty quickly.<br>
<span><br>
> Insisting that the LDType and STType <br>
> are some multiple of Byte should be sufficient, but that's probably <br>
> something that exists only for you.<br>
> <br>
> Can you try replacing with the following additional type legality check?<br>
> <br>
> -Nirav<br>
> + if (DAG.getDataLayout().isBigEndi<wbr>an()) {<br>
> + // Avoid dealing with big endian type legalization.<br>
> + if (!TLI.isTypeLegal(STType) || !TLI.isTypeLegal(LDType))<br>
> + return SDValue();<br>
> + Offset =<br>
> + (STMemType.getSizeInBit<wbr>s() - LDMemType.getSizeInBits()) / 8 - <br>
> Offset;<br>
> + }<br>
> +<br>
<br>
</span>Unfortunately it doesn't help in this case.<br>
<br>
We have<br>
<br>
STType: i40<br>
LDType: i32<br>
<br>
and both i32 and i40 are legal on my target. (Yes, we've added i40 to <br>
MVT which has also been interesting, there are a couple of places where <br>
it's assumed that the MVTs are all power-of-2, which i40 clearly isn't).<br>
<br>
Checking that the sizes of LDType and STType are multiple of bytes like<br>
<br>
// Normalize for Endianness.<br>
if (DAG.getDataLayout().isBigEndi<wbr>an()) {<br>
<span> // Avoid dealing with big endian type legalization.<br>
</span> if (!TLI.isTypeLegal(STType) || !TLI.isTypeLegal(LDType) ||<br>
(LDType.getSizeInBits() % bitsPerByte() != 0) ||<br>
(STType.getSizeInBits() % bitsPerByte() != 0))<br>
return SDValue();<br>
<span> Offset =<br>
(STMemType.getSizeInBits() - LDMemType.getSizeInBits()) / <br>
bitsPerByte() - Offset;<br>
}<br>
<br>
</span>seems to work since it then bails out on the i40.<br>
<br>
<br>
I still have a nagging feeling that this could be solved by involving <br>
getStoreSizeInBits() instead of, or in addition to, getSizeInBits() in <br>
some way though. If we calculate Offset as<br>
<br>
Offset =<br>
(STMemType.<wbr>getStoreSizeInBits() - LDMemType.getStoreSizeInBits()<wbr>) <br>
/ bitsPerByte() - Offset;<br>
<br>
then we would get (48 - 32)/16 - 0 so Offset would be 1 and then we'd <br>
abort transformation with<br>
<span><br>
// TODO: Deal with nonzero offset.<br>
</span><span> if (LD->getBasePtr().isUndef() || Offset != 0)<br>
</span> return SDValue();<br>
<br>
so that would work too in this particular case but I don't know if <br>
that's correct or not.<br>
<br>
I also don't know if this is really just a problem for bigendian targets <br>
or not, or if it's indeed just a problem for my target with all its <br>
oddities.<br>
<br>
Thanks,<br>
Mikael<br>
<span><br>
> <br>
> <br>
> <br>
> <br>
> <br>
> <br>
> 16-bit bytes? My understanding is that we've baked in 8-bit bytes pretty <br>
> strongly into the backend. Are you<br>
> <br>
> <br>
> On Mon, Oct 15, 2018 at 2:43 AM, Mikael Holmén <br>
</span><div><div>> <<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson<wbr>.com</a>>> wrote:<br>
> <br>
> Hi,<br>
> <br>
> On 10/12/2018 04:03 PM, Nirav Davé wrote:<br>
> > Hmm. I wonder if this is an issue with bigendian vector representations.<br>
> > <br>
> <br>
> No vectors involved in this case though.<br>
> <br>
> I think it's a size vs stores size issue, possibly that might affect<br>
> bigendian vectors too? I don't know.<br>
> <br>
> > I suspect there are not too many cases where we actually get to the <br>
> > getTruncatedStoreValue in your case. Can you tell me what STType, <br>
> > LDType, STMemType, LDMemType, and final offset are when we get there for <br>
> > your test case?<br>
> <br>
> When we reach getTruncatedStoreValue we have the following DAG:<br>
> <br>
> SelectionDAG has 22 nodes:<br>
> t0: ch = EntryToken<br>
> t2: i24,ch = CopyFromReg t0, Register:i24 %0<br>
> t23: ch = TokenFactor t2:1, t22<br>
> t32: i32 = srl t38, Constant:i16<16><br>
> t17: ch,glue = CopyToReg t23, Register:i32 $a1_32, t32<br>
> t27: i16 = add FrameIndex:i16<0>, Constant:i16<2><br>
> t34: i32,ch = load<(dereferenceable load 1 from %ir._p48 + 2),<br>
> zext from i16> t22, t27, undef:i16<br>
> t30: i32 = shl t38, Constant:i16<16><br>
> t37: i32 = add t34, t30<br>
> t19: ch,glue = CopyToReg t17, Register:i32 $a0_32, t37, t17:1<br>
> t24: i40 = any_extend t2<br>
> t6: i40 = shl nuw t24, Constant:i16<16><br>
> t22: ch = store<(store 3 into %ir._p40, align 1)> t0, t6,<br>
> FrameIndex:i16<0>, undef:i16<br>
> t38: i32,ch = load<(dereferenceable load 2 from %ir._p48, align 1)><br>
> t22, FrameIndex:i16<0>, undef:i16<br>
> t20: ch = PHXISD::RETURN t19, Register:i32 $a1_32, Register:i32<br>
> $a0_32, t19:1<br>
> <br>
> and the following types<br>
> <br>
> STType: i40<br>
> LDType: i32<br>
> STMemType: i40<br>
> LDMemType: i32<br>
> <br>
> The Offset is 0.<br>
> <br>
> Complicating factor: the byte size on my target is 16, not 8, so we've<br>
> replaced the hardcoded 8 in "* 8" and "/ 8" with "bitsPerByte()" which<br>
> in our case is 16 so the code looks like:<br>
> <br>
> bool STCoversLD =<br>
> BasePtrST.equalBaseIndex(Base<wbr>PtrLD, DAG, Offset) && (Offset<br>
> >= 0) &&<br>
> (Offset * bitsPerByte() <= LDMemType.getSizeInBits()) &&<br>
> (Offset * bitsPerByte() + LDMemType.getSizeInBits() <=<br>
> STMemType.getSizeInBits());<br>
> <br>
> if (!STCoversLD)<br>
> return SDValue();<br>
> <br>
> // Normalize for Endianness.<br>
> if (DAG.getDataLayout().isBigEndi<wbr>an())<br>
> Offset =<br>
> (STMemType.getSizeInBits() - LDMemType.getSizeInBits()) /<br>
> bitsPerByte() - Offset;<br>
> <br>
> The Offset was thus calculated as<br>
> <br>
> (40 - 32)/16 - 0<br>
> <br>
> which I suspect is incorrect.<br>
> <br>
> STMemType is i40, so the size in bits is 40. However, the store size<br>
> for<br>
> i40 is 48!<br>
> <br>
> So I think that we need to involve the store size in some way here.<br>
> <br>
> Regards,<br>
> Mikael<br>
> <br>
> > <br>
> > -Nirav<br>
> > <br>
> > <br>
> > <br>
> > <br>
> > <br>
> > <br>
> > <br>
> > On Fri, Oct 12, 2018 at 9:33 AM, Mikael Holmén <br>
> > <<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson<wbr>.com</a>><br>
</div></div><div><div>> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a><br>
> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a>>>> wrote:<br>
> ><br>
> > Hi again,<br>
> ><br>
> > There seems to be another problem too.<br>
> ><br>
> > I don't have an in-tree reproducer for it but I think the problem<br>
> > has to<br>
> > do with cases where the store size of the VT is larger than the<br>
> > "normal"<br>
> > size.<br>
> ><br>
> ><br>
> > Then I think the new code can miscalculate what part of the<br>
> stored<br>
> > value<br>
> > it should use instead of the load. Not sure if this is only a<br>
> problem<br>
> > for bigendian targets or not.<br>
> ><br>
> > The end result is code that fails at runtime so it's quite nasty.<br>
> ><br>
> ><br>
> ><br>
> ><br>
> ><br>
> > Regards,<br>
> > Mikael<br>
> ><br>
> > On 10/12/2018 08:08 AM, Mikael Holmén wrote:<br>
> > > Yep, thanks!<br>
> > ><br>
> > > Regards,<br>
> > > Mikael<br>
> > ><br>
> > > On 10/11/2018 08:44 PM, Nirav Davé wrote:<br>
> > >> Should be fixed in rL344272.<br>
> > >><br>
> > >> Thanks for the catch.<br>
> > >><br>
> > >> -Nirav<br>
> > >><br>
> > >> On Thu, Oct 11, 2018 at 7:41 AM, Mikael Holmén<br>
> > >> <<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a><br>
> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a>><br>
> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson<wbr>.com</a>>><br>
> > <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a><br>
> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a>><br>
> > <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a><br>
> <mailto:<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsso<wbr>n.com</a>>>>> wrote:<br>
> > >><br>
> > >> Hi,<br>
> > >><br>
> > >> Reproducer for powerpc:<br>
> > >><br>
> > >> llc bug.ll -o - -O1<br>
> > >><br>
> > >> Without the patch we get<br>
> > >><br>
> > >> addis 4, 2, .LC0@toc@ha<br>
> > >> sth 3, -2(1)<br>
> > >> ld 4, .LC0@toc@l(4)<br>
> > >> lbz 3, -2(1)<br>
> > >> stb 3, 0(4)<br>
> > >> blr<br>
> > >><br>
> > >> and with<br>
> > >><br>
> > >> addis 4, 2, .LC0@toc@ha<br>
> > >> sth 3, -2(1)<br>
> > >> ld 4, .LC0@toc@l(4)<br>
> > >> stb 3, 0(4)<br>
> > >> blr<br>
> > >><br>
> > >> Admittedly I'm no ppc expert but I think the final<br>
> stb will<br>
> > write<br>
> > >> bits<br>
> > >> [0-7] of 3 to 0(4).<br>
> > >><br>
> > >> Before your patch those 8 bits were setup from the<br>
> > >><br>
> > >> lbz 3, -2(1)<br>
> > >><br>
> > >> but with the patch, I think the bits we're after are<br>
> placed<br>
> > at bit<br>
> > >> [8-15] in 3 so we'll get the wrong byte.<br>
> > >><br>
> > >> /Mikael<br>
> > >><br>
> > >> On 10/11/2018 12:54 PM, Mikael Holmén wrote:<br>
> > >> > Hi Nirav,<br>
> > >> ><br>
> > >> > I suspect that this patch doesn't handle big<br>
> endian targets<br>
> > >> correctly.<br>
> > >> ><br>
> > >> > I'll try to get back with a reproducer for some<br>
> in-tree<br>
> > target,<br>
> > >> but for<br>
> > >> > my out-of-tree bigendian target it looks like it<br>
> changes<br>
> > somethng<br>
> > >> like<br>
> > >> ><br>
> > >> > store i16 %v, i16* %p16<br>
> > >> > %p8 = bitcast i16* %p16 to i8*<br>
> > >> > %ld = load i16, i16* %p8<br>
> > >> ><br>
> > >> > to<br>
> > >> ><br>
> > >> > store i16 %v, i16* %p16<br>
> > >> > %ld = truncate i16 %v to i8<br>
> > >> ><br>
> > >> > but I think it should rather be<br>
> > >> ><br>
> > >> > store i16 %v, i16* %p16<br>
> > >> > %tmp = lshr i16 %v, 8<br>
> > >> > %ld = truncate i16 %tmp to i8<br>
> > >> ><br>
> > >> > I.e. if the target is bigendian, the load will<br>
> read the<br>
> > high 8<br>
> > >> bits from<br>
> > >> > %v rather than the low. And the truncate that this<br>
> patch<br>
> > >> generates gives<br>
> > >> > us the low bits.<br>
> > >> ><br>
> > >> > Regards,<br>
> > >> > Mikael<br>
> > >> ><br>
> > >> > On 10/10/2018 04:15 PM, Nirav Dave via<br>
> llvm-commits wrote:<br>
> > >> >> Author: niravd<br>
> > >> >> Date: Wed Oct 10 07:15:52 2018<br>
> > >> >> New Revision: 344142<br>
> > >> >><br>
> > >> >> URL:<br>
> > <a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=344142&view=rev</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a>><br>
> > <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a>>><br>
> > >> <br>
> <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a>><br>
> > <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a>>>><br>
> > >> >> Log:<br>
> > >> >> [DAGCombine] Improve Load-Store Forwarding<br>
> > >> >><br>
> > >> >> Summary:<br>
> > >> >> Extend analysis forwarding loads from preceeding<br>
> stores to<br>
> > >> work with<br>
> > >> >> extended loads and truncated stores to the same<br>
> address<br>
> > so long<br>
> > >> as the<br>
> > >> >> load is fully subsumed by the store.<br>
> > >> >><br>
> > >> >> Hexagon's swp-epilog-phis.ll and<br>
> swp-memrefs-epilog1.ll<br>
> > test are<br>
> > >> >> deleted as they've no longer seem to be relevant.<br>
> > >> >><br>
> > >> >> Reviewers: RKSimon, rnk, kparzysz, javed.absar<br>
> > >> >><br>
> > >> >> Subscribers: sdardis, nemanjai, hiraditya, atanasyan,<br>
> > >> llvm-commits<br>
> > >> >><br>
> > >> >> Differential Revision:<br>
> <a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D492<wbr>00</a> <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D492<wbr>00</a>><br>
> > <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D49<wbr>200</a><br>
> <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D49<wbr>200</a>>><br>
> > >> <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D492<wbr>00</a><br>
> <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D49<wbr>200</a>><br>
> > <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D49<wbr>200</a><br>
> <<a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/D49<wbr>200</a>>>><br>
> > >> >><br>
> > >> >> Removed:<br>
> > >> >> <br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-epilog-phis.ll<br>
> > >> >> <br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-memrefs-epilog1.ll<br>
> > >> >> Modified:<br>
> > >> >> <br>
> llvm/trunk/lib/CodeGen/Select<wbr>ionDAG/DAGCombiner.cpp<br>
> > >> >> <br>
> llvm/trunk/test/CodeGen/AArch<wbr>64/arm64-ld-from-st.ll<br>
> > >> >><br>
> > llvm/trunk/test/CodeGen/AArch<wbr>64/regress-tblgen-chains.ll<br>
> > >> >> <br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/clr_set_toggle.ll<br>
> > >> >> llvm/trunk/test/CodeGen/Mips/c<wbr>conv/vector.ll<br>
> > >> >><br>
> > >><br>
> llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/jumptable<wbr>s.ll<br>
> > >> >> llvm/trunk/test/CodeGen/Mips/o<wbr>32_cc_byval.ll<br>
> > >> >> llvm/trunk/test/CodeGen/Mips/o<wbr>32_cc_vararg.ll<br>
> > >> >> <br>
> llvm/trunk/test/CodeGen/Power<wbr>PC/addi-offset-fold.ll<br>
> > >> >><br>
> > llvm/trunk/test/CodeGen/Syste<wbr>mZ/store_nonbytesized_vecs.ll<br>
> > >> >> <br>
> llvm/trunk/test/CodeGen/X86/i<wbr>386-shrink-wrapping.ll<br>
> > >> >> llvm/trunk/test/CodeGen/X86/pr<wbr>32108.ll<br>
> > >> >> llvm/trunk/test/CodeGen/X86/pr<wbr>38533.ll<br>
> > >> >> llvm/trunk/test/CodeGen/X86/wi<wbr>n64_vararg.ll<br>
> > >> >><br>
> > >> >> Modified:<br>
> > llvm/trunk/lib/CodeGen/Select<wbr>ionDAG/DAGCombiner.cpp<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/CodeGen<wbr>/SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/CodeGen<wbr>/SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/CodeGen<wbr>/SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/CodeGen<wbr>/SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/lib/CodeGen/Select<wbr>ionDAG/DAGCombiner.cpp<br>
> > >> (original)<br>
> > >> >> +++<br>
> llvm/trunk/lib/CodeGen/Select<wbr>ionDAG/DAGCombiner.cpp Wed<br>
> > >> Oct 10<br>
> > >> >> 07:15:52 2018<br>
> > >> >> @@ -250,6 +250,11 @@ namespace {<br>
> > >> >> SDValue SplitIndexingFromLoad(LoadSDNo<wbr>de *LD);<br>
> > >> >> bool SliceUpLoad(SDNode *N);<br>
> > >> >> + // Scalars have size 0 to distinguish from<br>
> singleton<br>
> > >> vectors.<br>
> > >> >> + SDValue<br>
> <wbr>ForwardStoreValueToDirectLoad(<wbr>LoadSDNode *LD);<br>
> > >> >> + bool getTruncatedStoreValue(StoreSD<wbr>Node *ST,<br>
> > SDValue &Val);<br>
> > >> >> + bool extendLoadedValueToExtension(L<wbr>oadSDNode<br>
> *LD,<br>
> > SDValue<br>
> > >> &Val);<br>
> > >> >> +<br>
> > >> >> /// Replace an ISD::EXTRACT_VECTOR_ELT of a<br>
> load<br>
> > with a<br>
> > >> narrowed<br>
> > >> >> /// load.<br>
> > >> >> ///<br>
> > >> >> @@ -12762,6 +12767,133 @@ SDValue<br>
> > >> DAGCombiner::SplitIndexingFrom<wbr>Lo<br>
> > >> >> return DAG.getNode(Opc, SDLoc(LD),<br>
> > BP.getSimpleValueType(),<br>
> > >> BP, Inc);<br>
> > >> >> }<br>
> > >> >> +static inline int numVectorEltsOrZero(EVT T) {<br>
> > >> >> + return T.isVector() ? T.getVectorNumElements()<br>
> : 0;<br>
> > >> >> +}<br>
> > >> >> +<br>
> > >> >> +bool<br>
> DAGCombiner::getTruncatedStor<wbr>eValue(StoreSDNode *ST,<br>
> > >> SDValue<br>
> > >> >> &Val) {<br>
> > >> >> + Val = ST->getValue();<br>
> > >> >> + EVT STType = Val.getValueType();<br>
> > >> >> + EVT STMemType = ST->getMemoryVT();<br>
> > >> >> + if (STType == STMemType)<br>
> > >> >> + return true;<br>
> > >> >> + if (isTypeLegal(STMemType))<br>
> > >> >> + return false; // fail.<br>
> > >> >> + if (STType.isFloatingPoint() &&<br>
> > STMemType.isFloatingPoint() &&<br>
> > >> >> + TLI.isOperationLegal(ISD::FTRU<wbr>NC,<br>
> STMemType)) {<br>
> > >> >> + Val = DAG.getNode(ISD::FTRUNC, SDLoc(ST),<br>
> > STMemType, Val);<br>
> > >> >> + return true;<br>
> > >> >> + }<br>
> > >> >> + if (numVectorEltsOrZero(STType) ==<br>
> > >> numVectorEltsOrZero(STMemType) &&<br>
> > >> >> + STType.isInteger() && STMemType.isInteger()) {<br>
> > >> >> + Val = DAG.getNode(ISD::TRUNCATE, SDLoc(ST),<br>
> > STMemType, Val);<br>
> > >> >> + return true;<br>
> > >> >> + }<br>
> > >> >> + if (STType.getSizeInBits() ==<br>
> > STMemType.getSizeInBits()) {<br>
> > >> >> + Val = DAG.getBitcast(STMemType, Val);<br>
> > >> >> + return true;<br>
> > >> >> + }<br>
> > >> >> + return false; // fail.<br>
> > >> >> +}<br>
> > >> >> +<br>
> > >> >> +bool<br>
> > DAGCombiner::extendLoadedValu<wbr>eToExtension(LoadSDNode *LD,<br>
> > >> >> SDValue &Val) {<br>
> > >> >> + EVT LDMemType = LD->getMemoryVT();<br>
> > >> >> + EVT LDType = LD->getValueType(0);<br>
> > >> >> + assert(Val.getValueType() == LDMemType &&<br>
> > >> >> + "Attempting to extend value of non-matching<br>
> > type");<br>
> > >> >> + if (LDType == LDMemType)<br>
> > >> >> + return true;<br>
> > >> >> + if (LDMemType.isInteger() && LDType.isInteger()) {<br>
> > >> >> + switch (LD->getExtensionType()) {<br>
> > >> >> + case ISD::NON_EXTLOAD:<br>
> > >> >> + Val = DAG.getBitcast(LDType, Val);<br>
> > >> >> + return true;<br>
> > >> >> + case ISD::EXTLOAD:<br>
> > >> >> + Val = DAG.getNode(ISD::ANY_EXTEND, SDLoc(LD),<br>
> > LDType,<br>
> > >> Val);<br>
> > >> >> + return true;<br>
> > >> >> + case ISD::SEXTLOAD:<br>
> > >> >> + Val = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(LD),<br>
> > LDType,<br>
> > >> Val);<br>
> > >> >> + return true;<br>
> > >> >> + case ISD::ZEXTLOAD:<br>
> > >> >> + Val = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(LD),<br>
> > LDType,<br>
> > >> Val);<br>
> > >> >> + return true;<br>
> > >> >> + }<br>
> > >> >> + }<br>
> > >> >> + return false;<br>
> > >> >> +}<br>
> > >> >> +<br>
> > >> >> +SDValue<br>
> > DAGCombiner::ForwardStoreValu<wbr>eToDirectLoad(LoadSDNode<br>
> > >> *LD) {<br>
> > >> >> + if (OptLevel == CodeGenOpt::None ||<br>
> LD->isVolatile())<br>
> > >> >> + return SDValue();<br>
> > >> >> + SDValue Chain = LD->getOperand(0);<br>
> > >> >> + StoreSDNode *ST =<br>
> dyn_cast<StoreSDNode>(Chain.g<wbr>etNode());<br>
> > >> >> + if (!ST || ST->isVolatile())<br>
> > >> >> + return SDValue();<br>
> > >> >> +<br>
> > >> >> + EVT LDType = LD->getValueType(0);<br>
> > >> >> + EVT LDMemType = LD->getMemoryVT();<br>
> > >> >> + EVT STMemType = ST->getMemoryVT();<br>
> > >> >> + EVT STType = ST->getValue().getValueType();<br>
> > >> >> +<br>
> > >> >> + BaseIndexOffset BasePtrLD =<br>
> > BaseIndexOffset::match(LD, DAG);<br>
> > >> >> + BaseIndexOffset BasePtrST =<br>
> > BaseIndexOffset::match(ST, DAG);<br>
> > >> >> + int64_t Offset;<br>
> > >> >> +<br>
> > >> >> + bool STCoversLD =<br>
> > >> >> + BasePtrST.equalBaseIndex(BaseP<wbr>trLD, DAG,<br>
> Offset) &&<br>
> > >> (Offset >=<br>
> > >> >> 0) &&<br>
> > >> >> + (Offset * 8 <= LDMemType.getSizeInBits()) &&<br>
> > >> >> + (Offset * 8 + LDMemType.getSizeInBits() <=<br>
> > >> >> STMemType.getSizeInBits());<br>
> > >> >> +<br>
> > >> >> + if (!STCoversLD)<br>
> > >> >> + return SDValue();<br>
> > >> >> +<br>
> > >> >> + // Memory as copy space (potentially masked).<br>
> > >> >> + if (Offset == 0 && LDType == STType &&<br>
> STMemType ==<br>
> > >> LDMemType) {<br>
> > >> >> + // Simple case: Direct non-truncating forwarding<br>
> > >> >> + if (LDType.getSizeInBits() ==<br>
> > LDMemType.getSizeInBits())<br>
> > >> >> + return CombineTo(LD, ST->getValue(), Chain);<br>
> > >> >> + // Can we model the truncate and extension<br>
> with an<br>
> > and mask?<br>
> > >> >> + if (STType.isInteger() &&<br>
> LDMemType.isInteger() &&<br>
> > >> >> !STType.isVector() &&<br>
> > >> >> + !LDMemType.isVector() &&<br>
> LD->getExtensionType() !=<br>
> > >> >> ISD::SEXTLOAD) {<br>
> > >> >> + // Mask to size of LDMemType<br>
> > >> >> + auto Mask =<br>
> > >> >> +<br>
> > >> DAG.getConstant(APInt::getLowB<wbr>itsSet(STType.getSizeInBits(),<br>
> > >> >> +<br>
> > >> >> STMemType.getSizeInBits()),<br>
> > >> >> + SDLoc(ST), STType);<br>
> > >> >> + auto Val = DAG.getNode(ISD::AND,<br>
> SDLoc(LD), LDType,<br>
> > >> >> ST->getValue(), Mask);<br>
> > >> >> + return CombineTo(LD, Val, Chain);<br>
> > >> >> + }<br>
> > >> >> + }<br>
> > >> >> +<br>
> > >> >> + // TODO: Deal with nonzero offset.<br>
> > >> >> + if (LD->getBasePtr().isUndef() || Offset != 0)<br>
> > >> >> + return SDValue();<br>
> > >> >> + // Model necessary truncations / extenstions.<br>
> > >> >> + SDValue Val;<br>
> > >> >> + // Truncate Value To Stored Memory Size.<br>
> > >> >> + do {<br>
> > >> >> + if (!getTruncatedStoreValue(ST, Val))<br>
> > >> >> + continue;<br>
> > >> >> + if (!isTypeLegal(LDMemType))<br>
> > >> >> + continue;<br>
> > >> >> + if (STMemType != LDMemType) {<br>
> > >> >> + if (numVectorEltsOrZero(STMemType<wbr>) ==<br>
> > >> >> numVectorEltsOrZero(LDMemType) &&<br>
> > >> >> + STMemType.isInteger() &&<br>
> LDMemType.isInteger())<br>
> > >> >> + Val = DAG.getNode(ISD::TRUNCATE, SDLoc(LD),<br>
> > LDMemType,<br>
> > >> Val);<br>
> > >> >> + else<br>
> > >> >> + continue;<br>
> > >> >> + }<br>
> > >> >> + if (!extendLoadedValueToExtension<wbr>(LD, Val))<br>
> > >> >> + continue;<br>
> > >> >> + return CombineTo(LD, Val, Chain);<br>
> > >> >> + } while (false);<br>
> > >> >> +<br>
> > >> >> + // On failure, cleanup dead nodes we may have<br>
> created.<br>
> > >> >> + if (Val->use_empty())<br>
> > >> >> + deleteAndRecombine(Val.getNode<wbr>());<br>
> > >> >> + return SDValue();<br>
> > >> >> +}<br>
> > >> >> +<br>
> > >> >> SDValue DAGCombiner::visitLOAD(SDNode *N) {<br>
> > >> >> LoadSDNode *LD = cast<LoadSDNode>(N);<br>
> > >> >> SDValue Chain = LD->getChain();<br>
> > >> >> @@ -12828,17 +12960,8 @@ SDValue<br>
> > DAGCombiner::visitLOAD(SDNode *N<br>
> > >> >> // If this load is directly stored, replace<br>
> the load<br>
> > value<br>
> > >> with<br>
> > >> >> the stored<br>
> > >> >> // value.<br>
> > >> >> - // TODO: Handle store large -> read small portion.<br>
> > >> >> - // TODO: Handle TRUNCSTORE/LOADEXT<br>
> > >> >> - if (OptLevel != CodeGenOpt::None &&<br>
> > >> >> - ISD::isNormalLoad(N) && !LD->isVolatile()) {<br>
> > >> >> - if (ISD::isNON_TRUNCStore(Chain.g<wbr>etNode())) {<br>
> > >> >> - StoreSDNode *PrevST =<br>
> cast<StoreSDNode>(Chain);<br>
> > >> >> - if (PrevST->getBasePtr() == Ptr &&<br>
> > >> >> - PrevST->getValue().getValueTyp<wbr>e() ==<br>
> > >> N->getValueType(0))<br>
> > >> >> - return CombineTo(N,<br>
> PrevST->getOperand(1), Chain);<br>
> > >> >> - }<br>
> > >> >> - }<br>
> > >> >> + if (auto V = ForwardStoreValueToDirectLoad(<wbr>LD))<br>
> > >> >> + return V;<br>
> > >> >> // Try to infer better alignment information than<br>
> > the load<br>
> > >> already<br>
> > >> >> has.<br>
> > >> >> if (OptLevel != CodeGenOpt::None &&<br>
> LD->isUnindexed()) {<br>
> > >> >><br>
> > >> >> Modified:<br>
> > llvm/trunk/test/CodeGen/AArch<wbr>64/arm64-ld-from-st.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/arm64-ld-from-st.ll?<wbr>rev=344142&r1=344141&r2=344142<wbr>&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/test/CodeGen/AArch<wbr>64/arm64-ld-from-st.ll<br>
> > >> (original)<br>
> > >> >> +++<br>
> llvm/trunk/test/CodeGen/AArch<wbr>64/arm64-ld-from-st.ll Wed<br>
> > >> Oct 10<br>
> > >> >> 07:15:52 2018<br>
> > >> >> @@ -13,7 +13,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str64Ldr32_0<br>
> > >> >> -; CHECK: and x0, x1, #0xffffffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i32 @Str64Ldr32_0(i64* nocapture %P, i64 %v,<br>
> > i64 %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i64* %P to i32*<br>
> > >> >> @@ -37,7 +37,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str64Ldr16_0<br>
> > >> >> -; CHECK: and x0, x1, #0xffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i16 @Str64Ldr16_0(i64* nocapture %P, i64 %v,<br>
> > i64 %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i64* %P to i16*<br>
> > >> >> @@ -85,7 +85,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str64Ldr8_0<br>
> > >> >> -; CHECK: and x0, x1, #0xff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i8 @Str64Ldr8_0(i64* nocapture %P, i64<br>
> %v, i64<br>
> > %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i64* %P to i8*<br>
> > >> >> @@ -193,7 +193,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str32Ldr16_0<br>
> > >> >> -; CHECK: and w0, w1, #0xffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i16 @Str32Ldr16_0(i32* nocapture %P, i32 %v,<br>
> > i64 %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i32* %P to i16*<br>
> > >> >> @@ -217,7 +217,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str32Ldr8_0<br>
> > >> >> -; CHECK: and w0, w1, #0xff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i8 @Str32Ldr8_0(i32* nocapture %P, i32<br>
> %v, i64<br>
> > %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i32* %P to i8*<br>
> > >> >> @@ -265,7 +265,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str16Ldr16<br>
> > >> >> -; CHECK: and w0, w1, #0xffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i16 @Str16Ldr16(i16* nocapture %P, i16<br>
> %v, i64<br>
> > %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i16* %P to i16*<br>
> > >> >> @@ -277,7 +277,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Str16Ldr8_0<br>
> > >> >> -; CHECK: and w0, w1, #0xff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i8 @Str16Ldr8_0(i16* nocapture %P, i16<br>
> %v, i64<br>
> > %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i16* %P to i8*<br>
> > >> >> @@ -314,7 +314,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str64Ldr32_0<br>
> > >> >> -; CHECK: and x0, x1, #0xffffffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i32 @Unscaled_Str64Ldr32_0(i64*<br>
> nocapture %P,<br>
> > i64 %v,<br>
> > >> i64 %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i64* %P to i32*<br>
> > >> >> @@ -338,7 +338,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str64Ldr16_0<br>
> > >> >> -; CHECK: and x0, x1, #0xffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i16 @Unscaled_Str64Ldr16_0(i64*<br>
> nocapture %P,<br>
> > i64 %v,<br>
> > >> i64 %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i64* %P to i16*<br>
> > >> >> @@ -386,7 +386,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str64Ldr8_0<br>
> > >> >> -; CHECK: and x0, x1, #0xff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i8 @Unscaled_Str64Ldr8_0(i64* nocapture<br>
> %P, i64<br>
> > %v, i64<br>
> > >> %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i64* %P to i8*<br>
> > >> >> @@ -494,7 +494,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str32Ldr16_0<br>
> > >> >> -; CHECK: and w0, w1, #0xffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i16 @Unscaled_Str32Ldr16_0(i32*<br>
> nocapture %P,<br>
> > i32 %v,<br>
> > >> i64 %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i32* %P to i16*<br>
> > >> >> @@ -518,7 +518,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str32Ldr8_0<br>
> > >> >> -; CHECK: and w0, w1, #0xff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i8 @Unscaled_Str32Ldr8_0(i32* nocapture<br>
> %P, i32<br>
> > %v, i64<br>
> > >> %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i32* %P to i8*<br>
> > >> >> @@ -566,7 +566,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str16Ldr16<br>
> > >> >> -; CHECK: and w0, w1, #0xffff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i16 @Unscaled_Str16Ldr16(i16* nocapture<br>
> %P, i16<br>
> > %v, i64<br>
> > >> %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i16* %P to i16*<br>
> > >> >> @@ -578,7 +578,7 @@ entry:<br>
> > >> >> }<br>
> > >> >> ; CHECK-LABEL: Unscaled_Str16Ldr8_0<br>
> > >> >> -; CHECK: and w0, w1, #0xff<br>
> > >> >> +; CHECK: mov w0, w1<br>
> > >> >> define i8 @Unscaled_Str16Ldr8_0(i16* nocapture<br>
> %P, i16<br>
> > %v, i64<br>
> > >> %n) {<br>
> > >> >> entry:<br>
> > >> >> %0 = bitcast i16* %P to i8*<br>
> > >> >><br>
> > >> >> Modified:<br>
> > >> llvm/trunk/test/CodeGen/AArch6<wbr>4/regress-tblgen-chains.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/AArch64/regress-tblgen-<wbr>chains.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/test/CodeGen/AArch<wbr>64/regress-tblgen-chains.ll<br>
> > >> (original)<br>
> > >> >> +++<br>
> > llvm/trunk/test/CodeGen/AArch<wbr>64/regress-tblgen-chains.ll Wed<br>
> > >> Oct<br>
> > >> >> 10 07:15:52 2018<br>
> > >> >> @@ -26,9 +26,9 @@ define i64 @test_chains() {<br>
> > >> >> store i8 %inc.4, i8* %locvar<br>
> > >> >> ; CHECK: ldurb {{w[0-9]+}}, [x29,<br>
> [[LOCADDR:#-?[0-9]+]]]<br>
> > >> >> -; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1<br>
> > >> >> +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #1<br>
> > >> >> ; CHECK: sturb w[[STRVAL:[0-9]+]], [x29,<br>
> [[LOCADDR]]]<br>
> > >> >> -; CHECK: and w0, w[[STRVAL]], #0xff<br>
> > >> >> +; CHECK: and x0, x[[STRVAL]], #0xff<br>
> > >> >> %ret.1 = load i8, i8* %locvar<br>
> > >> >> %ret.2 = zext i8 %ret.1 to i64<br>
> > >> >><br>
> > >> >> Modified:<br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/clr_set_toggle.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/clr_set_toggle.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/Hexago<wbr>n/clr_set_toggle.ll<br>
> > (original)<br>
> > >> >> +++ llvm/trunk/test/CodeGen/Hexago<wbr>n/clr_set_toggle.ll<br>
> > Wed Oct 10<br>
> > >> >> 07:15:52 2018<br>
> > >> >> @@ -70,7 +70,7 @@ entry:<br>
> > >> >> define zeroext i16 @my_setbit(i16 zeroext %crc)<br>
> nounwind {<br>
> > >> >> entry:<br>
> > >> >> ; CHECK-LABEL: my_setbit<br>
> > >> >> -; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}) = setbit(#15)<br>
> > >> >> +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)<br>
> > >> >> %crc.addr = alloca i16, align 2<br>
> > >> >> store i16 %crc, i16* %crc.addr, align 2<br>
> > >> >> %0 = load i16, i16* %crc.addr, align 2<br>
> > >> >><br>
> > >> >> Removed:<br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-epilog-phis.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-epilog-phis.ll?<wbr>rev=344141&view=auto</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-epilog-phis.ll<br>
> > (original)<br>
> > >> >> +++<br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-epilog-phis.ll<br>
> > (removed)<br>
> > >> >> @@ -1,55 +0,0 @@<br>
> > >> >> -; RUN: llc -march=hexagon -enable-pipeliner<br>
> > >> -pipeliner-max-stages=2 \<br>
> > >> >> -; RUN: -pipeliner-ignore-recmii<br>
> > >> -disable-hexagon-nv-schedule \<br>
> > >> >> -; RUN: -hexagon-initial-cfg-cleanup=0 -stats -o<br>
> > /dev/null \<br>
> > >> >> -; RUN: -enable-aa-sched-mi < %s 2>&1 |<br>
> FileCheck %s<br>
> > >> >> --check-prefix=STATS<br>
> > >> >> -; REQUIRES: asserts<br>
> > >> >> -;<br>
> > >> >> -; Test that we generate the correct phis in the<br>
> last epilog<br>
> > >> block when<br>
> > >> >> -; allowing multiple stages.<br>
> > >> >> -;<br>
> > >> >> -; STATS: 1 pipeliner - Number of loops<br>
> software<br>
> > pipelined<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind<br>
> > >> >> -define void @f0() #0 {<br>
> > >> >> -b0:<br>
> > >> >> - br i1 undef, label %b6, label %b1<br>
> > >> >> -<br>
> > >> >> -b1: ; preds = %b0<br>
> > >> >> - br i1 undef, label %b6, label %b2<br>
> > >> >> -<br>
> > >> >> -b2: ; preds = %b1<br>
> > >> >> - br label %b4<br>
> > >> >> -<br>
> > >> >> -b3: ; preds = %b4, %b3<br>
> > >> >> - %v0 = add nsw i32 0, 57344<br>
> > >> >> - %v1 = trunc i32 %v0 to i16<br>
> > >> >> - store i16 %v1, i16* null, align 2, !tbaa !0<br>
> > >> >> - %v2 = getelementptr inbounds i8, i8* null, i32<br>
> undef<br>
> > >> >> - %v3 = load i8, i8* %v2, align 1, !tbaa !4<br>
> > >> >> - %v4 = zext i8 %v3 to i32<br>
> > >> >> - %v5 = shl nuw nsw i32 %v4, 6<br>
> > >> >> - %v6 = add nsw i32 %v5, 57344<br>
> > >> >> - %v7 = trunc i32 %v6 to i16<br>
> > >> >> - store i16 %v7, i16* undef, align 2, !tbaa !0<br>
> > >> >> - br i1 undef, label %b5, label %b3<br>
> > >> >> -<br>
> > >> >> -b4: ; preds = %b5, %b2<br>
> > >> >> - %v8 = phi i32 [ 0, %b2 ], [ %v9, %b5 ]<br>
> > >> >> - br label %b3<br>
> > >> >> -<br>
> > >> >> -b5: ; preds = %b3<br>
> > >> >> - %v9 = add i32 %v8, 1<br>
> > >> >> - %v10 = icmp eq i32 %v9, undef<br>
> > >> >> - br i1 %v10, label %b6, label %b4<br>
> > >> >> -<br>
> > >> >> -b6: ; preds = %b5, %b1,<br>
> > >> >> %b0<br>
> > >> >> - ret void<br>
> > >> >> -}<br>
> > >> >> -<br>
> > >> >> -attributes #0 = { nounwind<br>
> "target-cpu"="hexagonv55" }<br>
> > >> >> -<br>
> > >> >> -!0 = !{!1, !1, i64 0}<br>
> > >> >> -!1 = !{!"short", !2}<br>
> > >> >> -!2 = !{!"omnipotent char", !3}<br>
> > >> >> -!3 = !{!"Simple C/C++ TBAA"}<br>
> > >> >> -!4 = !{!2, !2, i64 0}<br>
> > >> >><br>
> > >> >> Removed:<br>
> > llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-memrefs-epilog1.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Hexagon/swp-memrefs-epilog1.<wbr>ll?rev=344141&view=auto</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-memrefs-epilog1.ll<br>
> > >> (original)<br>
> > >> >> +++<br>
> llvm/trunk/test/CodeGen/Hexag<wbr>on/swp-memrefs-epilog1.ll<br>
> > >> (removed)<br>
> > >> >> @@ -1,90 +0,0 @@<br>
> > >> >> -; RUN: llc -march=hexagon -enable-pipeliner < %s |<br>
> > FileCheck %s<br>
> > >> >> -<br>
> > >> >> -; Test that a store and load, that alias, are<br>
> not put<br>
> > in the<br>
> > >> same<br>
> > >> >> packet. The<br>
> > >> >> -; pipeliner altered the size of the memrefs for<br>
> these<br>
> > >> instructions,<br>
> > >> >> which<br>
> > >> >> -; resulted in no order dependence between the<br>
> > instructions in<br>
> > >> the<br>
> > >> >> DAG. No order<br>
> > >> >> -; dependence was added since the size was set to<br>
> > UINT_MAX, but<br>
> > >> there<br>
> > >> >> is a<br>
> > >> >> -; computation using the size that overflowed.<br>
> > >> >> -<br>
> > >> >> -; CHECK: endloop0<br>
> > >> >> -; CHECK: memh([[REG:r([0-9]+)]]+#0) =<br>
> > >> >> -; CHECK: = memh([[REG]]++#2)<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind<br>
> > >> >> -define signext i16 @f0(i16* nocapture readonly<br>
> %a0, i16*<br>
> > >> nocapture<br>
> > >> >> readonly %a1) local_unnamed_addr #0 {<br>
> > >> >> -b0:<br>
> > >> >> - %v0 = alloca [40 x i16], align 8<br>
> > >> >> - %v1 = bitcast [40 x i16]* %v0 to i8*<br>
> > >> >> - call void @llvm.lifetime.start.p0i8(i64 80,<br>
> i8* nonnull<br>
> > >> %v1) #2<br>
> > >> >> - %v2 = getelementptr inbounds [40 x i16], [40 x<br>
> i16]*<br>
> > %v0, i32<br>
> > >> 0, i32 0<br>
> > >> >> - br label %b1<br>
> > >> >> -<br>
> > >> >> -b1: ; preds = %b1, %b0<br>
> > >> >> - %v3 = phi i16* [ %a1, %b0 ], [ %v24, %b1 ]<br>
> > >> >> - %v4 = phi i16* [ %v2, %b0 ], [ %v25, %b1 ]<br>
> > >> >> - %v5 = phi i32 [ 0, %b0 ], [ %v14, %b1 ]<br>
> > >> >> - %v6 = phi i32 [ 1, %b0 ], [ %v22, %b1 ]<br>
> > >> >> - %v7 = phi i32 [ 0, %b0 ], [ %v23, %b1 ]<br>
> > >> >> - %v8 = load i16, i16* %v3, align 2<br>
> > >> >> - %v9 = sext i16 %v8 to i32<br>
> > >> >> - %v10 = tail call i32 @llvm.hexagon.A2.aslh(i32<br>
> %v9)<br>
> > >> >> - %v11 = tail call i32<br>
> @llvm.hexagon.S2.asr.r.r.sat(<wbr>i32<br>
> > %v10,<br>
> > >> i32 1)<br>
> > >> >> - %v12 = tail call i32 @llvm.hexagon.A2.asrh(i32<br>
> %v11)<br>
> > >> >> - %v13 = trunc i32 %v12 to i16<br>
> > >> >> - store i16 %v13, i16* %v4, align 2<br>
> > >> >> - %v14 = add nuw nsw i32 %v5, 1<br>
> > >> >> - %v15 = icmp eq i32 %v14, 40<br>
> > >> >> - %v16 = getelementptr inbounds i16, i16* %a0,<br>
> i32 %v7<br>
> > >> >> - %v17 = load i16, i16* %v16, align 2<br>
> > >> >> - %v18 = sext i16 %v17 to i32<br>
> > >> >> - %v19 = getelementptr inbounds [40 x i16], [40<br>
> x i16]*<br>
> > %v0,<br>
> > >> i32 0,<br>
> > >> >> i32 %v7<br>
> > >> >> - %v20 = load i16, i16* %v19, align 2<br>
> > >> >> - %v21 = sext i16 %v20 to i32<br>
> > >> >> - %v22 = tail call i32<br>
> > @llvm.hexagon.M2.mpy.acc.sat.<wbr>ll.s1(i32<br>
> > >> %v6,<br>
> > >> >> i32 %v18, i32 %v21)<br>
> > >> >> - %v23 = add nuw nsw i32 %v7, 1<br>
> > >> >> - %v24 = getelementptr i16, i16* %v3, i32 1<br>
> > >> >> - %v25 = getelementptr i16, i16* %v4, i32 1<br>
> > >> >> - br i1 %v15, label %b2, label %b1<br>
> > >> >> -<br>
> > >> >> -b2: ; preds = %b1<br>
> > >> >> - %v26 = tail call signext i16 @f1(i32 %v22) #0<br>
> > >> >> - %v27 = sext i16 %v26 to i32<br>
> > >> >> - %v28 = tail call i32<br>
> @llvm.hexagon.S2.asl.r.r.sat(<wbr>i32<br>
> > %v22,<br>
> > >> i32 %v27)<br>
> > >> >> - %v29 = tail call i32 @llvm.hexagon.A2.asrh(i32<br>
> %v28)<br>
> > >> >> - %v30 = shl i32 %v29, 16<br>
> > >> >> - %v31 = ashr exact i32 %v30, 16<br>
> > >> >> - %v32 = icmp slt i32 %v30, 65536<br>
> > >> >> - br label %b3<br>
> > >> >> -<br>
> > >> >> -b3: ; preds = %b2<br>
> > >> >> - call void @llvm.lifetime.end.p0i8(i64 80, i8*<br>
> nonnull<br>
> > %v1) #2<br>
> > >> >> - ret i16 0<br>
> > >> >> -}<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: argmemonly nounwind<br>
> > >> >> -declare void @llvm.lifetime.start.p0i8(i64, i8*<br>
> > nocapture) #1<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind readnone<br>
> > >> >> -declare i32 @llvm.hexagon.S2.asr.r.r.sat(i<wbr>32,<br>
> i32) #2<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind readnone<br>
> > >> >> -declare i32 @llvm.hexagon.A2.aslh(i32) #2<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind readnone<br>
> > >> >> -declare i32 @llvm.hexagon.A2.asrh(i32) #2<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind readnone<br>
> > >> >> -declare i32 @llvm.hexagon.M2.mpy.acc.sat.l<wbr>l.s1(i32,<br>
> > i32, i32) #2<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind<br>
> > >> >> -declare signext i16 @f1(i32) local_unnamed_addr #0<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: nounwind readnone<br>
> > >> >> -declare i32 @llvm.hexagon.S2.asl.r.r.sat(i<wbr>32,<br>
> i32) #2<br>
> > >> >> -<br>
> > >> >> -; Function Attrs: argmemonly nounwind<br>
> > >> >> -declare void @llvm.lifetime.end.p0i8(i64, i8*<br>
> nocapture) #1<br>
> > >> >> -<br>
> > >> >> -attributes #0 = { nounwind }<br>
> > >> >> -attributes #1 = { argmemonly nounwind }<br>
> > >> >> -attributes #2 = { nounwind readnone }<br>
> > >> >><br>
> > >> >> Modified:<br>
> llvm/trunk/test/CodeGen/Mips/<wbr>cconv/vector.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/cconv/vector.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/Mips/c<wbr>conv/vector.ll<br>
> (original)<br>
> > >> >> +++ llvm/trunk/test/CodeGen/Mips/c<wbr>conv/vector.ll<br>
> Wed Oct 10<br>
> > >> 07:15:52 2018<br>
> > >> >> @@ -2053,12 +2053,10 @@ define <2 x i32> @i32_2(<2 x<br>
> > i32> %a, <2<br>
> > >> >> ; MIPS64R5-NEXT: sd $4, 24($sp)<br>
> > >> >> ; MIPS64R5-NEXT: ldi.b $w0, 0<br>
> > >> >> ; MIPS64R5-NEXT: lw $1, 20($sp)<br>
> > >> >> -; MIPS64R5-NEXT: lw $2, 16($sp)<br>
> > >> >> ; MIPS64R5-NEXT: move.v $w1, $w0<br>
> > >> >> -; MIPS64R5-NEXT: insert.d $w1[0], $2<br>
> > >> >> +; MIPS64R5-NEXT: insert.d $w1[0], $5<br>
> > >> >> ; MIPS64R5-NEXT: insert.d $w1[1], $1<br>
> > >> >> -; MIPS64R5-NEXT: lw $1, 24($sp)<br>
> > >> >> -; MIPS64R5-NEXT: insert.d $w0[0], $1<br>
> > >> >> +; MIPS64R5-NEXT: insert.d $w0[0], $4<br>
> > >> >> ; MIPS64R5-NEXT: lw $1, 28($sp)<br>
> > >> >> ; MIPS64R5-NEXT: insert.d $w0[1], $1<br>
> > >> >> ; MIPS64R5-NEXT: addv.d $w0, $w0, $w1<br>
> > >> >> @@ -3533,12 +3531,8 @@ define void @call_i8_2() {<br>
> > >> >> ; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 32<br>
> > >> >> ; MIPS32R5EB-NEXT: sw $ra, 28($sp) # 4-byte<br>
> Folded<br>
> > Spill<br>
> > >> >> ; MIPS32R5EB-NEXT: .cfi_offset 31, -4<br>
> > >> >> -; MIPS32R5EB-NEXT: addiu $1, $zero, 1543<br>
> > >> >> -; MIPS32R5EB-NEXT: sh $1, 20($sp)<br>
> > >> >> -; MIPS32R5EB-NEXT: addiu $1, $zero, 3080<br>
> > >> >> -; MIPS32R5EB-NEXT: sh $1, 24($sp)<br>
> > >> >> -; MIPS32R5EB-NEXT: lhu $4, 20($sp)<br>
> > >> >> -; MIPS32R5EB-NEXT: lhu $5, 24($sp)<br>
> > >> >> +; MIPS32R5EB-NEXT: addiu $4, $zero, 1543<br>
> > >> >> +; MIPS32R5EB-NEXT: addiu $5, $zero, 3080<br>
> > >> >> ; MIPS32R5EB-NEXT: jal i8_2<br>
> > >> >> ; MIPS32R5EB-NEXT: nop<br>
> > >> >> ; MIPS32R5EB-NEXT: sw $2, 16($sp)<br>
> > >> >> @@ -3645,12 +3639,8 @@ define void @call_i8_2() {<br>
> > >> >> ; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 32<br>
> > >> >> ; MIPS32R5EL-NEXT: sw $ra, 28($sp) # 4-byte<br>
> Folded<br>
> > Spill<br>
> > >> >> ; MIPS32R5EL-NEXT: .cfi_offset 31, -4<br>
> > >> >> -; MIPS32R5EL-NEXT: addiu $1, $zero, 1798<br>
> > >> >> -; MIPS32R5EL-NEXT: sh $1, 20($sp)<br>
> > >> >> -; MIPS32R5EL-NEXT: addiu $1, $zero, 2060<br>
> > >> >> -; MIPS32R5EL-NEXT: sh $1, 24($sp)<br>
> > >> >> -; MIPS32R5EL-NEXT: lhu $4, 20($sp)<br>
> > >> >> -; MIPS32R5EL-NEXT: lhu $5, 24($sp)<br>
> > >> >> +; MIPS32R5EL-NEXT: addiu $4, $zero, 1798<br>
> > >> >> +; MIPS32R5EL-NEXT: addiu $5, $zero, 2060<br>
> > >> >> ; MIPS32R5EL-NEXT: jal i8_2<br>
> > >> >> ; MIPS32R5EL-NEXT: nop<br>
> > >> >> ; MIPS32R5EL-NEXT: sw $2, 16($sp)<br>
> > >> >><br>
> > >> >> Modified:<br>
> > >> <br>
> llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/jumptable<wbr>s.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/indirect-jump-hazard/<wbr>jumptables.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> > >><br>
> llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/jumptable<wbr>s.ll<br>
> > >> >> (original)<br>
> > >> >> +++<br>
> > >><br>
> llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/jumptable<wbr>s.ll<br>
> > >> >> Wed Oct 10 07:15:52 2018<br>
> > >> >> @@ -155,11 +155,10 @@ define i8* @_Z3fooi(i32 signext<br>
> > %Letter)<br>
> > >> >> ; MIPS64R2: # %bb.0: # %entry<br>
> > >> >> ; MIPS64R2-NEXT: daddiu $sp, $sp, -16<br>
> > >> >> ; MIPS64R2-NEXT: .cfi_def_cfa_offset 16<br>
> > >> >> -; MIPS64R2-NEXT: sw $4, 4($sp)<br>
> > >> >> -; MIPS64R2-NEXT: lwu $2, 4($sp)<br>
> > >> >> +; MIPS64R2-NEXT: dext $2, $4, 0, 32<br>
> > >> >> ; MIPS64R2-NEXT: sltiu $1, $2, 7<br>
> > >> >> ; MIPS64R2-NEXT: beqz $1, .LBB0_3<br>
> > >> >> -; MIPS64R2-NEXT: nop<br>
> > >> >> +; MIPS64R2-NEXT: sw $4, 4($sp)<br>
> > >> >> ; MIPS64R2-NEXT: .LBB0_1: # %entry<br>
> > >> >> ; MIPS64R2-NEXT: dsll $1, $2, 3<br>
> > >> >> ; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0)<br>
> > >> >> @@ -251,10 +250,10 @@ define i8* @_Z3fooi(i32 signext<br>
> > %Letter)<br>
> > >> >> ; MIPS64R6: # %bb.0: # %entry<br>
> > >> >> ; MIPS64R6-NEXT: daddiu $sp, $sp, -16<br>
> > >> >> ; MIPS64R6-NEXT: .cfi_def_cfa_offset 16<br>
> > >> >> -; MIPS64R6-NEXT: sw $4, 4($sp)<br>
> > >> >> -; MIPS64R6-NEXT: lwu $2, 4($sp)<br>
> > >> >> +; MIPS64R6-NEXT: dext $2, $4, 0, 32<br>
> > >> >> ; MIPS64R6-NEXT: sltiu $1, $2, 7<br>
> > >> >> -; MIPS64R6-NEXT: beqzc $1, .LBB0_3<br>
> > >> >> +; MIPS64R6-NEXT: beqz $1, .LBB0_3<br>
> > >> >> +; MIPS64R6-NEXT: sw $4, 4($sp)<br>
> > >> >> ; MIPS64R6-NEXT: .LBB0_1: # %entry<br>
> > >> >> ; MIPS64R6-NEXT: dsll $1, $2, 3<br>
> > >> >> ; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0)<br>
> > >> >> @@ -473,11 +472,10 @@ define i8* @_Z3fooi(i32 signext<br>
> > %Letter)<br>
> > >> >> ; PIC-MIPS64R2-NEXT: lui $1,<br>
> > %hi(%neg(%gp_rel(_Z3fooi)))<br>
> > >> >> ; PIC-MIPS64R2-NEXT: daddu $1, $1, $25<br>
> > >> >> ; PIC-MIPS64R2-NEXT: daddiu $2, $1,<br>
> > >> %lo(%neg(%gp_rel(_Z3fooi)))<br>
> > >> >> -; PIC-MIPS64R2-NEXT: sw $4, 4($sp)<br>
> > >> >> -; PIC-MIPS64R2-NEXT: lwu $3, 4($sp)<br>
> > >> >> +; PIC-MIPS64R2-NEXT: dext $3, $4, 0, 32<br>
> > >> >> ; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7<br>
> > >> >> ; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_3<br>
> > >> >> -; PIC-MIPS64R2-NEXT: nop<br>
> > >> >> +; PIC-MIPS64R2-NEXT: sw $4, 4($sp)<br>
> > >> >> ; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry<br>
> > >> >> ; PIC-MIPS64R2-NEXT: dsll $1, $3, 3<br>
> > >> >> ; PIC-MIPS64R2-NEXT: ld $3,<br>
> %got_page(.LJTI0_0)($2)<br>
> > >> >> @@ -537,10 +535,10 @@ define i8* @_Z3fooi(i32 signext<br>
> > %Letter)<br>
> > >> >> ; PIC-MIPS64R6-NEXT: lui $1,<br>
> > %hi(%neg(%gp_rel(_Z3fooi)))<br>
> > >> >> ; PIC-MIPS64R6-NEXT: daddu $1, $1, $25<br>
> > >> >> ; PIC-MIPS64R6-NEXT: daddiu $2, $1,<br>
> > >> %lo(%neg(%gp_rel(_Z3fooi)))<br>
> > >> >> -; PIC-MIPS64R6-NEXT: sw $4, 4($sp)<br>
> > >> >> -; PIC-MIPS64R6-NEXT: lwu $3, 4($sp)<br>
> > >> >> +; PIC-MIPS64R6-NEXT: dext $3, $4, 0, 32<br>
> > >> >> ; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7<br>
> > >> >> -; PIC-MIPS64R6-NEXT: beqzc $1, .LBB0_3<br>
> > >> >> +; PIC-MIPS64R6-NEXT: beqz $1, .LBB0_3<br>
> > >> >> +; PIC-MIPS64R6-NEXT: sw $4, 4($sp)<br>
> > >> >> ; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry<br>
> > >> >> ; PIC-MIPS64R6-NEXT: dsll $1, $3, 3<br>
> > >> >> ; PIC-MIPS64R6-NEXT: ld $3,<br>
> %got_page(.LJTI0_0)($2)<br>
> > >> >><br>
> > >> >> Modified:<br>
> llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_byval.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/Mips/o<wbr>32_cc_byval.ll<br>
> (original)<br>
> > >> >> +++ llvm/trunk/test/CodeGen/Mips/o<wbr>32_cc_byval.ll<br>
> Wed Oct 10<br>
> > >> 07:15:52 2018<br>
> > >> >> @@ -109,7 +109,8 @@ define void @f2(float %f,<br>
> %struct.S1* no<br>
> > >> >> ; CHECK-NEXT: lw $1, 64($sp)<br>
> > >> >> ; CHECK-NEXT: lw $2, 68($sp)<br>
> > >> >> ; CHECK-NEXT: lh $3, 58($sp)<br>
> > >> >> -; CHECK-NEXT: lb $5, 56($sp)<br>
> > >> >> +; CHECK-NEXT: sll $5, $6, 24<br>
> > >> >> +; CHECK-NEXT: sra $5, $5, 24<br>
> > >> >> ; CHECK-NEXT: swc1 $f12, 36($sp)<br>
> > >> >> ; CHECK-NEXT: sw $5, 32($sp)<br>
> > >> >> ; CHECK-NEXT: sw $3, 28($sp)<br>
> > >> >> @@ -191,11 +192,12 @@ define void @f4(float %f,<br>
> > %struct.S3* no<br>
> > >> >> ; CHECK-NEXT: sw $ra, 44($sp) # 4-byte<br>
> Folded Spill<br>
> > >> >> ; CHECK-NEXT: addu $gp, $2, $25<br>
> > >> >> ; CHECK-NEXT: move $4, $7<br>
> > >> >> -; CHECK-NEXT: sw $5, 52($sp)<br>
> > >> >> ; CHECK-NEXT: sw $6, 56($sp)<br>
> > >> >> +; CHECK-NEXT: sw $5, 52($sp)<br>
> > >> >> ; CHECK-NEXT: sw $7, 60($sp)<br>
> > >> >> ; CHECK-NEXT: lw $1, 80($sp)<br>
> > >> >> -; CHECK-NEXT: lb $2, 52($sp)<br>
> > >> >> +; CHECK-NEXT: sll $2, $5, 24<br>
> > >> >> +; CHECK-NEXT: sra $2, $2, 24<br>
> > >> >> ; CHECK-NEXT: addiu $3, $zero, 4<br>
> > >> >> ; CHECK-NEXT: lui $5, 16576<br>
> > >> >> ; CHECK-NEXT: sw $5, 36($sp)<br>
> > >> >><br>
> > >> >> Modified:<br>
> llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/Mips/o32_cc_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/Mips/o<wbr>32_cc_vararg.ll<br>
> (original)<br>
> > >> >> +++ llvm/trunk/test/CodeGen/Mips/o<wbr>32_cc_vararg.ll<br>
> Wed Oct 10<br>
> > >> 07:15:52<br>
> > >> >> 2018<br>
> > >> >> @@ -29,10 +29,10 @@ entry:<br>
> > >> >> ; CHECK-LABEL: va1:<br>
> > >> >> ; CHECK: addiu $sp, $sp, -16<br>
> > >> >> -; CHECK: sw $5, 20($sp)<br>
> > >> >> ; CHECK: sw $7, 28($sp)<br>
> > >> >> ; CHECK: sw $6, 24($sp)<br>
> > >> >> -; CHECK: lw $2, 20($sp)<br>
> > >> >> +; CHECK: sw $5, 20($sp)<br>
> > >> >> +; CHECK: move $2, $5<br>
> > >> >> }<br>
> > >> >> ; check whether the variable double argument<br>
> will be<br>
> > accessed<br>
> > >> from<br>
> > >> >> the 8-byte<br>
> > >> >> @@ -83,9 +83,9 @@ entry:<br>
> > >> >> ; CHECK-LABEL: va3:<br>
> > >> >> ; CHECK: addiu $sp, $sp, -16<br>
> > >> >> -; CHECK: sw $6, 24($sp)<br>
> > >> >> ; CHECK: sw $7, 28($sp)<br>
> > >> >> -; CHECK: lw $2, 24($sp)<br>
> > >> >> +; CHECK: sw $6, 24($sp)<br>
> > >> >> +; CHECK: move $2, $6<br>
> > >> >> }<br>
> > >> >> ; double<br>
> > >> >> @@ -135,7 +135,7 @@ entry:<br>
> > >> >> ; CHECK-LABEL: va5:<br>
> > >> >> ; CHECK: addiu $sp, $sp, -24<br>
> > >> >> ; CHECK: sw $7, 36($sp)<br>
> > >> >> -; CHECK: lw $2, 36($sp)<br>
> > >> >> +; CHECK: move $2, $7<br>
> > >> >> }<br>
> > >> >> ; double<br>
> > >> >><br>
> > >> >> Modified:<br>
> > llvm/trunk/test/CodeGen/Power<wbr>PC/addi-offset-fold.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/PowerPC/addi-offset-fold.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/test/CodeGen/Power<wbr>PC/addi-offset-fold.ll<br>
> > >> (original)<br>
> > >> >> +++<br>
> llvm/trunk/test/CodeGen/Power<wbr>PC/addi-offset-fold.ll Wed<br>
> > >> Oct 10<br>
> > >> >> 07:15:52 2018<br>
> > >> >> @@ -24,12 +24,11 @@ entry:<br>
> > >> >> ret i32 %bf.cast<br>
> > >> >> ; CHECK-LABEL: @foo<br>
> > >> >> -; FIXME: We don't need to do these stores/loads<br>
> at all.<br>
> > >> >> +; FIXME: We don't need to do these stores at all.<br>
> > >> >> ; CHECK-DAG: std 3, -24(1)<br>
> > >> >> ; CHECK-DAG: stb 4, -16(1)<br>
> > >> >> -; CHECK-DAG: lbz [[REG1:[0-9]+]], -16(1)<br>
> > >> >> +; CHECK-DAG: sldi [[REG3:[0-9]+]], 4, 32<br>
> > >> >> ; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)<br>
> > >> >> -; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG1]], 32<br>
> > >> >> ; CHECK-DAG: or [[REG4:[0-9]+]], [[REG2]], [[REG3]]<br>
> > >> >> ; CHECK: rldicl 3, [[REG4]], 33, 57<br>
> > >> >> ; CHECK: blr<br>
> > >> >><br>
> > >> >> Modified:<br>
> > >> llvm/trunk/test/CodeGen/System<wbr>Z/store_nonbytesized_vecs.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/SystemZ/store_nonbytesized_<wbr>vecs.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> > llvm/trunk/test/CodeGen/Syste<wbr>mZ/store_nonbytesized_vecs.ll<br>
> > >> (original)<br>
> > >> >> +++<br>
> > llvm/trunk/test/CodeGen/Syste<wbr>mZ/store_nonbytesized_vecs.ll<br>
> > >> Wed Oct<br>
> > >> >> 10 07:15:52 2018<br>
> > >> >> @@ -60,8 +60,7 @@ define i16 @fun1(<16 x i1> %src)<br>
> > >> >> ; CHECK-NEXT: rosbg %r0, %r1, 62, 62, 1<br>
> > >> >> ; CHECK-NEXT: vlgvb %r1, %v24, 15<br>
> > >> >> ; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 0<br>
> > >> >> -; CHECK-NEXT: sth %r0, 160(%r15)<br>
</div></div><span>> > >> >> -; CHECK-NEXT: lh %r2, 160(%r15)<br>
> > >> >> +; CHECK-NEXT: llhr %r2, %r0<br>
> > >> >> ; CHECK-NEXT: aghi %r15, 168<br>
> > >> >> ; CHECK-NEXT: br %r14<br>
> > >> >> {<br>
> > >> >><br>
> > >> >> Modified:<br>
> > llvm/trunk/test/CodeGen/X86/i<wbr>386-shrink-wrapping.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/i386-shrink-wrapping.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> ---<br>
> llvm/trunk/test/CodeGen/X86/i<wbr>386-shrink-wrapping.ll<br>
> > >> (original)<br>
> > >> >> +++<br>
</span>> llvm/trunk/test/CodeGen/X86/i<wbr>386-shrink-wrapping.ll Wed<br>
<span>> > >> Oct 10<br>
> > >> >> 07:15:52 2018<br>
</span><span>> > >> >> @@ -56,7 +56,7 @@ target triple =<br>
> "i386-apple-macosx10.5"<br>
> > >> >> ;<br>
> > >> >> ; CHECK-NEXT: L_e$non_lazy_ptr, [[E:%[a-z]+]]<br>
> > >> >> ; CHECK-NEXT: movb %dl, ([[E]])<br>
> > >> >> -; CHECK-NEXT: movsbl ([[E]]), [[CONV:%[a-z]+]]<br>
> > >> >> +; CHECK-NEXT: movzbl %dl, [[CONV:%[a-z]+]]<br>
> > >> >> ; CHECK-NEXT: movl $6, [[CONV:%[a-z]+]]<br>
> > >> >> ; The eflags is used in the next instruction.<br>
> > >> >> ; If that instruction disappear, we are not<br>
> exercising<br>
> > the bug<br>
> > >> >><br>
> > >> >> Modified: llvm/trunk/test/CodeGen/X86/pr<wbr>32108.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr32108.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr32108.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr32108.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr32108.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr32108.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr32108.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr32108.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr32108.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/X86/pr<wbr>32108.ll (original)<br>
</span>> > >> >> +++ llvm/trunk/test/CodeGen/X86/pr<wbr>32108.ll Wed Oct 10<br>
> > 07:15:52<br>
> > >> 2018<br>
<span>> > >> >> @@ -4,7 +4,6 @@<br>
> > >> >> define void @pr32108() {<br>
> > >> >> ; CHECK-LABEL: pr32108:<br>
> > >> >> ; CHECK: # %bb.0: # %BB<br>
> > >> >> -; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)<br>
> > >> >> ; CHECK-NEXT: .p2align 4, 0x90<br>
> > >> >> ; CHECK-NEXT: .LBB0_1: # %CF244<br>
> > >> >> ; CHECK-NEXT: # =>This Inner Loop Header:<br>
> Depth=1<br>
> > >> >><br>
> > >> >> Modified: llvm/trunk/test/CodeGen/X86/pr<wbr>38533.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr38533.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr38533.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr38533.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr38533.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr38533.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr38533.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/pr38533.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/pr38533.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/X86/pr<wbr>38533.ll (original)<br>
</span>> > >> >> +++ llvm/trunk/test/CodeGen/X86/pr<wbr>38533.ll Wed Oct 10<br>
> > 07:15:52<br>
> > >> 2018<br>
<div><div>> > >> >> @@ -19,8 +19,6 @@ define void @pr38533_2(half %x) {<br>
> > >> >> ; SSE-NEXT: pushq %rax<br>
> > >> >> ; SSE-NEXT: .cfi_def_cfa_offset 16<br>
> > >> >> ; SSE-NEXT: callq __gnu_f2h_ieee<br>
> > >> >> -; SSE-NEXT: movw %ax, {{[0-9]+}}(%rsp)<br>
> > >> >> -; SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax<br>
> > >> >> ; SSE-NEXT: movw %ax, (%rax)<br>
> > >> >> ; SSE-NEXT: popq %rax<br>
> > >> >> ; SSE-NEXT: .cfi_def_cfa_offset 8<br>
> > >> >> @@ -30,8 +28,6 @@ define void @pr38533_2(half %x) {<br>
> > >> >> ; AVX512: # %bb.0:<br>
> > >> >> ; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0<br>
> > >> >> ; AVX512-NEXT: vmovd %xmm0, %eax<br>
> > >> >> -; AVX512-NEXT: movw %ax, -{{[0-9]+}}(%rsp)<br>
> > >> >> -; AVX512-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax<br>
> > >> >> ; AVX512-NEXT: movw %ax, (%rax)<br>
> > >> >> ; AVX512-NEXT: retq<br>
> > >> >> %a = bitcast half %x to <4 x i4><br>
> > >> >> @@ -46,8 +42,6 @@ define void @pr38533_3(half %x) {<br>
> > >> >> ; SSE-NEXT: pushq %rax<br>
> > >> >> ; SSE-NEXT: .cfi_def_cfa_offset 16<br>
> > >> >> ; SSE-NEXT: callq __gnu_f2h_ieee<br>
> > >> >> -; SSE-NEXT: movw %ax, (%rsp)<br>
> > >> >> -; SSE-NEXT: movzwl (%rsp), %eax<br>
> > >> >> ; SSE-NEXT: movw %ax, (%rax)<br>
> > >> >> ; SSE-NEXT: popq %rax<br>
> > >> >> ; SSE-NEXT: .cfi_def_cfa_offset 8<br>
> > >> >><br>
> > >> >> Modified: llvm/trunk/test/CodeGen/X86/wi<wbr>n64_vararg.ll<br>
> > >> >> URL:<br>
> > >> >><br>
> > >><br>
> > >><br>
> ><br>
> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a><br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>><br>
> ><br>
> > >><br>
> > >><br>
> > >><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>><br>
> > <br>
> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/CodeGe<wbr>n/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-p<wbr>roject/llvm/trunk/test/CodeGen<wbr>/X86/win64_vararg.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a>>>><br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >><br>
> > >><br>
> > >><br>
> > <br>
> =============================<wbr>==============================<wbr>===================<br>
> ><br>
> > >><br>
> > >><br>
> > >> >><br>
> > >> >> --- llvm/trunk/test/CodeGen/X86/wi<wbr>n64_vararg.ll<br>
> (original)<br>
> > >> >> +++ llvm/trunk/test/CodeGen/X86/wi<wbr>n64_vararg.ll<br>
</div></div><span>> Wed Oct 10<br>
> > >> 07:15:52 2018<br>
</span><span>> > >> >> @@ -124,7 +124,8 @@ entry:<br>
> > >> >> ; CHECK: movq %rcx, %rax<br>
> > >> >> ; CHECK-DAG: movq %r9, 40(%rsp)<br>
> > >> >> ; CHECK-DAG: movq %r8, 32(%rsp)<br>
> > >> >> -; CHECK: movl 32(%rsp), %[[tmp:[^ ]*]]<br>
> > >> >> -; CHECK: movl %[[tmp]], (%rax)<br>
> > >> >> +; CHECK-DAG: leaq 36(%rsp), %[[sret:[^ ]*]]<br>
> > >> >> +; CHECK-DAG: movl %r8d, (%rax)<br>
> > >> >> +; CHECK-DAG: movq %[[sret]], (%rsp)<br>
> > >> >> ; CHECK: popq<br>
> > >> >> ; CHECK: retq<br>
> > >> >><br>
> > >> >><br>
> > >> >> ______________________________<wbr>_________________<br>
> > >> >> llvm-commits mailing list<br>
> > >> >> <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
> <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.ll<wbr>vm.org</a>><br>
> > <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.ll<wbr>vm.org</a><br>
> <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.ll<wbr>vm.org</a>>><br>
> > <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.ll<wbr>vm.org</a><br>
> <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.ll<wbr>vm.org</a>><br>
</span>> > <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.ll<wbr>vm.org</a> <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llv<wbr>m.org</a>>>><br>
<div><div>> > >> >><br>
> > <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-<wbr>bin/mailman/listinfo/llvm-<wbr>commits</a><br>
> <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a>><br>
> > <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a><br>
> <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a>>><br>
> > >> <br>
> <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a><br>
> <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a>><br>
> > <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a><br>
> <<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bi<wbr>n/mailman/listinfo/llvm-commit<wbr>s</a>>>><br>
> > >> >><br>
> > >><br>
> > >><br>
> > ><br>
> ><br>
> ><br>
> <br>
> <br>
<br>
</div></div></blockquote></div><br></div>
</blockquote></div><br></div>