<div dir="ltr"><div dir="ltr">Should be fixed in rL344272.<br></div><div dir="ltr"><br></div><div>Thanks for the catch.</div><div><br></div><div>-Nirav</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Oct 11, 2018 at 7:41 AM, Mikael Holmén <span dir="ltr"><<a href="mailto:mikael.holmen@ericsson.com" target="_blank">mikael.holmen@ericsson.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<br>
Reproducer for powerpc:<br>
<br>
llc bug.ll -o - -O1<br>
<br>
Without the patch we get<br>
<br>
addis 4, 2, .LC0@toc@ha<br>
sth 3, -2(1)<br>
ld 4, .LC0@toc@l(4)<br>
lbz 3, -2(1)<br>
stb 3, 0(4)<br>
blr<br>
<br>
and with<br>
<br>
addis 4, 2, .LC0@toc@ha<br>
sth 3, -2(1)<br>
ld 4, .LC0@toc@l(4)<br>
stb 3, 0(4)<br>
blr<br>
<br>
Admittedly I'm no ppc expert but I think the final stb will write bits <br>
[0-7] of 3 to 0(4).<br>
<br>
Before your patch those 8 bits were setup from the<br>
<br>
lbz 3, -2(1)<br>
<br>
but with the patch, I think the bits we're after are placed at bit <br>
[8-15] in 3 so we'll get the wrong byte.<br>
<span class="HOEnZb"><font color="#888888"><br>
/Mikael<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
On 10/11/2018 12:54 PM, Mikael Holmén wrote:<br>
> Hi Nirav,<br>
> <br>
> I suspect that this patch doesn't handle big endian targets correctly.<br>
> <br>
> I'll try to get back with a reproducer for some in-tree target, but for <br>
> my out-of-tree bigendian target it looks like it changes somethng like<br>
> <br>
> store i16 %v, i16* %p16<br>
> %p8 = bitcast i16* %p16 to i8*<br>
> %ld = load i16, i16* %p8<br>
> <br>
> to<br>
> <br>
> store i16 %v, i16* %p16<br>
> %ld = truncate i16 %v to i8<br>
> <br>
> but I think it should rather be<br>
> <br>
> store i16 %v, i16* %p16<br>
> %tmp = lshr i16 %v, 8<br>
> %ld = truncate i16 %tmp to i8<br>
> <br>
> I.e. if the target is bigendian, the load will read the high 8 bits from <br>
> %v rather than the low. And the truncate that this patch generates gives <br>
> us the low bits.<br>
> <br>
> Regards,<br>
> Mikael<br>
> <br>
> On 10/10/2018 04:15 PM, Nirav Dave via llvm-commits wrote:<br>
>> Author: niravd<br>
>> Date: Wed Oct 10 07:15:52 2018<br>
>> New Revision: 344142<br>
>><br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=344142&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=344142&view=rev</a><br>
>> Log:<br>
>> [DAGCombine] Improve Load-Store Forwarding<br>
>><br>
>> Summary:<br>
>> Extend analysis forwarding loads from preceeding stores to work with<br>
>> extended loads and truncated stores to the same address so long as the<br>
>> load is fully subsumed by the store.<br>
>><br>
>> Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are<br>
>> deleted as they've no longer seem to be relevant.<br>
>><br>
>> Reviewers: RKSimon, rnk, kparzysz, javed.absar<br>
>><br>
>> Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits<br>
>><br>
>> Differential Revision: <a href="https://reviews.llvm.org/D49200" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D49200</a><br>
>><br>
>> Removed:<br>
>> llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-phis.ll<br>
>> llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-memrefs-epilog1.ll<br>
>> Modified:<br>
>> llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
>> llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-ld-from-st.ll<br>
>> llvm/trunk/test/CodeGen/<wbr>AArch64/regress-tblgen-chains.<wbr>ll<br>
>> llvm/trunk/test/CodeGen/<wbr>Hexagon/clr_set_toggle.ll<br>
>> llvm/trunk/test/CodeGen/Mips/<wbr>cconv/vector.ll<br>
>> llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/<wbr>jumptables.ll<br>
>> llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll<br>
>> llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll<br>
>> llvm/trunk/test/CodeGen/<wbr>PowerPC/addi-offset-fold.ll<br>
>> llvm/trunk/test/CodeGen/<wbr>SystemZ/store_nonbytesized_<wbr>vecs.ll<br>
>> llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll<br>
>> llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll<br>
>> llvm/trunk/test/CodeGen/X86/<wbr>pr38533.ll<br>
>> llvm/trunk/test/CodeGen/X86/<wbr>win64_vararg.ll<br>
>><br>
>> Modified: llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/SelectionDAG/<wbr>DAGCombiner.cpp?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp (original)<br>
>> +++ llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp Wed Oct 10 <br>
>> 07:15:52 2018<br>
>> @@ -250,6 +250,11 @@ namespace {<br>
>> SDValue SplitIndexingFromLoad(<wbr>LoadSDNode *LD);<br>
>> bool SliceUpLoad(SDNode *N);<br>
>> + // Scalars have size 0 to distinguish from singleton vectors.<br>
>> + SDValue ForwardStoreValueToDirectLoad(<wbr>LoadSDNode *LD);<br>
>> + bool getTruncatedStoreValue(<wbr>StoreSDNode *ST, SDValue &Val);<br>
>> + bool extendLoadedValueToExtension(<wbr>LoadSDNode *LD, SDValue &Val);<br>
>> +<br>
>> /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed<br>
>> /// load.<br>
>> ///<br>
>> @@ -12762,6 +12767,133 @@ SDValue DAGCombiner::<wbr>SplitIndexingFromLo<br>
>> return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);<br>
>> }<br>
>> +static inline int numVectorEltsOrZero(EVT T) {<br>
>> + return T.isVector() ? T.getVectorNumElements() : 0;<br>
>> +}<br>
>> +<br>
>> +bool DAGCombiner::<wbr>getTruncatedStoreValue(<wbr>StoreSDNode *ST, SDValue <br>
>> &Val) {<br>
>> + Val = ST->getValue();<br>
>> + EVT STType = Val.getValueType();<br>
>> + EVT STMemType = ST->getMemoryVT();<br>
>> + if (STType == STMemType)<br>
>> + return true;<br>
>> + if (isTypeLegal(STMemType))<br>
>> + return false; // fail.<br>
>> + if (STType.isFloatingPoint() && STMemType.isFloatingPoint() &&<br>
>> + TLI.isOperationLegal(ISD::<wbr>FTRUNC, STMemType)) {<br>
>> + Val = DAG.getNode(ISD::FTRUNC, SDLoc(ST), STMemType, Val);<br>
>> + return true;<br>
>> + }<br>
>> + if (numVectorEltsOrZero(STType) == numVectorEltsOrZero(STMemType) &&<br>
>> + STType.isInteger() && STMemType.isInteger()) {<br>
>> + Val = DAG.getNode(ISD::TRUNCATE, SDLoc(ST), STMemType, Val);<br>
>> + return true;<br>
>> + }<br>
>> + if (STType.getSizeInBits() == STMemType.getSizeInBits()) {<br>
>> + Val = DAG.getBitcast(STMemType, Val);<br>
>> + return true;<br>
>> + }<br>
>> + return false; // fail.<br>
>> +}<br>
>> +<br>
>> +bool DAGCombiner::<wbr>extendLoadedValueToExtension(<wbr>LoadSDNode *LD, <br>
>> SDValue &Val) {<br>
>> + EVT LDMemType = LD->getMemoryVT();<br>
>> + EVT LDType = LD->getValueType(0);<br>
>> + assert(Val.getValueType() == LDMemType &&<br>
>> + "Attempting to extend value of non-matching type");<br>
>> + if (LDType == LDMemType)<br>
>> + return true;<br>
>> + if (LDMemType.isInteger() && LDType.isInteger()) {<br>
>> + switch (LD->getExtensionType()) {<br>
>> + case ISD::NON_EXTLOAD:<br>
>> + Val = DAG.getBitcast(LDType, Val);<br>
>> + return true;<br>
>> + case ISD::EXTLOAD:<br>
>> + Val = DAG.getNode(ISD::ANY_EXTEND, SDLoc(LD), LDType, Val);<br>
>> + return true;<br>
>> + case ISD::SEXTLOAD:<br>
>> + Val = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(LD), LDType, Val);<br>
>> + return true;<br>
>> + case ISD::ZEXTLOAD:<br>
>> + Val = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(LD), LDType, Val);<br>
>> + return true;<br>
>> + }<br>
>> + }<br>
>> + return false;<br>
>> +}<br>
>> +<br>
>> +SDValue DAGCombiner::<wbr>ForwardStoreValueToDirectLoad(<wbr>LoadSDNode *LD) {<br>
>> + if (OptLevel == CodeGenOpt::None || LD->isVolatile())<br>
>> + return SDValue();<br>
>> + SDValue Chain = LD->getOperand(0);<br>
>> + StoreSDNode *ST = dyn_cast<StoreSDNode>(Chain.<wbr>getNode());<br>
>> + if (!ST || ST->isVolatile())<br>
>> + return SDValue();<br>
>> +<br>
>> + EVT LDType = LD->getValueType(0);<br>
>> + EVT LDMemType = LD->getMemoryVT();<br>
>> + EVT STMemType = ST->getMemoryVT();<br>
>> + EVT STType = ST->getValue().getValueType();<br>
>> +<br>
>> + BaseIndexOffset BasePtrLD = BaseIndexOffset::match(LD, DAG);<br>
>> + BaseIndexOffset BasePtrST = BaseIndexOffset::match(ST, DAG);<br>
>> + int64_t Offset;<br>
>> +<br>
>> + bool STCoversLD =<br>
>> + BasePtrST.equalBaseIndex(<wbr>BasePtrLD, DAG, Offset) && (Offset >= <br>
>> 0) &&<br>
>> + (Offset * 8 <= LDMemType.getSizeInBits()) &&<br>
>> + (Offset * 8 + LDMemType.getSizeInBits() <= <br>
>> STMemType.getSizeInBits());<br>
>> +<br>
>> + if (!STCoversLD)<br>
>> + return SDValue();<br>
>> +<br>
>> + // Memory as copy space (potentially masked).<br>
>> + if (Offset == 0 && LDType == STType && STMemType == LDMemType) {<br>
>> + // Simple case: Direct non-truncating forwarding<br>
>> + if (LDType.getSizeInBits() == LDMemType.getSizeInBits())<br>
>> + return CombineTo(LD, ST->getValue(), Chain);<br>
>> + // Can we model the truncate and extension with an and mask?<br>
>> + if (STType.isInteger() && LDMemType.isInteger() && <br>
>> !STType.isVector() &&<br>
>> + !LDMemType.isVector() && LD->getExtensionType() != <br>
>> ISD::SEXTLOAD) {<br>
>> + // Mask to size of LDMemType<br>
>> + auto Mask =<br>
>> + DAG.getConstant(APInt::<wbr>getLowBitsSet(STType.<wbr>getSizeInBits(),<br>
>> + <br>
>> STMemType.getSizeInBits()),<br>
>> + SDLoc(ST), STType);<br>
>> + auto Val = DAG.getNode(ISD::AND, SDLoc(LD), LDType, <br>
>> ST->getValue(), Mask);<br>
>> + return CombineTo(LD, Val, Chain);<br>
>> + }<br>
>> + }<br>
>> +<br>
>> + // TODO: Deal with nonzero offset.<br>
>> + if (LD->getBasePtr().isUndef() || Offset != 0)<br>
>> + return SDValue();<br>
>> + // Model necessary truncations / extenstions.<br>
>> + SDValue Val;<br>
>> + // Truncate Value To Stored Memory Size.<br>
>> + do {<br>
>> + if (!getTruncatedStoreValue(ST, Val))<br>
>> + continue;<br>
>> + if (!isTypeLegal(LDMemType))<br>
>> + continue;<br>
>> + if (STMemType != LDMemType) {<br>
>> + if (numVectorEltsOrZero(<wbr>STMemType) == <br>
>> numVectorEltsOrZero(LDMemType) &&<br>
>> + STMemType.isInteger() && LDMemType.isInteger())<br>
>> + Val = DAG.getNode(ISD::TRUNCATE, SDLoc(LD), LDMemType, Val);<br>
>> + else<br>
>> + continue;<br>
>> + }<br>
>> + if (!<wbr>extendLoadedValueToExtension(<wbr>LD, Val))<br>
>> + continue;<br>
>> + return CombineTo(LD, Val, Chain);<br>
>> + } while (false);<br>
>> +<br>
>> + // On failure, cleanup dead nodes we may have created.<br>
>> + if (Val->use_empty())<br>
>> + deleteAndRecombine(Val.<wbr>getNode());<br>
>> + return SDValue();<br>
>> +}<br>
>> +<br>
>> SDValue DAGCombiner::visitLOAD(SDNode *N) {<br>
>> LoadSDNode *LD = cast<LoadSDNode>(N);<br>
>> SDValue Chain = LD->getChain();<br>
>> @@ -12828,17 +12960,8 @@ SDValue DAGCombiner::visitLOAD(SDNode *N<br>
>> // If this load is directly stored, replace the load value with <br>
>> the stored<br>
>> // value.<br>
>> - // TODO: Handle store large -> read small portion.<br>
>> - // TODO: Handle TRUNCSTORE/LOADEXT<br>
>> - if (OptLevel != CodeGenOpt::None &&<br>
>> - ISD::isNormalLoad(N) && !LD->isVolatile()) {<br>
>> - if (ISD::isNON_TRUNCStore(Chain.<wbr>getNode())) {<br>
>> - StoreSDNode *PrevST = cast<StoreSDNode>(Chain);<br>
>> - if (PrevST->getBasePtr() == Ptr &&<br>
>> - PrevST->getValue().<wbr>getValueType() == N->getValueType(0))<br>
>> - return CombineTo(N, PrevST->getOperand(1), Chain);<br>
>> - }<br>
>> - }<br>
>> + if (auto V = ForwardStoreValueToDirectLoad(<wbr>LD))<br>
>> + return V;<br>
>> // Try to infer better alignment information than the load already <br>
>> has.<br>
>> if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-ld-from-st.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ld-from-st.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-ld-from-<wbr>st.ll?rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-ld-from-st.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-ld-from-st.ll Wed Oct 10 <br>
>> 07:15:52 2018<br>
>> @@ -13,7 +13,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str64Ldr32_0<br>
>> -; CHECK: and x0, x1, #0xffffffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i32 @Str64Ldr32_0(i64* nocapture %P, i64 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i64* %P to i32*<br>
>> @@ -37,7 +37,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str64Ldr16_0<br>
>> -; CHECK: and x0, x1, #0xffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i16 @Str64Ldr16_0(i64* nocapture %P, i64 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i64* %P to i16*<br>
>> @@ -85,7 +85,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str64Ldr8_0<br>
>> -; CHECK: and x0, x1, #0xff<br>
>> +; CHECK: mov w0, w1<br>
>> define i8 @Str64Ldr8_0(i64* nocapture %P, i64 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i64* %P to i8*<br>
>> @@ -193,7 +193,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str32Ldr16_0<br>
>> -; CHECK: and w0, w1, #0xffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i16 @Str32Ldr16_0(i32* nocapture %P, i32 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i32* %P to i16*<br>
>> @@ -217,7 +217,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str32Ldr8_0<br>
>> -; CHECK: and w0, w1, #0xff<br>
>> +; CHECK: mov w0, w1<br>
>> define i8 @Str32Ldr8_0(i32* nocapture %P, i32 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i32* %P to i8*<br>
>> @@ -265,7 +265,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str16Ldr16<br>
>> -; CHECK: and w0, w1, #0xffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i16 @Str16Ldr16(i16* nocapture %P, i16 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i16* %P to i16*<br>
>> @@ -277,7 +277,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Str16Ldr8_0<br>
>> -; CHECK: and w0, w1, #0xff<br>
>> +; CHECK: mov w0, w1<br>
>> define i8 @Str16Ldr8_0(i16* nocapture %P, i16 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i16* %P to i8*<br>
>> @@ -314,7 +314,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str64Ldr32_0<br>
>> -; CHECK: and x0, x1, #0xffffffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i32 @Unscaled_Str64Ldr32_0(i64* nocapture %P, i64 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i64* %P to i32*<br>
>> @@ -338,7 +338,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str64Ldr16_0<br>
>> -; CHECK: and x0, x1, #0xffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i16 @Unscaled_Str64Ldr16_0(i64* nocapture %P, i64 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i64* %P to i16*<br>
>> @@ -386,7 +386,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str64Ldr8_0<br>
>> -; CHECK: and x0, x1, #0xff<br>
>> +; CHECK: mov w0, w1<br>
>> define i8 @Unscaled_Str64Ldr8_0(i64* nocapture %P, i64 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i64* %P to i8*<br>
>> @@ -494,7 +494,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str32Ldr16_0<br>
>> -; CHECK: and w0, w1, #0xffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i16 @Unscaled_Str32Ldr16_0(i32* nocapture %P, i32 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i32* %P to i16*<br>
>> @@ -518,7 +518,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str32Ldr8_0<br>
>> -; CHECK: and w0, w1, #0xff<br>
>> +; CHECK: mov w0, w1<br>
>> define i8 @Unscaled_Str32Ldr8_0(i32* nocapture %P, i32 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i32* %P to i8*<br>
>> @@ -566,7 +566,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str16Ldr16<br>
>> -; CHECK: and w0, w1, #0xffff<br>
>> +; CHECK: mov w0, w1<br>
>> define i16 @Unscaled_Str16Ldr16(i16* nocapture %P, i16 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i16* %P to i16*<br>
>> @@ -578,7 +578,7 @@ entry:<br>
>> }<br>
>> ; CHECK-LABEL: Unscaled_Str16Ldr8_0<br>
>> -; CHECK: and w0, w1, #0xff<br>
>> +; CHECK: mov w0, w1<br>
>> define i8 @Unscaled_Str16Ldr8_0(i16* nocapture %P, i16 %v, i64 %n) {<br>
>> entry:<br>
>> %0 = bitcast i16* %P to i8*<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/regress-tblgen-chains.<wbr>ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/regress-<wbr>tblgen-chains.ll?rev=344142&<wbr>r1=344141&r2=344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>AArch64/regress-tblgen-chains.<wbr>ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>AArch64/regress-tblgen-chains.<wbr>ll Wed Oct <br>
>> 10 07:15:52 2018<br>
>> @@ -26,9 +26,9 @@ define i64 @test_chains() {<br>
>> store i8 %inc.4, i8* %locvar<br>
>> ; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]<br>
>> -; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1<br>
>> +; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #1<br>
>> ; CHECK: sturb w[[STRVAL:[0-9]+]], [x29, [[LOCADDR]]]<br>
>> -; CHECK: and w0, w[[STRVAL]], #0xff<br>
>> +; CHECK: and x0, x[[STRVAL]], #0xff<br>
>> %ret.1 = load i8, i8* %locvar<br>
>> %ret.2 = zext i8 %ret.1 to i64<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/clr_set_toggle.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/clr_set_<wbr>toggle.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>Hexagon/clr_set_toggle.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>Hexagon/clr_set_toggle.ll Wed Oct 10 <br>
>> 07:15:52 2018<br>
>> @@ -70,7 +70,7 @@ entry:<br>
>> define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {<br>
>> entry:<br>
>> ; CHECK-LABEL: my_setbit<br>
>> -; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}) = setbit(#15)<br>
>> +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)<br>
>> %crc.addr = alloca i16, align 2<br>
>> store i16 %crc, i16* %crc.addr, align 2<br>
>> %0 = load i16, i16* %crc.addr, align 2<br>
>><br>
>> Removed: llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-phis.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phis.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/swp-epilog-<wbr>phis.ll?rev=344141&view=auto</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-phis.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-epilog-phis.ll (removed)<br>
>> @@ -1,55 +0,0 @@<br>
>> -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 \<br>
>> -; RUN: -pipeliner-ignore-recmii -disable-hexagon-nv-schedule \<br>
>> -; RUN: -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null \<br>
>> -; RUN: -enable-aa-sched-mi < %s 2>&1 | FileCheck %s <br>
>> --check-prefix=STATS<br>
>> -; REQUIRES: asserts<br>
>> -;<br>
>> -; Test that we generate the correct phis in the last epilog block when<br>
>> -; allowing multiple stages.<br>
>> -;<br>
>> -; STATS: 1 pipeliner - Number of loops software pipelined<br>
>> -<br>
>> -; Function Attrs: nounwind<br>
>> -define void @f0() #0 {<br>
>> -b0:<br>
>> - br i1 undef, label %b6, label %b1<br>
>> -<br>
>> -b1: <wbr> ; preds = %b0<br>
>> - br i1 undef, label %b6, label %b2<br>
>> -<br>
>> -b2: <wbr> ; preds = %b1<br>
>> - br label %b4<br>
>> -<br>
>> -b3: <wbr> ; preds = %b4, %b3<br>
>> - %v0 = add nsw i32 0, 57344<br>
>> - %v1 = trunc i32 %v0 to i16<br>
>> - store i16 %v1, i16* null, align 2, !tbaa !0<br>
>> - %v2 = getelementptr inbounds i8, i8* null, i32 undef<br>
>> - %v3 = load i8, i8* %v2, align 1, !tbaa !4<br>
>> - %v4 = zext i8 %v3 to i32<br>
>> - %v5 = shl nuw nsw i32 %v4, 6<br>
>> - %v6 = add nsw i32 %v5, 57344<br>
>> - %v7 = trunc i32 %v6 to i16<br>
>> - store i16 %v7, i16* undef, align 2, !tbaa !0<br>
>> - br i1 undef, label %b5, label %b3<br>
>> -<br>
>> -b4: <wbr> ; preds = %b5, %b2<br>
>> - %v8 = phi i32 [ 0, %b2 ], [ %v9, %b5 ]<br>
>> - br label %b3<br>
>> -<br>
>> -b5: <wbr> ; preds = %b3<br>
>> - %v9 = add i32 %v8, 1<br>
>> - %v10 = icmp eq i32 %v9, undef<br>
>> - br i1 %v10, label %b6, label %b4<br>
>> -<br>
>> -b6: <wbr> ; preds = %b5, %b1, <br>
>> %b0<br>
>> - ret void<br>
>> -}<br>
>> -<br>
>> -attributes #0 = { nounwind "target-cpu"="hexagonv55" }<br>
>> -<br>
>> -!0 = !{!1, !1, i64 0}<br>
>> -!1 = !{!"short", !2}<br>
>> -!2 = !{!"omnipotent char", !3}<br>
>> -!3 = !{!"Simple C/C++ TBAA"}<br>
>> -!4 = !{!2, !2, i64 0}<br>
>><br>
>> Removed: llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-memrefs-epilog1.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll?rev=344141&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/swp-memrefs-<wbr>epilog1.ll?rev=344141&view=<wbr>auto</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-memrefs-epilog1.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-memrefs-epilog1.ll (removed)<br>
>> @@ -1,90 +0,0 @@<br>
>> -; RUN: llc -march=hexagon -enable-pipeliner < %s | FileCheck %s<br>
>> -<br>
>> -; Test that a store and load, that alias, are not put in the same <br>
>> packet. The<br>
>> -; pipeliner altered the size of the memrefs for these instructions, <br>
>> which<br>
>> -; resulted in no order dependence between the instructions in the <br>
>> DAG. No order<br>
>> -; dependence was added since the size was set to UINT_MAX, but there <br>
>> is a<br>
>> -; computation using the size that overflowed.<br>
>> -<br>
>> -; CHECK: endloop0<br>
>> -; CHECK: memh([[REG:r([0-9]+)]]+#0) =<br>
>> -; CHECK: = memh([[REG]]++#2)<br>
>> -<br>
>> -; Function Attrs: nounwind<br>
>> -define signext i16 @f0(i16* nocapture readonly %a0, i16* nocapture <br>
>> readonly %a1) local_unnamed_addr #0 {<br>
>> -b0:<br>
>> - %v0 = alloca [40 x i16], align 8<br>
>> - %v1 = bitcast [40 x i16]* %v0 to i8*<br>
>> - call void @llvm.lifetime.start.p0i8(i64 80, i8* nonnull %v1) #2<br>
>> - %v2 = getelementptr inbounds [40 x i16], [40 x i16]* %v0, i32 0, i32 0<br>
>> - br label %b1<br>
>> -<br>
>> -b1: <wbr> ; preds = %b1, %b0<br>
>> - %v3 = phi i16* [ %a1, %b0 ], [ %v24, %b1 ]<br>
>> - %v4 = phi i16* [ %v2, %b0 ], [ %v25, %b1 ]<br>
>> - %v5 = phi i32 [ 0, %b0 ], [ %v14, %b1 ]<br>
>> - %v6 = phi i32 [ 1, %b0 ], [ %v22, %b1 ]<br>
>> - %v7 = phi i32 [ 0, %b0 ], [ %v23, %b1 ]<br>
>> - %v8 = load i16, i16* %v3, align 2<br>
>> - %v9 = sext i16 %v8 to i32<br>
>> - %v10 = tail call i32 @llvm.hexagon.A2.aslh(i32 %v9)<br>
>> - %v11 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(<wbr>i32 %v10, i32 1)<br>
>> - %v12 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v11)<br>
>> - %v13 = trunc i32 %v12 to i16<br>
>> - store i16 %v13, i16* %v4, align 2<br>
>> - %v14 = add nuw nsw i32 %v5, 1<br>
>> - %v15 = icmp eq i32 %v14, 40<br>
>> - %v16 = getelementptr inbounds i16, i16* %a0, i32 %v7<br>
>> - %v17 = load i16, i16* %v16, align 2<br>
>> - %v18 = sext i16 %v17 to i32<br>
>> - %v19 = getelementptr inbounds [40 x i16], [40 x i16]* %v0, i32 0, <br>
>> i32 %v7<br>
>> - %v20 = load i16, i16* %v19, align 2<br>
>> - %v21 = sext i16 %v20 to i32<br>
>> - %v22 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.<wbr>ll.s1(i32 %v6, <br>
>> i32 %v18, i32 %v21)<br>
>> - %v23 = add nuw nsw i32 %v7, 1<br>
>> - %v24 = getelementptr i16, i16* %v3, i32 1<br>
>> - %v25 = getelementptr i16, i16* %v4, i32 1<br>
>> - br i1 %v15, label %b2, label %b1<br>
>> -<br>
>> -b2: <wbr> ; preds = %b1<br>
>> - %v26 = tail call signext i16 @f1(i32 %v22) #0<br>
>> - %v27 = sext i16 %v26 to i32<br>
>> - %v28 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(<wbr>i32 %v22, i32 %v27)<br>
>> - %v29 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v28)<br>
>> - %v30 = shl i32 %v29, 16<br>
>> - %v31 = ashr exact i32 %v30, 16<br>
>> - %v32 = icmp slt i32 %v30, 65536<br>
>> - br label %b3<br>
>> -<br>
>> -b3: <wbr> ; preds = %b2<br>
>> - call void @llvm.lifetime.end.p0i8(i64 80, i8* nonnull %v1) #2<br>
>> - ret i16 0<br>
>> -}<br>
>> -<br>
>> -; Function Attrs: argmemonly nounwind<br>
>> -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1<br>
>> -<br>
>> -; Function Attrs: nounwind readnone<br>
>> -declare i32 @llvm.hexagon.S2.asr.r.r.sat(<wbr>i32, i32) #2<br>
>> -<br>
>> -; Function Attrs: nounwind readnone<br>
>> -declare i32 @llvm.hexagon.A2.aslh(i32) #2<br>
>> -<br>
>> -; Function Attrs: nounwind readnone<br>
>> -declare i32 @llvm.hexagon.A2.asrh(i32) #2<br>
>> -<br>
>> -; Function Attrs: nounwind readnone<br>
>> -declare i32 @llvm.hexagon.M2.mpy.acc.sat.<wbr>ll.s1(i32, i32, i32) #2<br>
>> -<br>
>> -; Function Attrs: nounwind<br>
>> -declare signext i16 @f1(i32) local_unnamed_addr #0<br>
>> -<br>
>> -; Function Attrs: nounwind readnone<br>
>> -declare i32 @llvm.hexagon.S2.asl.r.r.sat(<wbr>i32, i32) #2<br>
>> -<br>
>> -; Function Attrs: argmemonly nounwind<br>
>> -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1<br>
>> -<br>
>> -attributes #0 = { nounwind }<br>
>> -attributes #1 = { argmemonly nounwind }<br>
>> -attributes #2 = { nounwind readnone }<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/Mips/<wbr>cconv/vector.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/cconv/vector.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/Mips/<wbr>cconv/vector.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/Mips/<wbr>cconv/vector.ll Wed Oct 10 07:15:52 2018<br>
>> @@ -2053,12 +2053,10 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2<br>
>> ; MIPS64R5-NEXT: sd $4, 24($sp)<br>
>> ; MIPS64R5-NEXT: ldi.b $w0, 0<br>
>> ; MIPS64R5-NEXT: lw $1, 20($sp)<br>
>> -; MIPS64R5-NEXT: lw $2, 16($sp)<br>
>> ; MIPS64R5-NEXT: move.v $w1, $w0<br>
>> -; MIPS64R5-NEXT: insert.d $w1[0], $2<br>
>> +; MIPS64R5-NEXT: insert.d $w1[0], $5<br>
>> ; MIPS64R5-NEXT: insert.d $w1[1], $1<br>
>> -; MIPS64R5-NEXT: lw $1, 24($sp)<br>
>> -; MIPS64R5-NEXT: insert.d $w0[0], $1<br>
>> +; MIPS64R5-NEXT: insert.d $w0[0], $4<br>
>> ; MIPS64R5-NEXT: lw $1, 28($sp)<br>
>> ; MIPS64R5-NEXT: insert.d $w0[1], $1<br>
>> ; MIPS64R5-NEXT: addv.d $w0, $w0, $w1<br>
>> @@ -3533,12 +3531,8 @@ define void @call_i8_2() {<br>
>> ; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 32<br>
>> ; MIPS32R5EB-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill<br>
>> ; MIPS32R5EB-NEXT: .cfi_offset 31, -4<br>
>> -; MIPS32R5EB-NEXT: addiu $1, $zero, 1543<br>
>> -; MIPS32R5EB-NEXT: sh $1, 20($sp)<br>
>> -; MIPS32R5EB-NEXT: addiu $1, $zero, 3080<br>
>> -; MIPS32R5EB-NEXT: sh $1, 24($sp)<br>
>> -; MIPS32R5EB-NEXT: lhu $4, 20($sp)<br>
>> -; MIPS32R5EB-NEXT: lhu $5, 24($sp)<br>
>> +; MIPS32R5EB-NEXT: addiu $4, $zero, 1543<br>
>> +; MIPS32R5EB-NEXT: addiu $5, $zero, 3080<br>
>> ; MIPS32R5EB-NEXT: jal i8_2<br>
>> ; MIPS32R5EB-NEXT: nop<br>
>> ; MIPS32R5EB-NEXT: sw $2, 16($sp)<br>
>> @@ -3645,12 +3639,8 @@ define void @call_i8_2() {<br>
>> ; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 32<br>
>> ; MIPS32R5EL-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill<br>
>> ; MIPS32R5EL-NEXT: .cfi_offset 31, -4<br>
>> -; MIPS32R5EL-NEXT: addiu $1, $zero, 1798<br>
>> -; MIPS32R5EL-NEXT: sh $1, 20($sp)<br>
>> -; MIPS32R5EL-NEXT: addiu $1, $zero, 2060<br>
>> -; MIPS32R5EL-NEXT: sh $1, 24($sp)<br>
>> -; MIPS32R5EL-NEXT: lhu $4, 20($sp)<br>
>> -; MIPS32R5EL-NEXT: lhu $5, 24($sp)<br>
>> +; MIPS32R5EL-NEXT: addiu $4, $zero, 1798<br>
>> +; MIPS32R5EL-NEXT: addiu $5, $zero, 2060<br>
>> ; MIPS32R5EL-NEXT: jal i8_2<br>
>> ; MIPS32R5EL-NEXT: nop<br>
>> ; MIPS32R5EL-NEXT: sw $2, 16($sp)<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/<wbr>jumptables.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/indirect-jump-<wbr>hazard/jumptables.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/<wbr>jumptables.ll <br>
>> (original)<br>
>> +++ llvm/trunk/test/CodeGen/Mips/<wbr>indirect-jump-hazard/<wbr>jumptables.ll <br>
>> Wed Oct 10 07:15:52 2018<br>
>> @@ -155,11 +155,10 @@ define i8* @_Z3fooi(i32 signext %Letter)<br>
>> ; MIPS64R2: # %bb.0: # %entry<br>
>> ; MIPS64R2-NEXT: daddiu $sp, $sp, -16<br>
>> ; MIPS64R2-NEXT: .cfi_def_cfa_offset 16<br>
>> -; MIPS64R2-NEXT: sw $4, 4($sp)<br>
>> -; MIPS64R2-NEXT: lwu $2, 4($sp)<br>
>> +; MIPS64R2-NEXT: dext $2, $4, 0, 32<br>
>> ; MIPS64R2-NEXT: sltiu $1, $2, 7<br>
>> ; MIPS64R2-NEXT: beqz $1, .LBB0_3<br>
>> -; MIPS64R2-NEXT: nop<br>
>> +; MIPS64R2-NEXT: sw $4, 4($sp)<br>
>> ; MIPS64R2-NEXT: .LBB0_1: # %entry<br>
>> ; MIPS64R2-NEXT: dsll $1, $2, 3<br>
>> ; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0)<br>
>> @@ -251,10 +250,10 @@ define i8* @_Z3fooi(i32 signext %Letter)<br>
>> ; MIPS64R6: # %bb.0: # %entry<br>
>> ; MIPS64R6-NEXT: daddiu $sp, $sp, -16<br>
>> ; MIPS64R6-NEXT: .cfi_def_cfa_offset 16<br>
>> -; MIPS64R6-NEXT: sw $4, 4($sp)<br>
>> -; MIPS64R6-NEXT: lwu $2, 4($sp)<br>
>> +; MIPS64R6-NEXT: dext $2, $4, 0, 32<br>
>> ; MIPS64R6-NEXT: sltiu $1, $2, 7<br>
>> -; MIPS64R6-NEXT: beqzc $1, .LBB0_3<br>
>> +; MIPS64R6-NEXT: beqz $1, .LBB0_3<br>
>> +; MIPS64R6-NEXT: sw $4, 4($sp)<br>
>> ; MIPS64R6-NEXT: .LBB0_1: # %entry<br>
>> ; MIPS64R6-NEXT: dsll $1, $2, 3<br>
>> ; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0)<br>
>> @@ -473,11 +472,10 @@ define i8* @_Z3fooi(i32 signext %Letter)<br>
>> ; PIC-MIPS64R2-NEXT: lui $1, %hi(%neg(%gp_rel(_Z3fooi)))<br>
>> ; PIC-MIPS64R2-NEXT: daddu $1, $1, $25<br>
>> ; PIC-MIPS64R2-NEXT: daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))<br>
>> -; PIC-MIPS64R2-NEXT: sw $4, 4($sp)<br>
>> -; PIC-MIPS64R2-NEXT: lwu $3, 4($sp)<br>
>> +; PIC-MIPS64R2-NEXT: dext $3, $4, 0, 32<br>
>> ; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7<br>
>> ; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_3<br>
>> -; PIC-MIPS64R2-NEXT: nop<br>
>> +; PIC-MIPS64R2-NEXT: sw $4, 4($sp)<br>
>> ; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry<br>
>> ; PIC-MIPS64R2-NEXT: dsll $1, $3, 3<br>
>> ; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2)<br>
>> @@ -537,10 +535,10 @@ define i8* @_Z3fooi(i32 signext %Letter)<br>
>> ; PIC-MIPS64R6-NEXT: lui $1, %hi(%neg(%gp_rel(_Z3fooi)))<br>
>> ; PIC-MIPS64R6-NEXT: daddu $1, $1, $25<br>
>> ; PIC-MIPS64R6-NEXT: daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))<br>
>> -; PIC-MIPS64R6-NEXT: sw $4, 4($sp)<br>
>> -; PIC-MIPS64R6-NEXT: lwu $3, 4($sp)<br>
>> +; PIC-MIPS64R6-NEXT: dext $3, $4, 0, 32<br>
>> ; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7<br>
>> -; PIC-MIPS64R6-NEXT: beqzc $1, .LBB0_3<br>
>> +; PIC-MIPS64R6-NEXT: beqz $1, .LBB0_3<br>
>> +; PIC-MIPS64R6-NEXT: sw $4, 4($sp)<br>
>> ; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry<br>
>> ; PIC-MIPS64R6-NEXT: dsll $1, $3, 3<br>
>> ; PIC-MIPS64R6-NEXT: ld $3, %got_page(.LJTI0_0)($2)<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/o32_cc_byval.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll Wed Oct 10 07:15:52 2018<br>
>> @@ -109,7 +109,8 @@ define void @f2(float %f, %struct.S1* no<br>
>> ; CHECK-NEXT: lw $1, 64($sp)<br>
>> ; CHECK-NEXT: lw $2, 68($sp)<br>
>> ; CHECK-NEXT: lh $3, 58($sp)<br>
>> -; CHECK-NEXT: lb $5, 56($sp)<br>
>> +; CHECK-NEXT: sll $5, $6, 24<br>
>> +; CHECK-NEXT: sra $5, $5, 24<br>
>> ; CHECK-NEXT: swc1 $f12, 36($sp)<br>
>> ; CHECK-NEXT: sw $5, 32($sp)<br>
>> ; CHECK-NEXT: sw $3, 28($sp)<br>
>> @@ -191,11 +192,12 @@ define void @f4(float %f, %struct.S3* no<br>
>> ; CHECK-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill<br>
>> ; CHECK-NEXT: addu $gp, $2, $25<br>
>> ; CHECK-NEXT: move $4, $7<br>
>> -; CHECK-NEXT: sw $5, 52($sp)<br>
>> ; CHECK-NEXT: sw $6, 56($sp)<br>
>> +; CHECK-NEXT: sw $5, 52($sp)<br>
>> ; CHECK-NEXT: sw $7, 60($sp)<br>
>> ; CHECK-NEXT: lw $1, 80($sp)<br>
>> -; CHECK-NEXT: lb $2, 52($sp)<br>
>> +; CHECK-NEXT: sll $2, $5, 24<br>
>> +; CHECK-NEXT: sra $2, $2, 24<br>
>> ; CHECK-NEXT: addiu $3, $zero, 4<br>
>> ; CHECK-NEXT: lui $5, 16576<br>
>> ; CHECK-NEXT: sw $5, 36($sp)<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/o32_cc_vararg.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll Wed Oct 10 07:15:52 <br>
>> 2018<br>
>> @@ -29,10 +29,10 @@ entry:<br>
>> ; CHECK-LABEL: va1:<br>
>> ; CHECK: addiu $sp, $sp, -16<br>
>> -; CHECK: sw $5, 20($sp)<br>
>> ; CHECK: sw $7, 28($sp)<br>
>> ; CHECK: sw $6, 24($sp)<br>
>> -; CHECK: lw $2, 20($sp)<br>
>> +; CHECK: sw $5, 20($sp)<br>
>> +; CHECK: move $2, $5<br>
>> }<br>
>> ; check whether the variable double argument will be accessed from <br>
>> the 8-byte<br>
>> @@ -83,9 +83,9 @@ entry:<br>
>> ; CHECK-LABEL: va3:<br>
>> ; CHECK: addiu $sp, $sp, -16<br>
>> -; CHECK: sw $6, 24($sp)<br>
>> ; CHECK: sw $7, 28($sp)<br>
>> -; CHECK: lw $2, 24($sp)<br>
>> +; CHECK: sw $6, 24($sp)<br>
>> +; CHECK: move $2, $6<br>
>> }<br>
>> ; double<br>
>> @@ -135,7 +135,7 @@ entry:<br>
>> ; CHECK-LABEL: va5:<br>
>> ; CHECK: addiu $sp, $sp, -24<br>
>> ; CHECK: sw $7, 36($sp)<br>
>> -; CHECK: lw $2, 36($sp)<br>
>> +; CHECK: move $2, $7<br>
>> }<br>
>> ; double<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/addi-offset-fold.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/addi-offset-<wbr>fold.ll?rev=344142&r1=344141&<wbr>r2=344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>PowerPC/addi-offset-fold.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>PowerPC/addi-offset-fold.ll Wed Oct 10 <br>
>> 07:15:52 2018<br>
>> @@ -24,12 +24,11 @@ entry:<br>
>> ret i32 %bf.cast<br>
>> ; CHECK-LABEL: @foo<br>
>> -; FIXME: We don't need to do these stores/loads at all.<br>
>> +; FIXME: We don't need to do these stores at all.<br>
>> ; CHECK-DAG: std 3, -24(1)<br>
>> ; CHECK-DAG: stb 4, -16(1)<br>
>> -; CHECK-DAG: lbz [[REG1:[0-9]+]], -16(1)<br>
>> +; CHECK-DAG: sldi [[REG3:[0-9]+]], 4, 32<br>
>> ; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)<br>
>> -; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG1]], 32<br>
>> ; CHECK-DAG: or [[REG4:[0-9]+]], [[REG2]], [[REG3]]<br>
>> ; CHECK: rldicl 3, [[REG4]], 33, 57<br>
>> ; CHECK: blr<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/<wbr>SystemZ/store_nonbytesized_<wbr>vecs.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/SystemZ/store_<wbr>nonbytesized_vecs.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/<wbr>SystemZ/store_nonbytesized_<wbr>vecs.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/<wbr>SystemZ/store_nonbytesized_<wbr>vecs.ll Wed Oct <br>
>> 10 07:15:52 2018<br>
>> @@ -60,8 +60,7 @@ define i16 @fun1(<16 x i1> %src)<br>
>> ; CHECK-NEXT: rosbg %r0, %r1, 62, 62, 1<br>
>> ; CHECK-NEXT: vlgvb %r1, %v24, 15<br>
>> ; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 0<br>
>> -; CHECK-NEXT: sth %r0, 160(%r15)<br>
>> -; CHECK-NEXT: lh %r2, 160(%r15)<br>
>> +; CHECK-NEXT: llhr %r2, %r0<br>
>> ; CHECK-NEXT: aghi %r15, 168<br>
>> ; CHECK-NEXT: br %r14<br>
>> {<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/i386-shrink-<wbr>wrapping.ll?rev=344142&r1=<wbr>344141&r2=344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll Wed Oct 10 <br>
>> 07:15:52 2018<br>
>> @@ -56,7 +56,7 @@ target triple = "i386-apple-macosx10.5"<br>
>> ;<br>
>> ; CHECK-NEXT: L_e$non_lazy_ptr, [[E:%[a-z]+]]<br>
>> ; CHECK-NEXT: movb %dl, ([[E]])<br>
>> -; CHECK-NEXT: movsbl ([[E]]), [[CONV:%[a-z]+]]<br>
>> +; CHECK-NEXT: movzbl %dl, [[CONV:%[a-z]+]]<br>
>> ; CHECK-NEXT: movl $6, [[CONV:%[a-z]+]]<br>
>> ; The eflags is used in the next instruction.<br>
>> ; If that instruction disappear, we are not exercising the bug<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/pr32108.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll Wed Oct 10 07:15:52 2018<br>
>> @@ -4,7 +4,6 @@<br>
>> define void @pr32108() {<br>
>> ; CHECK-LABEL: pr32108:<br>
>> ; CHECK: # %bb.0: # %BB<br>
>> -; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)<br>
>> ; CHECK-NEXT: .p2align 4, 0x90<br>
>> ; CHECK-NEXT: .LBB0_1: # %CF244<br>
>> ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/X86/<wbr>pr38533.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/pr38533.ll?rev=<wbr>344142&r1=344141&r2=344142&<wbr>view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/X86/<wbr>pr38533.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/X86/<wbr>pr38533.ll Wed Oct 10 07:15:52 2018<br>
>> @@ -19,8 +19,6 @@ define void @pr38533_2(half %x) {<br>
>> ; SSE-NEXT: pushq %rax<br>
>> ; SSE-NEXT: .cfi_def_cfa_offset 16<br>
>> ; SSE-NEXT: callq __gnu_f2h_ieee<br>
>> -; SSE-NEXT: movw %ax, {{[0-9]+}}(%rsp)<br>
>> -; SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax<br>
>> ; SSE-NEXT: movw %ax, (%rax)<br>
>> ; SSE-NEXT: popq %rax<br>
>> ; SSE-NEXT: .cfi_def_cfa_offset 8<br>
>> @@ -30,8 +28,6 @@ define void @pr38533_2(half %x) {<br>
>> ; AVX512: # %bb.0:<br>
>> ; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0<br>
>> ; AVX512-NEXT: vmovd %xmm0, %eax<br>
>> -; AVX512-NEXT: movw %ax, -{{[0-9]+}}(%rsp)<br>
>> -; AVX512-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax<br>
>> ; AVX512-NEXT: movw %ax, (%rax)<br>
>> ; AVX512-NEXT: retq<br>
>> %a = bitcast half %x to <4 x i4><br>
>> @@ -46,8 +42,6 @@ define void @pr38533_3(half %x) {<br>
>> ; SSE-NEXT: pushq %rax<br>
>> ; SSE-NEXT: .cfi_def_cfa_offset 16<br>
>> ; SSE-NEXT: callq __gnu_f2h_ieee<br>
>> -; SSE-NEXT: movw %ax, (%rsp)<br>
>> -; SSE-NEXT: movzwl (%rsp), %eax<br>
>> ; SSE-NEXT: movw %ax, (%rax)<br>
>> ; SSE-NEXT: popq %rax<br>
>> ; SSE-NEXT: .cfi_def_cfa_offset 8<br>
>><br>
>> Modified: llvm/trunk/test/CodeGen/X86/<wbr>win64_vararg.ll<br>
>> URL: <br>
>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_vararg.ll?rev=344142&r1=344141&r2=344142&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/win64_vararg.ll?<wbr>rev=344142&r1=344141&r2=<wbr>344142&view=diff</a> <br>
>><br>
>> ==============================<wbr>==============================<wbr>================== <br>
>><br>
>> --- llvm/trunk/test/CodeGen/X86/<wbr>win64_vararg.ll (original)<br>
>> +++ llvm/trunk/test/CodeGen/X86/<wbr>win64_vararg.ll Wed Oct 10 07:15:52 2018<br>
>> @@ -124,7 +124,8 @@ entry:<br>
>> ; CHECK: movq %rcx, %rax<br>
>> ; CHECK-DAG: movq %r9, 40(%rsp)<br>
>> ; CHECK-DAG: movq %r8, 32(%rsp)<br>
>> -; CHECK: movl 32(%rsp), %[[tmp:[^ ]*]]<br>
>> -; CHECK: movl %[[tmp]], (%rax)<br>
>> +; CHECK-DAG: leaq 36(%rsp), %[[sret:[^ ]*]]<br>
>> +; CHECK-DAG: movl %r8d, (%rax)<br>
>> +; CHECK-DAG: movq %[[sret]], (%rsp)<br>
>> ; CHECK: popq<br>
>> ; CHECK: retq<br>
>><br>
>><br>
>> ______________________________<wbr>_________________<br>
>> llvm-commits mailing list<br>
>> <a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
>> <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><br>
>><br>
</div></div></blockquote></div><br></div>