<div dir="ltr"><div>Hi Guillaume</div><div><br>
</div><div>+unsigned Variable::getIndex() const {</div><div>
+ assert(Index >= 0); <br></div><div><br></div>Index is an unsigned...<div> That comparison is trivially true, so it should be removed. clang/gcc generate a warning when assertions are enabled.<br></div><div><br></div><div>
<div>More in general: we should avoid asserts with no string message.</div><div><br></div>
</div><div>-Andrea<br></div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Oct 9, 2018 at 10:00 AM Guillaume Chatelet via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: gchatelet<br>
Date: Tue Oct 9 01:59:10 2018<br>
New Revision: 344028<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=344028&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=344028&view=rev</a><br>
Log:<br>
[llvm-exegesis][NFC] Use accessors for Operand.<br>
<br>
Summary:<br>
This moves checking logic into the accessors and makes the structure smaller.<br>
It will also help when/if Operand are generated from the TD files.<br>
<br>
Subscribers: tschuett, courbet, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D52982" rel="noreferrer" target="_blank">https://reviews.llvm.org/D52982</a><br>
<br>
Modified:<br>
llvm/trunk/tools/llvm-exegesis/lib/CodeTemplate.cpp<br>
llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp<br>
llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h<br>
llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp<br>
llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp<br>
llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp<br>
<br>
Modified: llvm/trunk/tools/llvm-exegesis/lib/CodeTemplate.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/CodeTemplate.cpp?rev=344028&r1=344027&r2=344028&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/CodeTemplate.cpp?rev=344028&r1=344027&r2=344028&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-exegesis/lib/CodeTemplate.cpp (original)<br>
+++ llvm/trunk/tools/llvm-exegesis/lib/CodeTemplate.cpp Tue Oct 9 01:59:10 2018<br>
@@ -33,32 +33,26 @@ unsigned InstructionTemplate::getOpcode(<br>
}<br>
<br>
llvm::MCOperand &InstructionTemplate::getValueFor(const Variable &Var) {<br>
- return VariableValues[Var.Index];<br>
+ return VariableValues[Var.getIndex()];<br>
}<br>
<br>
const llvm::MCOperand &<br>
InstructionTemplate::getValueFor(const Variable &Var) const {<br>
- return VariableValues[Var.Index];<br>
+ return VariableValues[Var.getIndex()];<br>
}<br>
<br>
llvm::MCOperand &InstructionTemplate::getValueFor(const Operand &Op) {<br>
- assert(Op.VariableIndex >= 0);<br>
- return getValueFor(Instr.Variables[Op.VariableIndex]);<br>
+ return getValueFor(Instr.Variables[Op.getVariableIndex()]);<br>
}<br>
<br>
const llvm::MCOperand &<br>
InstructionTemplate::getValueFor(const Operand &Op) const {<br>
- assert(Op.VariableIndex >= 0);<br>
- return getValueFor(Instr.Variables[Op.VariableIndex]);<br>
+ return getValueFor(Instr.Variables[Op.getVariableIndex()]);<br>
}<br>
<br>
bool InstructionTemplate::hasImmediateVariables() const {<br>
return llvm::any_of(Instr.Variables, [this](const Variable &Var) {<br>
- assert(!Var.TiedOperands.empty());<br>
- const unsigned OpIndex = Var.TiedOperands[0];<br>
- const Operand &Op = Instr.Operands[OpIndex];<br>
- assert(Op.Info);<br>
- return Op.Info->OperandType == llvm::MCOI::OPERAND_IMMEDIATE;<br>
+ return Instr.getPrimaryOperand(Var).isImmediate();<br>
});<br>
}<br>
<br>
@@ -66,7 +60,7 @@ llvm::MCInst InstructionTemplate::build(<br>
llvm::MCInst Result;<br>
Result.setOpcode(Instr.Description->Opcode);<br>
for (const auto &Op : Instr.Operands)<br>
- if (Op.IsExplicit)<br>
+ if (Op.isExplicit())<br>
Result.addOperand(getValueFor(Op));<br>
return Result;<br>
}<br>
<br>
Modified: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp?rev=344028&r1=344027&r2=344028&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp?rev=344028&r1=344027&r2=344028&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp (original)<br>
+++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp Tue Oct 9 01:59:10 2018<br>
@@ -17,6 +17,70 @@<br>
<br>
namespace exegesis {<br>
<br>
+unsigned Variable::getIndex() const {<br>
+ assert(Index >= 0);<br>
+ return Index;<br>
+}<br>
+unsigned Variable::getPrimaryOperandIndex() const {<br>
+ assert(!TiedOperands.empty());<br>
+ return TiedOperands[0];<br>
+}<br>
+<br>
+bool Variable::hasTiedOperands() const { return TiedOperands.size() > 1; }<br>
+<br>
+bool Operand::getIndex() const { return Index; }<br>
+<br>
+bool Operand::isExplicit() const { return Info; }<br>
+<br>
+bool Operand::isImplicit() const { return !Info; }<br>
+<br>
+bool Operand::isImplicitReg() const { return ImplicitReg; }<br>
+<br>
+bool Operand::isDef() const { return IsDef; }<br>
+<br>
+bool Operand::isUse() const { return !IsDef; }<br>
+<br>
+bool Operand::isReg() const { return Tracker; }<br>
+<br>
+bool Operand::isTied() const { return TiedToIndex >= 0; }<br>
+<br>
+bool Operand::isVariable() const { return VariableIndex >= 0; }<br>
+<br>
+bool Operand::isMemory() const {<br>
+ return isExplicit() &&<br>
+ getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_MEMORY;<br>
+}<br>
+<br>
+bool Operand::isImmediate() const {<br>
+ return isExplicit() &&<br>
+ getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_IMMEDIATE;<br>
+}<br>
+<br>
+int Operand::getTiedToIndex() const {<br>
+ assert(isTied());<br>
+ return TiedToIndex;<br>
+}<br>
+<br>
+int Operand::getVariableIndex() const {<br>
+ assert(isVariable());<br>
+ return VariableIndex;<br>
+}<br>
+<br>
+unsigned Operand::getImplicitReg() const {<br>
+ assert(ImplicitReg);<br>
+ return *ImplicitReg;<br>
+}<br>
+<br>
+const RegisterAliasingTracker &Operand::getRegisterAliasing() const {<br>
+ assert(Tracker);<br>
+ return *Tracker;<br>
+}<br>
+<br>
+const llvm::MCOperandInfo &Operand::getExplicitOperandInfo() const {<br>
+ assert(Info);<br>
+ return *Info;<br>
+}<br>
+<br>
Instruction::Instruction(const llvm::MCInstrDesc &MCInstrDesc,<br>
const RegisterAliasingTrackerCache &RATC)<br>
: Description(&MCInstrDesc) {<br>
@@ -26,8 +90,6 @@ Instruction::Instruction(const llvm::MCI<br>
Operand Operand;<br>
Operand.Index = OpIndex;<br>
Operand.IsDef = (OpIndex < MCInstrDesc.getNumDefs());<br>
- Operand.IsMem = OpInfo.OperandType == llvm::MCOI::OPERAND_MEMORY;<br>
- Operand.IsExplicit = true;<br>
// TODO(gchatelet): Handle isLookupPtrRegClass.<br>
if (OpInfo.RegClass >= 0)<br>
Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);<br>
@@ -41,7 +103,6 @@ Instruction::Instruction(const llvm::MCI<br>
Operand Operand;<br>
Operand.Index = OpIndex;<br>
Operand.IsDef = true;<br>
- Operand.IsExplicit = false;<br>
Operand.Tracker = &RATC.getRegister(*MCPhysReg);<br>
Operand.ImplicitReg = MCPhysReg;<br>
Operands.push_back(Operand);<br>
@@ -51,7 +112,6 @@ Instruction::Instruction(const llvm::MCI<br>
Operand Operand;<br>
Operand.Index = OpIndex;<br>
Operand.IsDef = false;<br>
- Operand.IsExplicit = false;<br>
Operand.Tracker = &RATC.getRegister(*MCPhysReg);<br>
Operand.ImplicitReg = MCPhysReg;<br>
Operands.push_back(Operand);<br>
@@ -59,7 +119,7 @@ Instruction::Instruction(const llvm::MCI<br>
// Assigning Variables to non tied explicit operands.<br>
Variables.reserve(Operands.size()); // Variables.size() <= Operands.size()<br>
for (auto &Op : Operands)<br>
- if (Op.IsExplicit && Op.TiedToIndex < 0) {<br>
+ if (Op.isExplicit() && !Op.isTied()) {<br>
const size_t VariableIndex = Variables.size();<br>
Op.VariableIndex = VariableIndex;<br>
Variables.emplace_back();<br>
@@ -67,26 +127,55 @@ Instruction::Instruction(const llvm::MCI<br>
}<br>
// Assigning Variables to tied operands.<br>
for (auto &Op : Operands)<br>
- if (Op.TiedToIndex >= 0)<br>
- Op.VariableIndex = Operands[Op.TiedToIndex].VariableIndex;<br>
+ if (Op.isTied())<br>
+ Op.VariableIndex = Operands[Op.getTiedToIndex()].getVariableIndex();<br>
// Assigning Operands to Variables.<br>
for (auto &Op : Operands)<br>
- if (Op.VariableIndex >= 0)<br>
- Variables[Op.VariableIndex].TiedOperands.push_back(Op.Index);<br>
+ if (Op.isVariable())<br>
+ Variables[Op.getVariableIndex()].TiedOperands.push_back(Op.getIndex());<br>
// Processing Aliasing.<br>
- DefRegisters = RATC.emptyRegisters();<br>
- UseRegisters = RATC.emptyRegisters();<br>
+ ImplDefRegs = RATC.emptyRegisters();<br>
+ ImplUseRegs = RATC.emptyRegisters();<br>
+ AllDefRegs = RATC.emptyRegisters();<br>
+ AllUseRegs = RATC.emptyRegisters();<br>
for (const auto &Op : Operands) {<br>
- if (Op.Tracker) {<br>
- auto &Registers = Op.IsDef ? DefRegisters : UseRegisters;<br>
- Registers |= Op.Tracker->aliasedBits();<br>
+ if (Op.isReg()) {<br>
+ const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();<br>
+ if (Op.isDef())<br>
+ AllDefRegs |= AliasingBits;<br>
+ if (Op.isUse())<br>
+ AllUseRegs |= AliasingBits;<br>
+ if (Op.isDef() && Op.isImplicit())<br>
+ ImplDefRegs |= AliasingBits;<br>
+ if (Op.isUse() && Op.isImplicit())<br>
+ ImplUseRegs |= AliasingBits;<br>
}<br>
}<br>
}<br>
<br>
+const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {<br>
+ const auto PrimaryOperandIndex = Var.getPrimaryOperandIndex();<br>
+ assert(PrimaryOperandIndex < Operands.size());<br>
+ return Operands[PrimaryOperandIndex];<br>
+}<br>
+<br>
bool Instruction::hasMemoryOperands() const {<br>
- return std::any_of(Operands.begin(), Operands.end(),<br>
- [](const Operand &Op) { return Op.IsMem; });<br>
+ return std::any_of(Operands.begin(), Operands.end(), [](const Operand &Op) {<br>
+ return Op.isReg() && Op.isExplicit() && Op.isMemory();<br>
+ });<br>
+}<br>
+<br>
+bool Instruction::hasAliasingImplicitRegisters() const {<br>
+ return ImplDefRegs.anyCommon(ImplUseRegs);<br>
+}<br>
+<br>
+bool Instruction::hasTiedRegisters() const {<br>
+ return llvm::any_of(<br>
+ Variables, [this](const Variable &Var) { return Var.hasTiedOperands(); });<br>
+}<br>
+<br>
+bool Instruction::hasAliasingRegisters() const {<br>
+ return AllDefRegs.anyCommon(AllUseRegs);<br>
}<br>
<br>
bool RegisterOperandAssignment::<br>
@@ -103,8 +192,8 @@ static void addOperandIfAlias(<br>
const llvm::MCPhysReg Reg, bool SelectDef, llvm::ArrayRef<Operand> Operands,<br>
llvm::SmallVectorImpl<RegisterOperandAssignment> &OperandValues) {<br>
for (const auto &Op : Operands) {<br>
- if (Op.Tracker && Op.IsDef == SelectDef) {<br>
- const int SourceReg = Op.Tracker->getOrigin(Reg);<br>
+ if (Op.isReg() && Op.isDef() == SelectDef) {<br>
+ const int SourceReg = Op.getRegisterAliasing().getOrigin(Reg);<br>
if (SourceReg >= 0)<br>
OperandValues.emplace_back(&Op, SourceReg);<br>
}<br>
@@ -113,7 +202,7 @@ static void addOperandIfAlias(<br>
<br>
bool AliasingRegisterOperands::hasImplicitAliasing() const {<br>
const auto HasImplicit = [](const RegisterOperandAssignment &ROV) {<br>
- return !ROV.Op->IsExplicit;<br>
+ return ROV.Op->isImplicit();<br>
};<br>
return llvm::any_of(Defs, HasImplicit) && llvm::any_of(Uses, HasImplicit);<br>
}<br>
@@ -129,9 +218,9 @@ bool AliasingConfigurations::hasImplicit<br>
AliasingConfigurations::AliasingConfigurations(<br>
const Instruction &DefInstruction, const Instruction &UseInstruction)<br>
: DefInstruction(DefInstruction), UseInstruction(UseInstruction) {<br>
- if (UseInstruction.UseRegisters.anyCommon(DefInstruction.DefRegisters)) {<br>
- auto CommonRegisters = UseInstruction.UseRegisters;<br>
- CommonRegisters &= DefInstruction.DefRegisters;<br>
+ if (UseInstruction.AllUseRegs.anyCommon(DefInstruction.AllDefRegs)) {<br>
+ auto CommonRegisters = UseInstruction.AllUseRegs;<br>
+ CommonRegisters &= DefInstruction.AllDefRegs;<br>
for (const llvm::MCPhysReg Reg : CommonRegisters.set_bits()) {<br>
AliasingRegisterOperands ARO;<br>
addOperandIfAlias(Reg, true, DefInstruction.Operands, ARO.Defs);<br>
<br>
Modified: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h?rev=344028&r1=344027&r2=344028&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h?rev=344028&r1=344027&r2=344028&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h (original)<br>
+++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h Tue Oct 9 01:59:10 2018<br>
@@ -30,11 +30,18 @@<br>
<br>
namespace exegesis {<br>
<br>
-struct Operand; // forward declaration.<br>
-<br>
// A variable represents the value associated to an Operand or a set of Operands<br>
// if they are tied together.<br>
struct Variable {<br>
+ // Returns the index of this Variable inside Instruction's Variable.<br>
+ unsigned getIndex() const;<br>
+<br>
+ // Returns the index of the Operand linked to this Variable.<br>
+ unsigned getPrimaryOperandIndex() const;<br>
+<br>
+ // Returns whether this Variable has more than one Operand linked to it.<br>
+ bool hasTiedOperands() const;<br>
+<br>
// The indices of the operands tied to this Variable.<br>
llvm::SmallVector<unsigned, 2> TiedOperands;<br>
llvm::MCOperand AssignedValue;<br>
@@ -45,7 +52,6 @@ struct Variable {<br>
<br>
// MCOperandInfo can only represents Explicit operands. This object gives a<br>
// uniform view of Implicit and Explicit Operands.<br>
-//<br>
// - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.<br>
// - Tracker: is set for Register Operands and is used to keep track of possible<br>
// registers and the registers reachable from them (aliasing registers).<br>
@@ -56,10 +62,26 @@ struct Variable {<br>
// - VariableIndex: the index of the Variable holding the value for this Operand<br>
// or -1 if this operand is implicit.<br>
struct Operand {<br>
+ bool getIndex() const;<br>
+ bool isExplicit() const;<br>
+ bool isImplicit() const;<br>
+ bool isImplicitReg() const;<br>
+ bool isDef() const;<br>
+ bool isUse() const;<br>
+ bool isReg() const;<br>
+ bool isTied() const;<br>
+ bool isVariable() const;<br>
+ bool isMemory() const;<br>
+ bool isImmediate() const;<br>
+ int getTiedToIndex() const;<br>
+ int getVariableIndex() const;<br>
+ unsigned getImplicitReg() const;<br>
+ const RegisterAliasingTracker &getRegisterAliasing() const;<br>
+ const llvm::MCOperandInfo &getExplicitOperandInfo() const;<br>
+<br>
+ // Please use the accessors above and not the following fields.<br>
unsigned Index = 0;<br>
bool IsDef = false;<br>
- bool IsMem = false;<br>
- bool IsExplicit = false;<br>
const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.<br>
const llvm::MCOperandInfo *Info = nullptr; // Set for Explicit Op.<br>
int TiedToIndex = -1; // Set for Reg&Explicit Op.<br>
@@ -73,13 +95,36 @@ struct Instruction {<br>
Instruction(const llvm::MCInstrDesc &MCInstrDesc,<br>
const RegisterAliasingTrackerCache &ATC);<br>
<br>
+ // Returns the Operand linked to this Variable.<br>
+ // In case the Variable is tied, the primary (i.e. Def) Operand is returned.<br>
+ const Operand &getPrimaryOperand(const Variable &Var) const;<br>
+<br>
+ // Returns whether this instruction has Memory Operands.<br>
+ // Repeating this instruction executes sequentially with an instruction that<br>
+ // reads or write the same memory region.<br>
bool hasMemoryOperands() const;<br>
<br>
+ // Whether this instruction is self aliasing through its implicit registers.<br>
+ // Repeating this instruction is guaranteed to executes sequentially.<br>
+ bool hasAliasingImplicitRegisters() const;<br>
+<br>
+ // Whether this instruction is self aliasing through its tied registers.<br>
+ // Repeating this instruction is guaranteed to executes sequentially.<br>
+ bool hasTiedRegisters() const;<br>
+<br>
+ // Whether this instruction is self aliasing through some registers.<br>
+ // Repeating this instruction may execute sequentially by picking aliasing<br>
+ // Use and Def registers. It may also execute in parallel by picking non<br>
+ // aliasing Use and Def registers.<br>
+ bool hasAliasingRegisters() const;<br>
+<br>
const llvm::MCInstrDesc *Description; // Never nullptr.<br>
llvm::SmallVector<Operand, 8> Operands;<br>
llvm::SmallVector<Variable, 4> Variables;<br>
- llvm::BitVector DefRegisters; // The union of the aliased def registers.<br>
- llvm::BitVector UseRegisters; // The union of the aliased use registers.<br>
+ llvm::BitVector ImplDefRegs; // The set of aliased implicit def registers.<br>
+ llvm::BitVector ImplUseRegs; // The set of aliased implicit use registers.<br>
+ llvm::BitVector AllDefRegs; // The set of all aliased def registers.<br>
+ llvm::BitVector AllUseRegs; // The set of all aliased use registers.<br>
};<br>
<br>
// Represents the assignment of a Register to an Operand.<br>
<br>
Modified: llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp?rev=344028&r1=344027&r2=344028&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp?rev=344028&r1=344027&r2=344028&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp (original)<br>
+++ llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp Tue Oct 9 01:59:10 2018<br>
@@ -70,17 +70,17 @@ std::vector<RegisterValue> SnippetGenera<br>
// Returns the register that this Operand sets or uses, or 0 if this is not<br>
// a register.<br>
const auto GetOpReg = [&IT](const Operand &Op) -> unsigned {<br>
- if (Op.IsMem)<br>
+ if (Op.isMemory())<br>
return 0;<br>
- if (Op.ImplicitReg)<br>
- return *Op.ImplicitReg;<br>
- if (Op.IsExplicit && IT.getValueFor(Op).isReg())<br>
+ if (Op.isImplicitReg())<br>
+ return Op.getImplicitReg();<br>
+ if (Op.isExplicit() && IT.getValueFor(Op).isReg())<br>
return IT.getValueFor(Op).getReg();<br>
return 0;<br>
};<br>
// Collect used registers that have never been def'ed.<br>
for (const Operand &Op : IT.Instr.Operands) {<br>
- if (!Op.IsDef) {<br>
+ if (Op.isUse()) {<br>
const unsigned Reg = GetOpReg(Op);<br>
if (Reg > 0 && !DefinedRegs.test(Reg)) {<br>
RIV.push_back(RegisterValue{Reg, llvm::APInt()});<br>
@@ -90,7 +90,7 @@ std::vector<RegisterValue> SnippetGenera<br>
}<br>
// Mark defs as having been def'ed.<br>
for (const Operand &Op : IT.Instr.Operands) {<br>
- if (Op.IsDef) {<br>
+ if (Op.isDef()) {<br>
const unsigned Reg = GetOpReg(Op);<br>
if (Reg > 0)<br>
DefinedRegs.set(Reg);<br>
@@ -149,18 +149,15 @@ static auto randomElement(const C &Conta<br>
static void randomize(const Instruction &Instr, const Variable &Var,<br>
llvm::MCOperand &AssignedValue,<br>
const llvm::BitVector &ForbiddenRegs) {<br>
- assert(!Var.TiedOperands.empty());<br>
- const Operand &Op = Instr.Operands[Var.TiedOperands.front()];<br>
- assert(Op.Info != nullptr);<br>
- const auto &OpInfo = *Op.Info;<br>
- switch (OpInfo.OperandType) {<br>
+ const Operand &Op = Instr.getPrimaryOperand(Var);<br>
+ switch (Op.getExplicitOperandInfo().OperandType) {<br>
case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:<br>
// FIXME: explore immediate values too.<br>
AssignedValue = llvm::MCOperand::createImm(1);<br>
break;<br>
case llvm::MCOI::OperandType::OPERAND_REGISTER: {<br>
- assert(Op.Tracker);<br>
- auto AllowedRegs = Op.Tracker->sourceBits();<br>
+ assert(Op.isReg());<br>
+ auto AllowedRegs = Op.getRegisterAliasing().sourceBits();<br>
assert(AllowedRegs.size() == ForbiddenRegs.size());<br>
for (auto I : ForbiddenRegs.set_bits())<br>
AllowedRegs.reset(I);<br>
@@ -175,7 +172,7 @@ static void randomize(const Instruction<br>
static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,<br>
InstructionTemplate &IB) {<br>
assert(ROV.Op);<br>
- if (ROV.Op->IsExplicit) {<br>
+ if (ROV.Op->isExplicit()) {<br>
auto &AssignedValue = IB.getValueFor(*ROV.Op);<br>
if (AssignedValue.isValid()) {<br>
assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);<br>
@@ -183,8 +180,8 @@ static void setRegisterOperandValue(cons<br>
}<br>
AssignedValue = llvm::MCOperand::createReg(ROV.Reg);<br>
} else {<br>
- assert(ROV.Op->ImplicitReg != nullptr);<br>
- assert(ROV.Reg == *ROV.Op->ImplicitReg);<br>
+ assert(ROV.Op->isImplicitReg());<br>
+ assert(ROV.Reg == ROV.Op->getImplicitReg());<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp?rev=344028&r1=344027&r2=344028&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp?rev=344028&r1=344027&r2=344028&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp (original)<br>
+++ llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp Tue Oct 9 01:59:10 2018<br>
@@ -93,25 +93,11 @@ UopsSnippetGenerator::isInfeasible(const<br>
return llvm::Error::success();<br>
}<br>
<br>
-// Returns whether this Variable ties Use and Def operands together.<br>
-static bool hasTiedOperands(const Instruction &Instr, const Variable &Var) {<br>
- bool HasUse = false;<br>
- bool HasDef = false;<br>
- for (const unsigned OpIndex : Var.TiedOperands) {<br>
- const Operand &Op = Instr.Operands[OpIndex];<br>
- if (Op.IsDef)<br>
- HasDef = true;<br>
- else<br>
- HasUse = true;<br>
- }<br>
- return HasUse && HasDef;<br>
-}<br>
-<br>
static llvm::SmallVector<const Variable *, 8><br>
-getTiedVariables(const Instruction &Instr) {<br>
+getVariablesWithTiedOperands(const Instruction &Instr) {<br>
llvm::SmallVector<const Variable *, 8> Result;<br>
for (const auto &Var : Instr.Variables)<br>
- if (hasTiedOperands(Instr, Var))<br>
+ if (Var.hasTiedOperands())<br>
Result.push_back(&Var);<br>
return Result;<br>
}<br>
@@ -170,8 +156,8 @@ UopsSnippetGenerator::generateCodeTempla<br>
// If the instruction implicitly writes to ScratchSpacePointerInReg , abort.<br>
// FIXME: We could make a copy of the scratch register.<br>
for (const auto &Op : Instr.Operands) {<br>
- if (Op.IsDef && Op.ImplicitReg &&<br>
- ScratchSpaceAliasedRegs->test(*Op.ImplicitReg))<br>
+ if (Op.isDef() && Op.isImplicitReg() &&<br>
+ ScratchSpaceAliasedRegs->test(Op.getImplicitReg()))<br>
return llvm::make_error<BenchmarkFailure>(<br>
"Infeasible : memory instruction uses scratch memory register");<br>
}<br>
@@ -191,7 +177,7 @@ UopsSnippetGenerator::generateCodeTempla<br>
instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);<br>
return std::move(CT);<br>
}<br>
- const auto TiedVariables = getTiedVariables(Instr);<br>
+ const auto TiedVariables = getVariablesWithTiedOperands(Instr);<br>
if (!TiedVariables.empty()) {<br>
if (TiedVariables.size() > 1)<br>
return llvm::make_error<llvm::StringError>(<br>
@@ -199,11 +185,11 @@ UopsSnippetGenerator::generateCodeTempla<br>
llvm::inconvertibleErrorCode());<br>
const Variable *Var = TiedVariables.front();<br>
assert(Var);<br>
- assert(!Var->TiedOperands.empty());<br>
- const Operand &Op = Instr.Operands[Var->TiedOperands.front()];<br>
- assert(Op.Tracker);<br>
+ const Operand &Op = Instr.getPrimaryOperand(*Var);<br>
+ assert(Op.isReg());<br>
CT.Info = "instruction has tied variables using static renaming.";<br>
- for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {<br>
+ for (const llvm::MCPhysReg Reg :<br>
+ Op.getRegisterAliasing().sourceBits().set_bits()) {<br>
if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg))<br>
continue; // Do not use the scratch memory address register.<br>
InstructionTemplate TmpIT = IT;<br>
@@ -216,8 +202,8 @@ UopsSnippetGenerator::generateCodeTempla<br>
// No tied variables, we pick random values for defs.<br>
llvm::BitVector Defs(State.getRegInfo().getNumRegs());<br>
for (const auto &Op : Instr.Operands) {<br>
- if (Op.Tracker && Op.IsExplicit && Op.IsDef && !Op.IsMem) {<br>
- auto PossibleRegisters = Op.Tracker->sourceBits();<br>
+ if (Op.isReg() && Op.isExplicit() && Op.isDef() && !Op.isMemory()) {<br>
+ auto PossibleRegisters = Op.getRegisterAliasing().sourceBits();<br>
remove(PossibleRegisters, RATC.reservedRegisters());<br>
// Do not use the scratch memory address register.<br>
if (ScratchSpaceAliasedRegs)<br>
@@ -231,8 +217,8 @@ UopsSnippetGenerator::generateCodeTempla<br>
// And pick random use values that are not reserved and don't alias with defs.<br>
const auto DefAliases = getAliasedBits(State.getRegInfo(), Defs);<br>
for (const auto &Op : Instr.Operands) {<br>
- if (Op.Tracker && Op.IsExplicit && !Op.IsDef && !Op.IsMem) {<br>
- auto PossibleRegisters = Op.Tracker->sourceBits();<br>
+ if (Op.isReg() && Op.isExplicit() && Op.isUse() && !Op.isMemory()) {<br>
+ auto PossibleRegisters = Op.getRegisterAliasing().sourceBits();<br>
remove(PossibleRegisters, RATC.reservedRegisters());<br>
// Do not use the scratch memory address register.<br>
if (ScratchSpaceAliasedRegs)<br>
<br>
Modified: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp?rev=344028&r1=344027&r2=344028&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp?rev=344028&r1=344027&r2=344028&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp (original)<br>
+++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp Tue Oct 9 01:59:10 2018<br>
@@ -262,25 +262,25 @@ class ExegesisX86Target : public Exegesi<br>
// value for input and output.<br>
for (size_t I = 0, E = IT.Instr.Operands.size(); I < E; ++I) {<br>
const Operand *Op = &IT.Instr.Operands[I];<br>
- if (Op->IsExplicit && Op->IsMem) {<br>
+ if (Op->isExplicit() && Op->isMemory()) {<br>
// Case 1: 5-op memory.<br>
assert((I + 5 <= E) && "x86 memory references are always 5 ops");<br>
IT.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg<br>
Op = &IT.Instr.Operands[++I];<br>
- assert(Op->IsMem);<br>
- assert(Op->IsExplicit);<br>
+ assert(Op->isMemory());<br>
+ assert(Op->isExplicit());<br>
IT.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt<br>
Op = &IT.Instr.Operands[++I];<br>
- assert(Op->IsMem);<br>
- assert(Op->IsExplicit);<br>
+ assert(Op->isMemory());<br>
+ assert(Op->isExplicit());<br>
IT.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg<br>
Op = &IT.Instr.Operands[++I];<br>
- assert(Op->IsMem);<br>
- assert(Op->IsExplicit);<br>
+ assert(Op->isMemory());<br>
+ assert(Op->isExplicit());<br>
IT.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp<br>
Op = &IT.Instr.Operands[++I];<br>
- assert(Op->IsMem);<br>
- assert(Op->IsExplicit);<br>
+ assert(Op->isMemory());<br>
+ assert(Op->isExplicit());<br>
IT.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment<br>
// Case2: segment:index addressing. We assume that ES is 0.<br>
}<br>
<br>
<br>
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</blockquote></div>