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<p style="margin-top:0;margin-bottom:0">LGTM, cheers.</p>
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<p style="font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">Sam Parker</span></p>
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<p style="font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">Compilation Tools Engineer | Arm</span></p>
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<p style="font-family:"Times New Roman""><span style="font-family:Calibri,Helvetica,sans-serif">Arm.com</span></p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Sjoerd Meijer via Phabricator <reviews@reviews.llvm.org><br>
<b>Sent:</b> 21 September 2018 15:45:01<br>
<b>To:</b> Sjoerd Meijer; Sam Parker; David Green; t.p.northover@gmail.com; John Brawn; Javed Absar<br>
<b>Cc:</b> Kristof Beyls; christian.bruel@st.com; llvm-commits@lists.llvm.org; kanheim@a-bix.com; James Molloy; diana.picus@linaro.org; Florian Hahn<br>
<b>Subject:</b> [PATCH] D52289: [ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33</font>
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<div class="PlainText">SjoerdMeijer updated this revision to Diff 166483.<br>
SjoerdMeijer added a comment.<br>
<br>
Thanks for the reviews. <br>
Now take code size into account, and removed outdated comment.<br>
<br>
<br>
<a href="https://reviews.llvm.org/D52289">https://reviews.llvm.org/D52289</a><br>
<br>
Files:<br>
lib/Target/ARM/ARM.td<br>
lib/Target/ARM/ARMInstrInfo.td<br>
test/CodeGen/ARM/fmacs.ll<br>
test/CodeGen/Thumb2/float-intrinsics-float.ll<br>
<br>
<br>
Index: test/CodeGen/Thumb2/float-intrinsics-float.ll<br>
===================================================================<br>
--- test/CodeGen/Thumb2/float-intrinsics-float.ll<br>
+++ test/CodeGen/Thumb2/float-intrinsics-float.ll<br>
@@ -1,5 +1,6 @@<br>
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE<br>
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VMLA<br>
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=NO-VMLA<br>
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m33 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=NO-VMLA<br>
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8 -check-prefix=VMLA<br>
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=FP-ARMv8 -check-prefix=VMLA<br>
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4 -check-prefix=NO-VMLA<br>
@@ -188,8 +189,6 @@<br>
ret float %1<br>
}<br>
<br>
-; FIXME: why does cortex-m4 use vmla, while cortex-a7 uses vmul+vadd?<br>
-; (these should be equivalent, even the rounding is the same)<br>
declare float @llvm.fmuladd.f32(float %a, float %b, float %c)<br>
define float @fmuladd_f(float %a, float %b, float %c) {<br>
; CHECK-LABEL: fmuladd_f:<br>
Index: test/CodeGen/ARM/fmacs.ll<br>
===================================================================<br>
--- test/CodeGen/ARM/fmacs.ll<br>
+++ test/CodeGen/ARM/fmacs.ll<br>
@@ -3,6 +3,8 @@<br>
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8<br>
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9<br>
; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard %s -o - | FileCheck %s -check-prefix=HARD<br>
+; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard %s -o - | FileCheck %s -check-prefix=VMLA<br>
+; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-m33 -float-abi=hard %s -o - | FileCheck %s -check-prefix=VMLA<br>
<br>
define float @t1(float %acc, float %a, float %b) {<br>
entry:<br>
@@ -15,6 +17,21 @@<br>
; A8-LABEL: t1:<br>
; A8: vmul.f32<br>
; A8: vadd.f32<br>
+<br>
+; VMLA-LABEL: t1:<br>
+; VMLA: vmul.f32<br>
+; VMLA-NEXT: vadd.f32<br>
+<br>
+ %0 = fmul float %a, %b<br>
+ %1 = fadd float %acc, %0<br>
+ ret float %1<br>
+}<br>
+<br>
+define float @vlma_minsize(float %acc, float %a, float %b) #0 {<br>
+entry:<br>
+; VMLA-LABEL: vlma_minsize:<br>
+; VLMA: vmla.f32 s0, s1, s2<br>
+<br>
%0 = fmul float %a, %b<br>
%1 = fadd float %acc, %0<br>
ret float %1<br>
@@ -102,3 +119,5 @@<br>
%3 = fadd float %1, %2<br>
ret float %3<br>
}<br>
+<br>
+attributes #0 = { minsize nounwind optsize }<br>
Index: lib/Target/ARM/ARMInstrInfo.td<br>
===================================================================<br>
--- lib/Target/ARM/ARMInstrInfo.td<br>
+++ lib/Target/ARM/ARMInstrInfo.td<br>
@@ -353,10 +353,10 @@<br>
let RecomputePerFunction = 1 in {<br>
def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;<br>
def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;<br>
- def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">;<br>
- def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">;<br>
+ def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">;<br>
+ def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">;<br>
+ def UseFPVMLx : Predicate<"Subtarget->useFPVMLx() || MF->getFunction().optForMinSize()">;<br>
}<br>
-def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;<br>
def UseMulOps : Predicate<"Subtarget->useMulOps()">;<br>
<br>
// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.<br>
Index: lib/Target/ARM/ARM.td<br>
===================================================================<br>
--- lib/Target/ARM/ARM.td<br>
+++ lib/Target/ARM/ARM.td<br>
@@ -966,6 +966,7 @@<br>
FeatureVFPOnlySP,<br>
FeatureD16,<br>
FeaturePrefLoopAlign32,<br>
+ FeatureHasSlowFPVMLx,<br>
FeatureHasNoBranchPredictor]>;<br>
<br>
def : ProcNoItin<"cortex-m7", [ARMv7em,<br>
@@ -981,6 +982,7 @@<br>
FeatureD16,<br>
FeatureVFPOnlySP,<br>
FeaturePrefLoopAlign32,<br>
+ FeatureHasSlowFPVMLx,<br>
FeatureHasNoBranchPredictor]>;<br>
<br>
def : ProcNoItin<"cortex-a32", [ARMv8a,<br>
<br>
<br>
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