<div dir="ltr"><div><div class="gmail_signature" data-smartmail="gmail_signature">I'm not sure I understand why you have to bump the uops by +1. Is this because WriteRMW isn't listed as 2 uops?</div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div><br></div><br><div class="gmail_quote"><div dir="ltr">On Mon, Sep 24, 2018 at 1:13 PM Simon Pilgrim via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Mon Sep 24 13:11:50 2018<br>
New Revision: 342916<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=342916&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=342916&view=rev</a><br>
Log:<br>
[X86] Remove shift/rotate by CL memory (RMW) overrides<br>
<br>
The uops are slightly different to the register variant, so requires a +1uop tweak<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td<br>
llvm/trunk/lib/Target/X86/X86SchedHaswell.td<br>
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td<br>
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td<br>
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td<br>
llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll<br>
llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-bmi2.s<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Sep 24 13:11:50 2018<br>
@@ -84,7 +84,7 @@ def : ReadAdvance<ReadAfterLd, 5>;<br>
multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,<br>
list<ProcResourceKind> ExePorts,<br>
int Lat, list<int> Res = [1], int UOps = 1,<br>
- int LoadLat = 5> {<br>
+ int LoadLat = 5, int LoadUOps = 1> {<br>
// Register variant is using a single cycle on ExePort.<br>
def : WriteRes<SchedRW, ExePorts> {<br>
let Latency = Lat;<br>
@@ -97,7 +97,7 @@ multiclass BWWriteResPair<X86FoldableSch<br>
def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {<br>
let Latency = !add(Lat, LoadLat);<br>
let ResourceCycles = !listconcat([1], Res);<br>
- let NumMicroOps = !add(UOps, 1);<br>
+ let NumMicroOps = !add(UOps, LoadUOps);<br>
}<br>
}<br>
<br>
@@ -173,9 +173,9 @@ defm : BWWriteResPair<WritePOPCNT,<br>
<br>
// Integer shifts and rotates.<br>
defm : BWWriteResPair<WriteShift, [BWPort06], 1>;<br>
-defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3>;<br>
+defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3, 5, 2>;<br>
defm : BWWriteResPair<WriteRotate, [BWPort06], 2, [2], 2>;<br>
-defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3>;<br>
+defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3, 5, 2>;<br>
<br>
// SHLD/SHRD.<br>
defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;<br>
@@ -1167,11 +1167,6 @@ def BWWriteResGroup100 : SchedWriteRes<[<br>
let ResourceCycles = [1,1,1,2,1];<br>
}<br>
def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;<br>
-def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",<br>
- "ROR(8|16|32|64)mCL",<br>
- "SAR(8|16|32|64)mCL",<br>
- "SHL(8|16|32|64)mCL",<br>
- "SHR(8|16|32|64)mCL")>;<br>
<br>
def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {<br>
let Latency = 9;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Sep 24 13:11:50 2018<br>
@@ -89,7 +89,7 @@ def : ReadAdvance<ReadAfterLd, 5>;<br>
multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,<br>
list<ProcResourceKind> ExePorts,<br>
int Lat, list<int> Res = [1], int UOps = 1,<br>
- int LoadLat = 5> {<br>
+ int LoadLat = 5, int LoadUOps = 1> {<br>
// Register variant is using a single cycle on ExePort.<br>
def : WriteRes<SchedRW, ExePorts> {<br>
let Latency = Lat;<br>
@@ -102,7 +102,7 @@ multiclass HWWriteResPair<X86FoldableSch<br>
def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {<br>
let Latency = !add(Lat, LoadLat);<br>
let ResourceCycles = !listconcat([1], Res);<br>
- let NumMicroOps = !add(UOps, 1);<br>
+ let NumMicroOps = !add(UOps, LoadUOps);<br>
}<br>
}<br>
<br>
@@ -144,9 +144,9 @@ defm : X86WriteRes<WriteXCHG, [HWPort015<br>
<br>
// Integer shifts and rotates.<br>
defm : HWWriteResPair<WriteShift, [HWPort06], 1>;<br>
-defm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3>;<br>
+defm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3, 6, 2>;<br>
defm : HWWriteResPair<WriteRotate, [HWPort06], 2, [2], 2>;<br>
-defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3>;<br>
+defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3, 6, 2>;<br>
<br>
// SHLD/SHRD.<br>
defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;<br>
@@ -1306,11 +1306,6 @@ def HWWriteResGroup69 : SchedWriteRes<[H<br>
let NumMicroOps = 6;<br>
let ResourceCycles = [1,1,1,2,1];<br>
}<br>
-def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",<br>
- "ROR(8|16|32|64)mCL",<br>
- "SAR(8|16|32|64)mCL",<br>
- "SHL(8|16|32|64)mCL",<br>
- "SHR(8|16|32|64)mCL")>;<br>
def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;<br>
<br>
def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Sep 24 13:11:50 2018<br>
@@ -79,7 +79,7 @@ def : ReadAdvance<ReadAfterLd, 5>;<br>
multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,<br>
list<ProcResourceKind> ExePorts,<br>
int Lat, list<int> Res = [1], int UOps = 1,<br>
- int LoadLat = 5> {<br>
+ int LoadLat = 5, int LoadUOps = 1> {<br>
// Register variant is using a single cycle on ExePort.<br>
def : WriteRes<SchedRW, ExePorts> {<br>
let Latency = Lat;<br>
@@ -92,7 +92,7 @@ multiclass SBWriteResPair<X86FoldableSch<br>
def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {<br>
let Latency = !add(Lat, LoadLat);<br>
let ResourceCycles = !listconcat([1], Res);<br>
- let NumMicroOps = !add(UOps, 1);<br>
+ let NumMicroOps = !add(UOps, LoadUOps);<br>
}<br>
}<br>
<br>
@@ -144,10 +144,10 @@ defm : X86WriteRes<WriteSHDrrcl,[SBPort0<br>
defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>;<br>
defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>;<br>
<br>
-defm : SBWriteResPair<WriteShift, [SBPort05], 1>;<br>
-defm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3>;<br>
-defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>;<br>
-defm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3>;<br>
+defm : SBWriteResPair<WriteShift, [SBPort05], 1, [1], 1, 6, 2>;<br>
+defm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3, 6, 2>;<br>
+defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2, 6, 2>;<br>
+defm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3, 6, 2>;<br>
<br>
defm : SBWriteResPair<WriteJump, [SBPort5], 1>;<br>
defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>;<br>
@@ -924,10 +924,7 @@ def SBWriteResGroup69 : SchedWriteRes<[S<br>
}<br>
def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8",<br>
"BTR(16|32|64)mi8",<br>
- "BTS(16|32|64)mi8",<br>
- "SAR(8|16|32|64)m(1|i)",<br>
- "SHL(8|16|32|64)m(1|i)",<br>
- "SHR(8|16|32|64)m(1|i)")>;<br>
+ "BTS(16|32|64)mi8")>;<br>
<br>
def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {<br>
let Latency = 8;<br>
@@ -960,14 +957,6 @@ def SBWriteResGroup84 : SchedWriteRes<[S<br>
}<br>
def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>;<br>
<br>
-def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {<br>
- let Latency = 8;<br>
- let NumMicroOps = 5;<br>
- let ResourceCycles = [1,2,2];<br>
-}<br>
-def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",<br>
- "ROR(8|16|32|64)m(1|i)")>;<br>
-<br>
def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {<br>
let Latency = 8;<br>
let NumMicroOps = 5;<br>
@@ -1005,17 +994,6 @@ def SBWriteResGroup97 : SchedWriteRes<[S<br>
def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",<br>
"IST_FP(16|32|64)m")>;<br>
<br>
-def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {<br>
- let Latency = 9;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,2,3];<br>
-}<br>
-def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",<br>
- "ROR(8|16|32|64)mCL",<br>
- "SAR(8|16|32|64)mCL",<br>
- "SHL(8|16|32|64)mCL",<br>
- "SHR(8|16|32|64)mCL")>;<br>
-<br>
def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {<br>
let Latency = 9;<br>
let NumMicroOps = 6;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Sep 24 13:11:50 2018<br>
@@ -83,7 +83,7 @@ def : ReadAdvance<ReadAfterLd, 5>;<br>
multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,<br>
list<ProcResourceKind> ExePorts,<br>
int Lat, list<int> Res = [1], int UOps = 1,<br>
- int LoadLat = 5> {<br>
+ int LoadLat = 5, int LoadUOps = 1> {<br>
// Register variant is using a single cycle on ExePort.<br>
def : WriteRes<SchedRW, ExePorts> {<br>
let Latency = Lat;<br>
@@ -96,7 +96,7 @@ multiclass SKLWriteResPair<X86FoldableSc<br>
def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {<br>
let Latency = !add(Lat, LoadLat);<br>
let ResourceCycles = !listconcat([1], Res);<br>
- let NumMicroOps = !add(UOps, 1);<br>
+ let NumMicroOps = !add(UOps, LoadUOps);<br>
}<br>
}<br>
<br>
@@ -169,10 +169,10 @@ defm : SKLWriteResPair<WriteTZCNT,<br>
defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>;<br>
<br>
// Integer shifts and rotates.<br>
-defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;<br>
-defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>;<br>
-defm : SKLWriteResPair<WriteRotate, [SKLPort06], 2, [2], 2>;<br>
-defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>;<br>
+defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;<br>
+defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3, 5, 2>;<br>
+defm : SKLWriteResPair<WriteRotate, [SKLPort06], 2, [2], 2>;<br>
+defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3, 5, 2>;<br>
<br>
// SHLD/SHRD.<br>
defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;<br>
@@ -1246,17 +1246,6 @@ def SKLWriteResGroup116 : SchedWriteRes<<br>
def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",<br>
"RCR(8|16|32|64)m(1|i)")>;<br>
<br>
-def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {<br>
- let Latency = 8;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,1,3];<br>
-}<br>
-def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",<br>
- "ROR(8|16|32|64)mCL",<br>
- "SAR(8|16|32|64)mCL",<br>
- "SHL(8|16|32|64)mCL",<br>
- "SHR(8|16|32|64)mCL")>;<br>
-<br>
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {<br>
let Latency = 8;<br>
let NumMicroOps = 6;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Sep 24 13:11:50 2018<br>
@@ -83,7 +83,7 @@ def : ReadAdvance<ReadAfterLd, 5>;<br>
multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,<br>
list<ProcResourceKind> ExePorts,<br>
int Lat, list<int> Res = [1], int UOps = 1,<br>
- int LoadLat = 5> {<br>
+ int LoadLat = 5, int LoadUOps = 1> {<br>
// Register variant is using a single cycle on ExePort.<br>
def : WriteRes<SchedRW, ExePorts> {<br>
let Latency = Lat;<br>
@@ -96,7 +96,7 @@ multiclass SKXWriteResPair<X86FoldableSc<br>
def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {<br>
let Latency = !add(Lat, LoadLat);<br>
let ResourceCycles = !listconcat([1], Res);<br>
- let NumMicroOps = !add(UOps, 1);<br>
+ let NumMicroOps = !add(UOps, LoadUOps);<br>
}<br>
}<br>
<br>
@@ -163,10 +163,10 @@ def : WriteRes<WriteLAHFSAHF, [SKXPort0<br>
def : WriteRes<WriteBitTest, [SKXPort06]>; //<br>
<br>
// Integer shifts and rotates.<br>
-defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;<br>
-defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>;<br>
-defm : SKXWriteResPair<WriteRotate, [SKXPort06], 2, [2], 2>;<br>
-defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>;<br>
+defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;<br>
+defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3, 5, 2>;<br>
+defm : SKXWriteResPair<WriteRotate, [SKXPort06], 2, [2], 2>;<br>
+defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3, 5, 2>;<br>
<br>
// SHLD/SHRD.<br>
defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;<br>
@@ -1599,17 +1599,6 @@ def SKXWriteResGroup127 : SchedWriteRes<<br>
def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",<br>
"RCR(8|16|32|64)m(1|i)")>;<br>
<br>
-def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {<br>
- let Latency = 8;<br>
- let NumMicroOps = 6;<br>
- let ResourceCycles = [1,1,1,3];<br>
-}<br>
-def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",<br>
- "ROR(8|16|32|64)mCL",<br>
- "SAR(8|16|32|64)mCL",<br>
- "SHL(8|16|32|64)mCL",<br>
- "SHR(8|16|32|64)mCL")>;<br>
-<br>
def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {<br>
let Latency = 8;<br>
let NumMicroOps = 6;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll Mon Sep 24 13:11:50 2018<br>
@@ -430,7 +430,7 @@ define i32 @test_rorx_i32(i32 %a0, i32 %<br>
; GENERIC-LABEL: test_rorx_i32:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.50]<br>
-; GENERIC-NEXT: rorxl $5, (%rdx), %eax # sched: [6:0.50]<br>
+; GENERIC-NEXT: rorxl $5, (%rdx), %eax # sched: [7:0.50]<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -483,7 +483,7 @@ define i64 @test_rorx_i64(i64 %a0, i64 %<br>
; GENERIC-LABEL: test_rorx_i64:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.50]<br>
-; GENERIC-NEXT: rorxq $5, (%rdx), %rax # sched: [6:0.50]<br>
+; GENERIC-NEXT: rorxq $5, (%rdx), %rax # sched: [7:0.50]<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -536,7 +536,7 @@ define i32 @test_sarx_i32(i32 %a0, i32 %<br>
; GENERIC-LABEL: test_sarx_i32:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.50]<br>
-; GENERIC-NEXT: sarxl %esi, (%rdx), %eax # sched: [6:0.50]<br>
+; GENERIC-NEXT: sarxl %esi, (%rdx), %eax # sched: [7:0.50]<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -585,7 +585,7 @@ define i64 @test_sarx_i64(i64 %a0, i64 %<br>
; GENERIC-LABEL: test_sarx_i64:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
-; GENERIC-NEXT: sarxq %rsi, (%rdx), %rax # sched: [6:0.50]<br>
+; GENERIC-NEXT: sarxq %rsi, (%rdx), %rax # sched: [7:0.50]<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -634,7 +634,7 @@ define i32 @test_shlx_i32(i32 %a0, i32 %<br>
; GENERIC-LABEL: test_shlx_i32:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.50]<br>
-; GENERIC-NEXT: shlxl %esi, (%rdx), %eax # sched: [6:0.50]<br>
+; GENERIC-NEXT: shlxl %esi, (%rdx), %eax # sched: [7:0.50]<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -683,7 +683,7 @@ define i64 @test_shlx_i64(i64 %a0, i64 %<br>
; GENERIC-LABEL: test_shlx_i64:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
-; GENERIC-NEXT: shlxq %rsi, (%rdx), %rax # sched: [6:0.50]<br>
+; GENERIC-NEXT: shlxq %rsi, (%rdx), %rax # sched: [7:0.50]<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -732,7 +732,7 @@ define i32 @test_shrx_i32(i32 %a0, i32 %<br>
; GENERIC-LABEL: test_shrx_i32:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.50]<br>
-; GENERIC-NEXT: shrxl %esi, (%rdx), %eax # sched: [6:0.50]<br>
+; GENERIC-NEXT: shrxl %esi, (%rdx), %eax # sched: [7:0.50]<br>
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
@@ -781,7 +781,7 @@ define i64 @test_shrx_i64(i64 %a0, i64 %<br>
; GENERIC-LABEL: test_shrx_i64:<br>
; GENERIC: # %bb.0:<br>
; GENERIC-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.50]<br>
-; GENERIC-NEXT: shrxq %rsi, (%rdx), %rax # sched: [6:0.50]<br>
+; GENERIC-NEXT: shrxq %rsi, (%rdx), %rax # sched: [7:0.50]<br>
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]<br>
; GENERIC-NEXT: retq # sched: [1:1.00]<br>
;<br>
<br>
Modified: llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-bmi2.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-bmi2.s?rev=342916&r1=342915&r2=342916&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-bmi2.s?rev=342916&r1=342915&r2=342916&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-bmi2.s (original)<br>
+++ llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-bmi2.s Mon Sep 24 13:11:50 2018<br>
@@ -75,21 +75,21 @@ shrx %rax, (%rbx), %rcx<br>
# CHECK-NEXT: 1 1 0.33 pextq %rax, %rbx, %rcx<br>
# CHECK-NEXT: 2 6 0.50 * pextq (%rax), %rbx, %rcx<br>
# CHECK-NEXT: 1 1 0.50 rorxl $1, %eax, %ecx<br>
-# CHECK-NEXT: 2 6 0.50 * rorxl $1, (%rax), %ecx<br>
+# CHECK-NEXT: 3 7 0.50 * rorxl $1, (%rax), %ecx<br>
# CHECK-NEXT: 1 1 0.50 rorxq $1, %rax, %rcx<br>
-# CHECK-NEXT: 2 6 0.50 * rorxq $1, (%rax), %rcx<br>
+# CHECK-NEXT: 3 7 0.50 * rorxq $1, (%rax), %rcx<br>
# CHECK-NEXT: 1 1 0.50 sarxl %eax, %ebx, %ecx<br>
-# CHECK-NEXT: 2 6 0.50 * sarxl %eax, (%rbx), %ecx<br>
+# CHECK-NEXT: 3 7 0.50 * sarxl %eax, (%rbx), %ecx<br>
# CHECK-NEXT: 1 1 0.50 sarxq %rax, %rbx, %rcx<br>
-# CHECK-NEXT: 2 6 0.50 * sarxq %rax, (%rbx), %rcx<br>
+# CHECK-NEXT: 3 7 0.50 * sarxq %rax, (%rbx), %rcx<br>
# CHECK-NEXT: 1 1 0.50 shlxl %eax, %ebx, %ecx<br>
-# CHECK-NEXT: 2 6 0.50 * shlxl %eax, (%rbx), %ecx<br>
+# CHECK-NEXT: 3 7 0.50 * shlxl %eax, (%rbx), %ecx<br>
# CHECK-NEXT: 1 1 0.50 shlxq %rax, %rbx, %rcx<br>
-# CHECK-NEXT: 2 6 0.50 * shlxq %rax, (%rbx), %rcx<br>
+# CHECK-NEXT: 3 7 0.50 * shlxq %rax, (%rbx), %rcx<br>
# CHECK-NEXT: 1 1 0.50 shrxl %eax, %ebx, %ecx<br>
-# CHECK-NEXT: 2 6 0.50 * shrxl %eax, (%rbx), %ecx<br>
+# CHECK-NEXT: 3 7 0.50 * shrxl %eax, (%rbx), %ecx<br>
# CHECK-NEXT: 1 1 0.50 shrxq %rax, %rbx, %rcx<br>
-# CHECK-NEXT: 2 6 0.50 * shrxq %rax, (%rbx), %rcx<br>
+# CHECK-NEXT: 3 7 0.50 * shrxq %rax, (%rbx), %rcx<br>
<br>
# CHECK: Resources:<br>
# CHECK-NEXT: [0] - SBDivider<br>
<br>
<br>
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</blockquote></div>