<div><div dir="auto">Are these used outside of lowering today? DAG combine should be using splitOpsAndApply to deal with arbitrarily wide types.</div></div><div><br><div class="gmail_quote"><div dir="ltr">On Wed, Sep 19, 2018 at 11:53 AM Sanjay Patel via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: spatel<br>
Date: Wed Sep 19 11:52:00 2018<br>
New Revision: 342575<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=342575&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=342575&view=rev</a><br>
Log:<br>
[x86] change names of vector splitting helper functions; NFC<br>
<br>
As the code comments suggest, these are about splitting, and they<br>
are not necessarily limited to lowering, so that misled me.<br>
<br>
There's nothing that's actually x86-specific in these either, so <br>
they might be better placed in a common header so any target can <br>
use them.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=342575&r1=342574&r2=342575&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=342575&r1=342574&r2=342575&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 19 11:52:00 2018<br>
@@ -22832,7 +22832,7 @@ static SDValue LowerCTTZ(SDValue Op, Sel<br>
<br>
/// Break a 256-bit integer operation into two new 128-bit ones and then<br>
/// concatenate the result back.<br>
-static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {<br>
+static SDValue split256IntArith(SDValue Op, SelectionDAG &DAG) {<br>
MVT VT = Op.getSimpleValueType();<br>
<br>
assert(VT.is256BitVector() && VT.isInteger() &&<br>
@@ -22861,7 +22861,7 @@ static SDValue Lower256IntArith(SDValue<br>
<br>
/// Break a 512-bit integer operation into two new 256-bit ones and then<br>
/// concatenate the result back.<br>
-static SDValue Lower512IntArith(SDValue Op, SelectionDAG &DAG) {<br>
+static SDValue split512IntArith(SDValue Op, SelectionDAG &DAG) {<br>
MVT VT = Op.getSimpleValueType();<br>
<br>
assert(VT.is512BitVector() && VT.isInteger() &&<br>
@@ -22896,7 +22896,7 @@ static SDValue LowerADD_SUB(SDValue Op,<br>
assert(Op.getSimpleValueType().is256BitVector() &&<br>
Op.getSimpleValueType().isInteger() &&<br>
"Only handle AVX 256-bit vector integer operation");<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
}<br>
<br>
static SDValue LowerABS(SDValue Op, SelectionDAG &DAG) {<br>
@@ -22924,7 +22924,7 @@ static SDValue LowerMINMAX(SDValue Op, S<br>
<br>
// For AVX1 cases, split to use legal ops (everything but v4i64).<br>
if (VT.getScalarType() != MVT::i64 && VT.is256BitVector())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
<br>
SDLoc DL(Op);<br>
unsigned Opcode = Op.getOpcode();<br>
@@ -22966,9 +22966,9 @@ static SDValue LowerMUL(SDValue Op, cons<br>
if (VT.getScalarType() == MVT::i1)<br>
return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));<br>
<br>
- // Decompose 256-bit ops into smaller 128-bit ops.<br>
+ // Decompose 256-bit ops into 128-bit ops.<br>
if (VT.is256BitVector() && !Subtarget.hasInt256())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
<br>
SDValue A = Op.getOperand(0);<br>
SDValue B = Op.getOperand(1);<br>
@@ -22980,13 +22980,13 @@ static SDValue LowerMUL(SDValue Op, cons<br>
// For 512-bit vectors, split into 256-bit vectors to allow the<br>
// sign-extension to occur.<br>
if (VT == MVT::v64i8)<br>
- return Lower512IntArith(Op, DAG);<br>
+ return split512IntArith(Op, DAG);<br>
<br>
// For 256-bit vectors, split into 128-bit vectors to allow the<br>
// sign-extension to occur. We don't need this on AVX512BW as we can<br>
// safely sign-extend to v32i16.<br>
if (VT == MVT::v32i8 && !Subtarget.hasBWI())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
<br>
MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());<br>
return DAG.getNode(<br>
@@ -23117,9 +23117,9 @@ static SDValue LowerMULH(SDValue Op, con<br>
SDValue A = Op.getOperand(0);<br>
SDValue B = Op.getOperand(1);<br>
<br>
- // Decompose 256-bit ops into smaller 128-bit ops.<br>
+ // Decompose 256-bit ops into 128-bit ops.<br>
if (VT.is256BitVector() && !Subtarget.hasInt256())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
<br>
if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {<br>
assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||<br>
@@ -23202,7 +23202,7 @@ static SDValue LowerMULH(SDValue Op, con<br>
// For 512-bit vectors, split into 256-bit vectors to allow the<br>
// sign-extension to occur.<br>
if (VT == MVT::v64i8)<br>
- return Lower512IntArith(Op, DAG);<br>
+ return split512IntArith(Op, DAG);<br>
<br>
// AVX2 implementations - extend xmm subvectors to ymm.<br>
if (Subtarget.hasInt256()) {<br>
@@ -24257,9 +24257,9 @@ static SDValue LowerShift(SDValue Op, co<br>
return R;<br>
}<br>
<br>
- // Decompose 256-bit shifts into smaller 128-bit shifts.<br>
+ // Decompose 256-bit shifts into 128-bit shifts.<br>
if (VT.is256BitVector())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
<br>
return SDValue();<br>
}<br>
@@ -24299,9 +24299,8 @@ static SDValue LowerRotate(SDValue Op, c<br>
// XOP has 128-bit vector variable + immediate rotates.<br>
// +ve/-ve Amt = rotate left/right - just need to handle ISD::ROTL.<br>
if (Subtarget.hasXOP()) {<br>
- // Split 256-bit integers.<br>
if (VT.is256BitVector())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");<br>
<br>
// Attempt to rotate by immediate.<br>
@@ -24320,7 +24319,7 @@ static SDValue LowerRotate(SDValue Op, c<br>
<br>
// Split 256-bit integers on pre-AVX2 targets.<br>
if (VT.is256BitVector() && !Subtarget.hasAVX2())<br>
- return Lower256IntArith(Op, DAG);<br>
+ return split256IntArith(Op, DAG);<br>
<br>
assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||<br>
((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&<br>
<br>
<br>
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</blockquote></div></div>-- <br><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div>