<div dir="ltr"><br><br><div class="gmail_quote"><div dir="ltr">On Tue, Sep 11, 2018 at 8:58 PM Konstantin Zhuravlyov via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: kzhuravl<br>
Date: Tue Sep 11 11:56:51 2018<br>
New Revision: 341982<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=341982&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=341982&view=rev</a><br>
Log:<br>
AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination<br>
into TargetParser.<br>
<br>
Also switch away from target features to CPU string when<br>
determining isa version. This fixes an issue when we<br>
output wrong isa version in the object code when features<br>
of a particular CPU are altered (i.e. gfx902 w/o xnack<br>
used to result in gfx900).<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D51890" rel="noreferrer" target="_blank">https://reviews.llvm.org/D51890</a><br>
<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/AMDGPU/gfx902-without-xnack.ll<br>
Modified:<br>
llvm/trunk/include/llvm/Support/TargetParser.h<br>
llvm/trunk/lib/Support/TargetParser.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h<br>
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp<br>
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp<br>
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h<br>
llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h<br>
llvm/trunk/test/MC/AMDGPU/hsa_isa_version_attrs.s<br>
<br>
Modified: llvm/trunk/include/llvm/Support/TargetParser.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/TargetParser.h (original)<br>
+++ llvm/trunk/include/llvm/Support/TargetParser.h Tue Sep 11 11:56:51 2018<br>
@@ -320,6 +320,13 @@ enum GPUKind : uint32_t {<br>
GK_AMDGCN_LAST = GK_GFX906,<br>
};<br>
<br>
+/// Instruction set architecture version.<br>
+struct IsaVersion {<br>
+ unsigned Major;<br>
+ unsigned Minor;<br>
+ unsigned Stepping;<br>
+};<br>
+<br>
// This isn't comprehensive for now, just things that are needed from the<br>
// frontend driver.<br>
enum ArchFeatureKind : uint32_t {<br>
@@ -335,18 +342,22 @@ enum ArchFeatureKind : uint32_t {<br>
FEATURE_FAST_DENORMAL_F32 = 1 << 5<br>
};<br>
<br>
-GPUKind parseArchAMDGCN(StringRef CPU);<br>
-GPUKind parseArchR600(StringRef CPU);<br>
StringRef getArchNameAMDGCN(GPUKind AK);<br>
StringRef getArchNameR600(GPUKind AK);<br>
StringRef getCanonicalArchName(StringRef Arch);<br>
+GPUKind parseArchAMDGCN(StringRef CPU);<br>
+GPUKind parseArchR600(StringRef CPU);<br>
unsigned getArchAttrAMDGCN(GPUKind AK);<br>
unsigned getArchAttrR600(GPUKind AK);<br>
<br>
void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values);<br>
void fillValidArchListR600(SmallVectorImpl<StringRef> &Values);<br>
<br>
-}<br>
+StringRef getArchNameFromElfMach(unsigned ElfMach);<br>
+unsigned getElfMach(StringRef GPU);<br>
+IsaVersion getIsaVersion(StringRef GPU);<br>
+<br>
+} // namespace AMDGPU<br>
<br>
} // namespace llvm<br>
<br>
<br>
Modified: llvm/trunk/lib/Support/TargetParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/TargetParser.cpp (original)<br>
+++ llvm/trunk/lib/Support/TargetParser.cpp Tue Sep 11 11:56:51 2018<br>
@@ -17,11 +17,13 @@<br>
#include "llvm/ADT/ArrayRef.h"<br>
#include "llvm/ADT/StringSwitch.h"<br>
#include "llvm/ADT/Twine.h"<br>
+#include "llvm/BinaryFormat/ELF.h"<br></blockquote><div><br></div><div>This is a layering violation, lib/Support cannot depend on things in BinaryFormat.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
#include <cctype><br>
<br>
using namespace llvm;<br>
using namespace ARM;<br>
using namespace AArch64;<br>
+using namespace AMDGPU;<br>
<br>
namespace {<br>
<br>
@@ -947,6 +949,8 @@ bool llvm::AArch64::isX18ReservedByDefau<br>
TT.isOSWindows();<br>
}<br>
<br>
+namespace {<br>
+<br>
struct GPUInfo {<br>
StringLiteral Name;<br>
StringLiteral CanonicalName;<br>
@@ -954,11 +958,9 @@ struct GPUInfo {<br>
unsigned Features;<br>
};<br>
<br>
-using namespace AMDGPU;<br>
-static constexpr GPUInfo R600GPUs[26] = {<br>
- // Name Canonical Kind Features<br>
- // Name<br>
- //<br>
+constexpr GPUInfo R600GPUs[26] = {<br>
+ // Name Canonical Kind Features<br>
+ // Name<br>
{{"r600"}, {"r600"}, GK_R600, FEATURE_NONE },<br>
{{"rv630"}, {"r600"}, GK_R600, FEATURE_NONE },<br>
{{"rv635"}, {"r600"}, GK_R600, FEATURE_NONE },<br>
@@ -989,9 +991,9 @@ static constexpr GPUInfo R600GPUs[26] =<br>
<br>
// This table should be sorted by the value of GPUKind<br>
// Don't bother listing the implicitly true features<br>
-static constexpr GPUInfo AMDGCNGPUs[32] = {<br>
- // Name Canonical Kind Features<br>
- // Name<br>
+constexpr GPUInfo AMDGCNGPUs[32] = {<br>
+ // Name Canonical Kind Features<br>
+ // Name<br>
{{"gfx600"}, {"gfx600"}, GK_GFX600, FEATURE_FAST_FMA_F32},<br>
{{"tahiti"}, {"gfx600"}, GK_GFX600, FEATURE_FAST_FMA_F32},<br>
{{"gfx601"}, {"gfx601"}, GK_GFX601, FEATURE_NONE},<br>
@@ -1026,8 +1028,7 @@ static constexpr GPUInfo AMDGCNGPUs[32]<br>
{{"gfx906"}, {"gfx906"}, GK_GFX906, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32},<br>
};<br>
<br>
-static const GPUInfo *getArchEntry(AMDGPU::GPUKind AK,<br>
- ArrayRef<GPUInfo> Table) {<br>
+const GPUInfo *getArchEntry(AMDGPU::GPUKind AK, ArrayRef<GPUInfo> Table) {<br>
GPUInfo Search = { {""}, {""}, AK, AMDGPU::FEATURE_NONE };<br>
<br>
auto I = std::lower_bound(Table.begin(), Table.end(), Search,<br>
@@ -1040,6 +1041,8 @@ static const GPUInfo *getArchEntry(AMDGP<br>
return I;<br>
}<br>
<br>
+} // namespace<br>
+<br>
StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK) {<br>
if (const auto *Entry = getArchEntry(AK, AMDGCNGPUs))<br>
return Entry->CanonicalName;<br>
@@ -1092,3 +1095,118 @@ void AMDGPU::fillValidArchListR600(Small<br>
for (const auto C : R600GPUs)<br>
Values.push_back(C.Name);<br>
}<br>
+<br>
+StringRef AMDGPU::getArchNameFromElfMach(unsigned ElfMach) {<br>
+ AMDGPU::GPUKind AK;<br>
+<br>
+ switch (ElfMach) {<br>
+ case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;<br>
+ case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;<br>
+ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;<br>
+ case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;<br>
+ }<br>
+<br>
+ StringRef GPUName = getArchNameAMDGCN(AK);<br>
+ if (GPUName != "")<br>
+ return GPUName;<br>
+ return getArchNameR600(AK);<br>
+}<br>
+<br>
+unsigned AMDGPU::getElfMach(StringRef GPU) {<br>
+ AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);<br>
+ if (AK == AMDGPU::GPUKind::GK_NONE)<br>
+ AK = parseArchR600(GPU);<br>
+<br>
+ switch (AK) {<br>
+ case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;<br>
+ case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;<br>
+ case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;<br>
+ case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;<br>
+ case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;<br>
+ case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;<br>
+ case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;<br>
+ case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;<br>
+ case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;<br>
+ case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;<br>
+ case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;<br>
+ case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;<br>
+ case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;<br>
+ case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;<br>
+ case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;<br>
+ case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;<br>
+ case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;<br>
+ case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;<br>
+ case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;<br>
+ case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;<br>
+ case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;<br>
+ case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;<br>
+ case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;<br>
+ case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;<br>
+ case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;<br>
+ case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;<br>
+ case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;<br>
+ case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;<br>
+ case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;<br>
+ case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;<br>
+ case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;<br>
+ case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;<br>
+ }<br>
+<br>
+ llvm_unreachable("unknown GPU");<br>
+}<br>
+<br>
+AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {<br>
+ if (GPU == "generic")<br>
+ return {7, 0, 0};<br>
+<br>
+ AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);<br>
+ if (AK == AMDGPU::GPUKind::GK_NONE)<br>
+ return {0, 0, 0};<br>
+<br>
+ switch (AK) {<br>
+ case GK_GFX600: return {6, 0, 0};<br>
+ case GK_GFX601: return {6, 0, 1};<br>
+ case GK_GFX700: return {7, 0, 0};<br>
+ case GK_GFX701: return {7, 0, 1};<br>
+ case GK_GFX702: return {7, 0, 2};<br>
+ case GK_GFX703: return {7, 0, 3};<br>
+ case GK_GFX704: return {7, 0, 4};<br>
+ case GK_GFX801: return {8, 0, 1};<br>
+ case GK_GFX802: return {8, 0, 2};<br>
+ case GK_GFX803: return {8, 0, 3};<br>
+ case GK_GFX810: return {8, 1, 0};<br>
+ case GK_GFX900: return {9, 0, 0};<br>
+ case GK_GFX902: return {9, 0, 2};<br>
+ case GK_GFX904: return {9, 0, 4};<br>
+ case GK_GFX906: return {9, 0, 6};<br>
+ default: return {0, 0, 0};<br>
+ }<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Tue Sep 11 11:56:51 2018<br>
@@ -40,6 +40,7 @@<br>
#include "llvm/MC/MCStreamer.h"<br>
#include "llvm/Support/AMDGPUMetadata.h"<br>
#include "llvm/Support/MathExtras.h"<br>
+#include "llvm/Support/TargetParser.h"<br>
#include "llvm/Support/TargetRegistry.h"<br>
#include "llvm/Target/TargetLoweringObjectFile.h"<br>
<br>
@@ -134,9 +135,9 @@ void AMDGPUAsmPrinter::EmitStartOfAsmFil<br>
getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);<br>
<br>
// HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.<br>
- IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());<br>
+ IsaVersion Version = getIsaVersion(getSTI()->getCPU());<br>
getTargetStreamer()->EmitDirectiveHSACodeObjectISA(<br>
- ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");<br>
+ Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");<br>
}<br>
<br>
void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {<br>
@@ -240,7 +241,7 @@ void AMDGPUAsmPrinter::EmitFunctionBodyE<br>
*getSTI(), KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),<br>
CurrentProgramInfo.NumVGPRsForWavesPerEU,<br>
CurrentProgramInfo.NumSGPRsForWavesPerEU -<br>
- IsaInfo::getNumExtraSGPRs(getSTI()->getFeatureBits(),<br>
+ IsaInfo::getNumExtraSGPRs(getSTI(),<br>
CurrentProgramInfo.VCCUsed,<br>
CurrentProgramInfo.FlatUsed),<br>
CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,<br>
@@ -561,7 +562,7 @@ static bool hasAnyNonFlatUseOfReg(const<br>
<br>
int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(<br>
const GCNSubtarget &ST) const {<br>
- return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(ST.getFeatureBits(),<br>
+ return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,<br>
UsesVCC, UsesFlatScratch);<br>
}<br>
<br>
@@ -758,7 +759,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo<br>
<br>
// 48 SGPRs - vcc, - flat_scr, -xnack<br>
int MaxSGPRGuess =<br>
- 47 - IsaInfo::getNumExtraSGPRs(ST.getFeatureBits(), true,<br>
+ 47 - IsaInfo::getNumExtraSGPRs(getSTI(), true,<br>
ST.hasFlatAddressSpace());<br>
MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);<br>
MaxVGPR = std::max(MaxVGPR, 23);<br>
@@ -823,7 +824,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(<br>
// duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be<br>
// unified.<br>
unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(<br>
- STM.getFeatureBits(), ProgInfo.VCCUsed, ProgInfo.FlatUsed);<br>
+ getSTI(), ProgInfo.VCCUsed, ProgInfo.FlatUsed);<br>
<br>
// Check the addressable register limit before we add ExtraSGPRs.<br>
if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&<br>
@@ -905,9 +906,9 @@ void AMDGPUAsmPrinter::getSIProgramInfo(<br>
}<br>
<br>
ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(<br>
- STM.getFeatureBits(), ProgInfo.NumSGPRsForWavesPerEU);<br>
+ getSTI(), ProgInfo.NumSGPRsForWavesPerEU);<br>
ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(<br>
- STM.getFeatureBits(), ProgInfo.NumVGPRsForWavesPerEU);<br>
+ getSTI(), ProgInfo.NumVGPRsForWavesPerEU);<br>
<br>
// Update DebuggerWavefrontPrivateSegmentOffsetSGPR and<br>
// DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"<br>
@@ -1137,7 +1138,7 @@ void AMDGPUAsmPrinter::getAmdKernelCode(<br>
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();<br>
const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();<br>
<br>
- AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());<br>
+ AMDGPU::initDefaultAMDKernelCodeT(Out, getSTI());<br>
<br>
Out.compute_pgm_resource_registers =<br>
CurrentProgramInfo.ComputePGMRSrc1 |<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Tue Sep 11 11:56:51 2018<br>
@@ -124,10 +124,8 @@ GCNSubtarget::initializeSubtargetDepende<br>
return *this;<br>
}<br>
<br>
-AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT,<br>
- const FeatureBitset &FeatureBits) :<br>
+AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) :<br>
TargetTriple(TT),<br>
- SubtargetFeatureBits(FeatureBits),<br>
Has16BitInsts(false),<br>
HasMadMixInsts(false),<br>
FP32Denormals(false),<br>
@@ -144,9 +142,9 @@ AMDGPUSubtarget::AMDGPUSubtarget(const T<br>
{ }<br>
<br>
GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,<br>
- const GCNTargetMachine &TM) :<br>
+ const GCNTargetMachine &TM) :<br>
AMDGPUGenSubtargetInfo(TT, GPU, FS),<br>
- AMDGPUSubtarget(TT, getFeatureBits()),<br>
+ AMDGPUSubtarget(TT),<br>
TargetTriple(TT),<br>
Gen(SOUTHERN_ISLANDS),<br>
IsaVersion(ISAVersion0_0_0),<br>
@@ -448,7 +446,7 @@ unsigned AMDGPUSubtarget::getKernArgSegm<br>
R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,<br>
const TargetMachine &TM) :<br>
R600GenSubtargetInfo(TT, GPU, FS),<br>
- AMDGPUSubtarget(TT, getFeatureBits()),<br>
+ AMDGPUSubtarget(TT),<br>
InstrInfo(*this),<br>
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),<br>
FMA(false),<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Tue Sep 11 11:56:51 2018<br>
@@ -63,7 +63,6 @@ private:<br>
Triple TargetTriple;<br>
<br>
protected:<br>
- const FeatureBitset &SubtargetFeatureBits;<br>
bool Has16BitInsts;<br>
bool HasMadMixInsts;<br>
bool FP32Denormals;<br>
@@ -79,7 +78,7 @@ protected:<br>
unsigned WavefrontSize;<br>
<br>
public:<br>
- AMDGPUSubtarget(const Triple &TT, const FeatureBitset &FeatureBits);<br>
+ AMDGPUSubtarget(const Triple &TT);<br>
<br>
static const AMDGPUSubtarget &get(const MachineFunction &MF);<br>
static const AMDGPUSubtarget &get(const TargetMachine &TM,<br>
@@ -203,33 +202,21 @@ public:<br>
<br>
/// \returns Maximum number of work groups per compute unit supported by the<br>
/// subtarget and limited by given \p FlatWorkGroupSize.<br>
- unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {<br>
- return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(SubtargetFeatureBits,<br>
- FlatWorkGroupSize);<br>
- }<br>
+ virtual unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const = 0;<br>
<br>
/// \returns Minimum flat work group size supported by the subtarget.<br>
- unsigned getMinFlatWorkGroupSize() const {<br>
- return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(SubtargetFeatureBits);<br>
- }<br>
+ virtual unsigned getMinFlatWorkGroupSize() const = 0;<br>
<br>
/// \returns Maximum flat work group size supported by the subtarget.<br>
- unsigned getMaxFlatWorkGroupSize() const {<br>
- return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(SubtargetFeatureBits);<br>
- }<br>
+ virtual unsigned getMaxFlatWorkGroupSize() const = 0;<br>
<br>
/// \returns Maximum number of waves per execution unit supported by the<br>
/// subtarget and limited by given \p FlatWorkGroupSize.<br>
- unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {<br>
- return AMDGPU::IsaInfo::getMaxWavesPerEU(SubtargetFeatureBits,<br>
- FlatWorkGroupSize);<br>
- }<br>
+ virtual unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const = 0;<br>
<br>
/// \returns Minimum number of waves per execution unit supported by the<br>
/// subtarget.<br>
- unsigned getMinWavesPerEU() const {<br>
- return AMDGPU::IsaInfo::getMinWavesPerEU(SubtargetFeatureBits);<br>
- }<br>
+ virtual unsigned getMinWavesPerEU() const = 0;<br>
<br>
unsigned getMaxWavesPerEU() const { return 10; }<br>
<br>
@@ -708,20 +695,19 @@ public:<br>
/// \returns Number of execution units per compute unit supported by the<br>
/// subtarget.<br>
unsigned getEUsPerCU() const {<br>
- return AMDGPU::IsaInfo::getEUsPerCU(MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getEUsPerCU(this);<br>
}<br>
<br>
/// \returns Maximum number of waves per compute unit supported by the<br>
/// subtarget without any kind of limitation.<br>
unsigned getMaxWavesPerCU() const {<br>
- return AMDGPU::IsaInfo::getMaxWavesPerCU(MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getMaxWavesPerCU(this);<br>
}<br>
<br>
/// \returns Maximum number of waves per compute unit supported by the<br>
/// subtarget and limited by given \p FlatWorkGroupSize.<br>
unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {<br>
- return AMDGPU::IsaInfo::getMaxWavesPerCU(MCSubtargetInfo::getFeatureBits(),<br>
- FlatWorkGroupSize);<br>
+ return AMDGPU::IsaInfo::getMaxWavesPerCU(this, FlatWorkGroupSize);<br>
}<br>
<br>
/// \returns Maximum number of waves per execution unit supported by the<br>
@@ -733,8 +719,7 @@ public:<br>
/// \returns Number of waves per work group supported by the subtarget and<br>
/// limited by given \p FlatWorkGroupSize.<br>
unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {<br>
- return AMDGPU::IsaInfo::getWavesPerWorkGroup(<br>
- MCSubtargetInfo::getFeatureBits(), FlatWorkGroupSize);<br>
+ return AMDGPU::IsaInfo::getWavesPerWorkGroup(this, FlatWorkGroupSize);<br>
}<br>
<br>
// static wrappers<br>
@@ -853,39 +838,34 @@ public:<br>
<br>
/// \returns SGPR allocation granularity supported by the subtarget.<br>
unsigned getSGPRAllocGranule() const {<br>
- return AMDGPU::IsaInfo::getSGPRAllocGranule(<br>
- MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getSGPRAllocGranule(this);<br>
}<br>
<br>
/// \returns SGPR encoding granularity supported by the subtarget.<br>
unsigned getSGPREncodingGranule() const {<br>
- return AMDGPU::IsaInfo::getSGPREncodingGranule(<br>
- MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getSGPREncodingGranule(this);<br>
}<br>
<br>
/// \returns Total number of SGPRs supported by the subtarget.<br>
unsigned getTotalNumSGPRs() const {<br>
- return AMDGPU::IsaInfo::getTotalNumSGPRs(MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getTotalNumSGPRs(this);<br>
}<br>
<br>
/// \returns Addressable number of SGPRs supported by the subtarget.<br>
unsigned getAddressableNumSGPRs() const {<br>
- return AMDGPU::IsaInfo::getAddressableNumSGPRs(<br>
- MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getAddressableNumSGPRs(this);<br>
}<br>
<br>
/// \returns Minimum number of SGPRs that meets the given number of waves per<br>
/// execution unit requirement supported by the subtarget.<br>
unsigned getMinNumSGPRs(unsigned WavesPerEU) const {<br>
- return AMDGPU::IsaInfo::getMinNumSGPRs(MCSubtargetInfo::getFeatureBits(),<br>
- WavesPerEU);<br>
+ return AMDGPU::IsaInfo::getMinNumSGPRs(this, WavesPerEU);<br>
}<br>
<br>
/// \returns Maximum number of SGPRs that meets the given number of waves per<br>
/// execution unit requirement supported by the subtarget.<br>
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {<br>
- return AMDGPU::IsaInfo::getMaxNumSGPRs(MCSubtargetInfo::getFeatureBits(),<br>
- WavesPerEU, Addressable);<br>
+ return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable);<br>
}<br>
<br>
/// \returns Reserved number of SGPRs for given function \p MF.<br>
@@ -903,39 +883,34 @@ public:<br>
<br>
/// \returns VGPR allocation granularity supported by the subtarget.<br>
unsigned getVGPRAllocGranule() const {<br>
- return AMDGPU::IsaInfo::getVGPRAllocGranule(<br>
- MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getVGPRAllocGranule(this);<br>
}<br>
<br>
/// \returns VGPR encoding granularity supported by the subtarget.<br>
unsigned getVGPREncodingGranule() const {<br>
- return AMDGPU::IsaInfo::getVGPREncodingGranule(<br>
- MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getVGPREncodingGranule(this);<br>
}<br>
<br>
/// \returns Total number of VGPRs supported by the subtarget.<br>
unsigned getTotalNumVGPRs() const {<br>
- return AMDGPU::IsaInfo::getTotalNumVGPRs(MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getTotalNumVGPRs(this);<br>
}<br>
<br>
/// \returns Addressable number of VGPRs supported by the subtarget.<br>
unsigned getAddressableNumVGPRs() const {<br>
- return AMDGPU::IsaInfo::getAddressableNumVGPRs(<br>
- MCSubtargetInfo::getFeatureBits());<br>
+ return AMDGPU::IsaInfo::getAddressableNumVGPRs(this);<br>
}<br>
<br>
/// \returns Minimum number of VGPRs that meets given number of waves per<br>
/// execution unit requirement supported by the subtarget.<br>
unsigned getMinNumVGPRs(unsigned WavesPerEU) const {<br>
- return AMDGPU::IsaInfo::getMinNumVGPRs(MCSubtargetInfo::getFeatureBits(),<br>
- WavesPerEU);<br>
+ return AMDGPU::IsaInfo::getMinNumVGPRs(this, WavesPerEU);<br>
}<br>
<br>
/// \returns Maximum number of VGPRs that meets given number of waves per<br>
/// execution unit requirement supported by the subtarget.<br>
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {<br>
- return AMDGPU::IsaInfo::getMaxNumVGPRs(MCSubtargetInfo::getFeatureBits(),<br>
- WavesPerEU);<br>
+ return AMDGPU::IsaInfo::getMaxNumVGPRs(this, WavesPerEU);<br>
}<br>
<br>
/// \returns Maximum number of VGPRs that meets number of waves per execution<br>
@@ -951,6 +926,34 @@ public:<br>
void getPostRAMutations(<br>
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)<br>
const override;<br>
+<br>
+ /// \returns Maximum number of work groups per compute unit supported by the<br>
+ /// subtarget and limited by given \p FlatWorkGroupSize.<br>
+ unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {<br>
+ return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);<br>
+ }<br>
+<br>
+ /// \returns Minimum flat work group size supported by the subtarget.<br>
+ unsigned getMinFlatWorkGroupSize() const override {<br>
+ return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);<br>
+ }<br>
+<br>
+ /// \returns Maximum flat work group size supported by the subtarget.<br>
+ unsigned getMaxFlatWorkGroupSize() const override {<br>
+ return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);<br>
+ }<br>
+<br>
+ /// \returns Maximum number of waves per execution unit supported by the<br>
+ /// subtarget and limited by given \p FlatWorkGroupSize.<br>
+ unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const override {<br>
+ return AMDGPU::IsaInfo::getMaxWavesPerEU(this, FlatWorkGroupSize);<br>
+ }<br>
+<br>
+ /// \returns Minimum number of waves per execution unit supported by the<br>
+ /// subtarget.<br>
+ unsigned getMinWavesPerEU() const override {<br>
+ return AMDGPU::IsaInfo::getMinWavesPerEU(this);<br>
+ }<br>
};<br>
<br>
class R600Subtarget final : public R600GenSubtargetInfo,<br>
@@ -1061,6 +1064,34 @@ public:<br>
bool enableSubRegLiveness() const override {<br>
return true;<br>
}<br>
+<br>
+ /// \returns Maximum number of work groups per compute unit supported by the<br>
+ /// subtarget and limited by given \p FlatWorkGroupSize.<br>
+ unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {<br>
+ return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);<br>
+ }<br>
+<br>
+ /// \returns Minimum flat work group size supported by the subtarget.<br>
+ unsigned getMinFlatWorkGroupSize() const override {<br>
+ return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);<br>
+ }<br>
+<br>
+ /// \returns Maximum flat work group size supported by the subtarget.<br>
+ unsigned getMaxFlatWorkGroupSize() const override {<br>
+ return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);<br>
+ }<br>
+<br>
+ /// \returns Maximum number of waves per execution unit supported by the<br>
+ /// subtarget and limited by given \p FlatWorkGroupSize.<br>
+ unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const override {<br>
+ return AMDGPU::IsaInfo::getMaxWavesPerEU(this, FlatWorkGroupSize);<br>
+ }<br>
+<br>
+ /// \returns Minimum number of waves per execution unit supported by the<br>
+ /// subtarget.<br>
+ unsigned getMinWavesPerEU() const override {<br>
+ return AMDGPU::IsaInfo::getMinWavesPerEU(this);<br>
+ }<br>
};<br>
<br>
} // end namespace llvm<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Tue Sep 11 11:56:51 2018<br>
@@ -49,6 +49,7 @@<br>
#include "llvm/Support/MachineValueType.h"<br>
#include "llvm/Support/MathExtras.h"<br>
#include "llvm/Support/SMLoc.h"<br>
+#include "llvm/Support/TargetParser.h"<br>
#include "llvm/Support/TargetRegistry.h"<br>
#include "llvm/Support/raw_ostream.h"<br>
#include <algorithm><br>
@@ -917,8 +918,7 @@ public:<br>
// Currently there is none suitable machinery in the core llvm-mc for this.<br>
// MCSymbol::isRedefinable is intended for another purpose, and<br>
// AsmParser::parseDirectiveSet() cannot be specialized for specific target.<br>
- AMDGPU::IsaInfo::IsaVersion ISA =<br>
- AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());<br>
+ AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());<br>
MCContext &Ctx = getContext();<br>
if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {<br>
MCSymbol *Sym =<br>
@@ -1826,7 +1826,7 @@ bool AMDGPUAsmParser::updateGprCountSymb<br>
unsigned DwordRegIndex,<br>
unsigned RegWidth) {<br>
// Symbols are only defined for GCN targets<br>
- if (AMDGPU::IsaInfo::getIsaVersion(getFeatureBits()).Major < 6)<br>
+ if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)<br>
return true;<br>
<br>
auto SymbolName = getGprCountSymbolName(RegKind);<br>
@@ -2637,18 +2637,18 @@ bool AMDGPUAsmParser::calculateGPRBlocks<br>
unsigned &SGPRBlocks) {<br>
// TODO(scott.linder): These calculations are duplicated from<br>
// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.<br>
- IsaInfo::IsaVersion Version = IsaInfo::getIsaVersion(Features);<br>
+ IsaVersion Version = getIsaVersion(getSTI().getCPU());<br>
<br>
unsigned NumVGPRs = NextFreeVGPR;<br>
unsigned NumSGPRs = NextFreeSGPR;<br>
- unsigned MaxAddressableNumSGPRs = IsaInfo::getAddressableNumSGPRs(Features);<br>
+ unsigned MaxAddressableNumSGPRs = IsaInfo::getAddressableNumSGPRs(&getSTI());<br>
<br>
if (Version.Major >= 8 && !Features.test(FeatureSGPRInitBug) &&<br>
NumSGPRs > MaxAddressableNumSGPRs)<br>
return OutOfRangeError(SGPRRange);<br>
<br>
NumSGPRs +=<br>
- IsaInfo::getNumExtraSGPRs(Features, VCCUsed, FlatScrUsed, XNACKUsed);<br>
+ IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);<br>
<br>
if ((Version.Major <= 7 || Features.test(FeatureSGPRInitBug)) &&<br>
NumSGPRs > MaxAddressableNumSGPRs)<br>
@@ -2657,8 +2657,8 @@ bool AMDGPUAsmParser::calculateGPRBlocks<br>
if (Features.test(FeatureSGPRInitBug))<br>
NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;<br>
<br>
- VGPRBlocks = IsaInfo::getNumVGPRBlocks(Features, NumVGPRs);<br>
- SGPRBlocks = IsaInfo::getNumSGPRBlocks(Features, NumSGPRs);<br>
+ VGPRBlocks = IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs);<br>
+ SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);<br>
<br>
return false;<br>
}<br>
@@ -2678,8 +2678,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDH<br>
<br>
StringSet<> Seen;<br>
<br>
- IsaInfo::IsaVersion IVersion =<br>
- IsaInfo::getIsaVersion(getSTI().getFeatureBits());<br>
+ IsaVersion IVersion = getIsaVersion(getSTI().getCPU());<br>
<br>
SMRange VGPRRange;<br>
uint64_t NextFreeVGPR = 0;<br>
@@ -2938,8 +2937,7 @@ bool AMDGPUAsmParser::ParseDirectiveHSAC<br>
// If this directive has no arguments, then use the ISA version for the<br>
// targeted GPU.<br>
if (getLexer().is(AsmToken::EndOfStatement)) {<br>
- AMDGPU::IsaInfo::IsaVersion ISA =<br>
- AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());<br>
+ AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());<br>
getTargetStreamer().EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor,<br>
ISA.Stepping,<br>
"AMD", "AMDGPU");<br>
@@ -3001,7 +2999,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCode<br>
<br>
bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {<br>
amd_kernel_code_t Header;<br>
- AMDGPU::initDefaultAMDKernelCodeT(Header, getFeatureBits());<br>
+ AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());<br>
<br>
while (true) {<br>
// Lex EndOfStatement. This is in a while loop, because lexing a comment<br>
@@ -3679,12 +3677,12 @@ void AMDGPUAsmParser::cvtExp(MCInst &Ins<br>
<br>
static bool<br>
encodeCnt(<br>
- const AMDGPU::IsaInfo::IsaVersion ISA,<br>
+ const AMDGPU::IsaVersion ISA,<br>
int64_t &IntVal,<br>
int64_t CntVal,<br>
bool Saturate,<br>
- unsigned (*encode)(const IsaInfo::IsaVersion &Version, unsigned, unsigned),<br>
- unsigned (*decode)(const IsaInfo::IsaVersion &Version, unsigned))<br>
+ unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned),<br>
+ unsigned (*decode)(const IsaVersion &Version, unsigned))<br>
{<br>
bool Failed = false;<br>
<br>
@@ -3715,8 +3713,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &<br>
if (getParser().parseAbsoluteExpression(CntVal))<br>
return true;<br>
<br>
- AMDGPU::IsaInfo::IsaVersion ISA =<br>
- AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());<br>
+ AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());<br>
<br>
bool Failed = true;<br>
bool Sat = CntName.endswith("_sat");<br>
@@ -3751,8 +3748,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &<br>
<br>
OperandMatchResultTy<br>
AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {<br>
- AMDGPU::IsaInfo::IsaVersion ISA =<br>
- AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());<br>
+ AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());<br>
int64_t Waitcnt = getWaitcntBitMask(ISA);<br>
SMLoc S = Parser.getTok().getLoc();<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Tue Sep 11 11:56:51 2018<br>
@@ -1155,8 +1155,7 @@ void AMDGPUInstPrinter::printSwizzle(con<br>
void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,<br>
const MCSubtargetInfo &STI,<br>
raw_ostream &O) {<br>
- AMDGPU::IsaInfo::IsaVersion ISA =<br>
- AMDGPU::IsaInfo::getIsaVersion(STI.getFeatureBits());<br>
+ AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());<br>
<br>
unsigned SImm16 = MI->getOperand(OpNo).getImm();<br>
unsigned Vmcnt, Expcnt, Lgkmcnt;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp Tue Sep 11 11:56:51 2018<br>
@@ -27,6 +27,7 @@<br>
#include "llvm/MC/MCObjectFileInfo.h"<br>
#include "llvm/MC/MCSectionELF.h"<br>
#include "llvm/Support/FormattedStream.h"<br>
+#include "llvm/Support/TargetParser.h"<br>
<br>
namespace llvm {<br>
#include "AMDGPUPTNote.h"<br>
@@ -39,84 +40,6 @@ using namespace llvm::AMDGPU;<br>
// AMDGPUTargetStreamer<br>
//===----------------------------------------------------------------------===//<br>
<br>
-static const struct {<br>
- const char *Name;<br>
- unsigned Mach;<br>
-} MachTable[] = {<br>
- // Radeon HD 2000/3000 Series (R600).<br>
- { "r600", ELF::EF_AMDGPU_MACH_R600_R600 },<br>
- { "r630", ELF::EF_AMDGPU_MACH_R600_R630 },<br>
- { "rs880", ELF::EF_AMDGPU_MACH_R600_RS880 },<br>
- { "rv670", ELF::EF_AMDGPU_MACH_R600_RV670 },<br>
- // Radeon HD 4000 Series (R700).<br>
- { "rv710", ELF::EF_AMDGPU_MACH_R600_RV710 },<br>
- { "rv730", ELF::EF_AMDGPU_MACH_R600_RV730 },<br>
- { "rv770", ELF::EF_AMDGPU_MACH_R600_RV770 },<br>
- // Radeon HD 5000 Series (Evergreen).<br>
- { "cedar", ELF::EF_AMDGPU_MACH_R600_CEDAR },<br>
- { "cypress", ELF::EF_AMDGPU_MACH_R600_CYPRESS },<br>
- { "juniper", ELF::EF_AMDGPU_MACH_R600_JUNIPER },<br>
- { "redwood", ELF::EF_AMDGPU_MACH_R600_REDWOOD },<br>
- { "sumo", ELF::EF_AMDGPU_MACH_R600_SUMO },<br>
- // Radeon HD 6000 Series (Northern Islands).<br>
- { "barts", ELF::EF_AMDGPU_MACH_R600_BARTS },<br>
- { "caicos", ELF::EF_AMDGPU_MACH_R600_CAICOS },<br>
- { "cayman", ELF::EF_AMDGPU_MACH_R600_CAYMAN },<br>
- { "turks", ELF::EF_AMDGPU_MACH_R600_TURKS },<br>
- // AMDGCN GFX6.<br>
- { "gfx600", ELF::EF_AMDGPU_MACH_AMDGCN_GFX600 },<br>
- { "tahiti", ELF::EF_AMDGPU_MACH_AMDGCN_GFX600 },<br>
- { "gfx601", ELF::EF_AMDGPU_MACH_AMDGCN_GFX601 },<br>
- { "hainan", ELF::EF_AMDGPU_MACH_AMDGCN_GFX601 },<br>
- { "oland", ELF::EF_AMDGPU_MACH_AMDGCN_GFX601 },<br>
- { "pitcairn", ELF::EF_AMDGPU_MACH_AMDGCN_GFX601 },<br>
- { "verde", ELF::EF_AMDGPU_MACH_AMDGCN_GFX601 },<br>
- // AMDGCN GFX7.<br>
- { "gfx700", ELF::EF_AMDGPU_MACH_AMDGCN_GFX700 },<br>
- { "kaveri", ELF::EF_AMDGPU_MACH_AMDGCN_GFX700 },<br>
- { "gfx701", ELF::EF_AMDGPU_MACH_AMDGCN_GFX701 },<br>
- { "hawaii", ELF::EF_AMDGPU_MACH_AMDGCN_GFX701 },<br>
- { "gfx702", ELF::EF_AMDGPU_MACH_AMDGCN_GFX702 },<br>
- { "gfx703", ELF::EF_AMDGPU_MACH_AMDGCN_GFX703 },<br>
- { "kabini", ELF::EF_AMDGPU_MACH_AMDGCN_GFX703 },<br>
- { "mullins", ELF::EF_AMDGPU_MACH_AMDGCN_GFX703 },<br>
- { "gfx704", ELF::EF_AMDGPU_MACH_AMDGCN_GFX704 },<br>
- { "bonaire", ELF::EF_AMDGPU_MACH_AMDGCN_GFX704 },<br>
- // AMDGCN GFX8.<br>
- { "gfx801", ELF::EF_AMDGPU_MACH_AMDGCN_GFX801 },<br>
- { "carrizo", ELF::EF_AMDGPU_MACH_AMDGCN_GFX801 },<br>
- { "gfx802", ELF::EF_AMDGPU_MACH_AMDGCN_GFX802 },<br>
- { "iceland", ELF::EF_AMDGPU_MACH_AMDGCN_GFX802 },<br>
- { "tonga", ELF::EF_AMDGPU_MACH_AMDGCN_GFX802 },<br>
- { "gfx803", ELF::EF_AMDGPU_MACH_AMDGCN_GFX803 },<br>
- { "fiji", ELF::EF_AMDGPU_MACH_AMDGCN_GFX803 },<br>
- { "polaris10", ELF::EF_AMDGPU_MACH_AMDGCN_GFX803 },<br>
- { "polaris11", ELF::EF_AMDGPU_MACH_AMDGCN_GFX803 },<br>
- { "gfx810", ELF::EF_AMDGPU_MACH_AMDGCN_GFX810 },<br>
- { "stoney", ELF::EF_AMDGPU_MACH_AMDGCN_GFX810 },<br>
- // AMDGCN GFX9.<br>
- { "gfx900", ELF::EF_AMDGPU_MACH_AMDGCN_GFX900 },<br>
- { "gfx902", ELF::EF_AMDGPU_MACH_AMDGCN_GFX902 },<br>
- { "gfx904", ELF::EF_AMDGPU_MACH_AMDGCN_GFX904 },<br>
- { "gfx906", ELF::EF_AMDGPU_MACH_AMDGCN_GFX906 },<br>
- // Not specified processor.<br>
- { nullptr, ELF::EF_AMDGPU_MACH_NONE }<br>
-};<br>
-<br>
-unsigned AMDGPUTargetStreamer::getMACH(StringRef GPU) const {<br>
- auto Entry = MachTable;<br>
- for (; Entry->Name && GPU != Entry->Name; ++Entry)<br>
- ;<br>
- return Entry->Mach;<br>
-}<br>
-<br>
-const char *AMDGPUTargetStreamer::getMachName(unsigned Mach) {<br>
- auto Entry = MachTable;<br>
- for (; Entry->Name && Mach != Entry->Mach; ++Entry)<br>
- ;<br>
- return Entry->Name;<br>
-}<br>
-<br>
bool AMDGPUTargetStreamer::EmitHSAMetadata(StringRef HSAMetadataString) {<br>
HSAMD::Metadata HSAMetadata;<br>
if (HSAMD::fromString(HSAMetadataString, HSAMetadata))<br>
@@ -205,7 +128,7 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsa<br>
bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {<br>
amdhsa::kernel_descriptor_t DefaultKD = getDefaultAmdhsaKernelDescriptor();<br>
<br>
- IsaInfo::IsaVersion IVersion = IsaInfo::getIsaVersion(STI.getFeatureBits());<br>
+ IsaVersion IVersion = getIsaVersion(STI.getCPU());<br>
<br>
OS << "\t.amdhsa_kernel " << KernelName << '\n';<br>
<br>
@@ -342,7 +265,7 @@ AMDGPUTargetELFStreamer::AMDGPUTargetELF<br>
unsigned EFlags = MCA.getELFHeaderEFlags();<br>
<br>
EFlags &= ~ELF::EF_AMDGPU_MACH;<br>
- EFlags |= getMACH(STI.getCPU());<br>
+ EFlags |= getElfMach(STI.getCPU());<br>
<br>
EFlags &= ~ELF::EF_AMDGPU_XNACK;<br>
if (AMDGPU::hasXNACK(STI))<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h Tue Sep 11 11:56:51 2018<br>
@@ -31,13 +31,7 @@ class AMDGPUTargetStreamer : public MCTa<br>
protected:<br>
MCContext &getContext() const { return Streamer.getContext(); }<br>
<br>
- /// \returns Equivalent EF_AMDGPU_MACH_* value for given \p GPU name.<br>
- unsigned getMACH(StringRef GPU) const;<br>
-<br>
public:<br>
- /// \returns Equivalent GPU name for an EF_AMDGPU_MACH_* value.<br>
- static const char *getMachName(unsigned Mach);<br>
-<br>
AMDGPUTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}<br>
<br>
virtual void EmitDirectiveAMDGCNTarget(StringRef Target) = 0;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp Tue Sep 11 11:56:51 2018<br>
@@ -369,7 +369,7 @@ private:<br>
const SIRegisterInfo *TRI = nullptr;<br>
const MachineRegisterInfo *MRI = nullptr;<br>
const MachineLoopInfo *MLI = nullptr;<br>
- AMDGPU::IsaInfo::IsaVersion IV;<br>
+ AMDGPU::IsaVersion IV;<br>
<br>
DenseSet<MachineBasicBlock *> BlockVisitedSet;<br>
DenseSet<MachineInstr *> TrackedWaitcntSet;<br>
@@ -1841,7 +1841,7 @@ bool SIInsertWaitcnts::runOnMachineFunct<br>
TRI = &TII->getRegisterInfo();<br>
MRI = &MF.getRegInfo();<br>
MLI = &getAnalysis<MachineLoopInfo>();<br>
- IV = AMDGPU::IsaInfo::getIsaVersion(ST->getFeatureBits());<br>
+ IV = AMDGPU::getIsaVersion(ST->getCPU());<br>
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();<br>
<br>
ForceEmitZeroWaitcnts = ForceEmitZeroFlag;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp Tue Sep 11 11:56:51 2018<br>
@@ -253,7 +253,7 @@ protected:<br>
/// Instruction info.<br>
const SIInstrInfo *TII = nullptr;<br>
<br>
- IsaInfo::IsaVersion IV;<br>
+ IsaVersion IV;<br>
<br>
SICacheControl(const GCNSubtarget &ST);<br>
<br>
@@ -605,7 +605,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::get<br>
<br>
SICacheControl::SICacheControl(const GCNSubtarget &ST) {<br>
TII = ST.getInstrInfo();<br>
- IV = IsaInfo::getIsaVersion(ST.getFeatureBits());<br>
+ IV = getIsaVersion(ST.getCPU());<br>
}<br>
<br>
/* static */<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Tue Sep 11 11:56:51 2018<br>
@@ -137,68 +137,18 @@ int getMCOpcode(uint16_t Opcode, unsigne<br>
<br>
namespace IsaInfo {<br>
<br>
-IsaVersion getIsaVersion(const FeatureBitset &Features) {<br>
- // GCN GFX6 (Southern Islands (SI)).<br>
- if (Features.test(FeatureISAVersion6_0_0))<br>
- return {6, 0, 0};<br>
- if (Features.test(FeatureISAVersion6_0_1))<br>
- return {6, 0, 1};<br>
-<br>
- // GCN GFX7 (Sea Islands (CI)).<br>
- if (Features.test(FeatureISAVersion7_0_0))<br>
- return {7, 0, 0};<br>
- if (Features.test(FeatureISAVersion7_0_1))<br>
- return {7, 0, 1};<br>
- if (Features.test(FeatureISAVersion7_0_2))<br>
- return {7, 0, 2};<br>
- if (Features.test(FeatureISAVersion7_0_3))<br>
- return {7, 0, 3};<br>
- if (Features.test(FeatureISAVersion7_0_4))<br>
- return {7, 0, 4};<br>
- if (Features.test(FeatureSeaIslands))<br>
- return {7, 0, 0};<br>
-<br>
- // GCN GFX8 (Volcanic Islands (VI)).<br>
- if (Features.test(FeatureISAVersion8_0_1))<br>
- return {8, 0, 1};<br>
- if (Features.test(FeatureISAVersion8_0_2))<br>
- return {8, 0, 2};<br>
- if (Features.test(FeatureISAVersion8_0_3))<br>
- return {8, 0, 3};<br>
- if (Features.test(FeatureISAVersion8_1_0))<br>
- return {8, 1, 0};<br>
- if (Features.test(FeatureVolcanicIslands))<br>
- return {8, 0, 0};<br>
-<br>
- // GCN GFX9.<br>
- if (Features.test(FeatureISAVersion9_0_0))<br>
- return {9, 0, 0};<br>
- if (Features.test(FeatureISAVersion9_0_2))<br>
- return {9, 0, 2};<br>
- if (Features.test(FeatureISAVersion9_0_4))<br>
- return {9, 0, 4};<br>
- if (Features.test(FeatureISAVersion9_0_6))<br>
- return {9, 0, 6};<br>
- if (Features.test(FeatureGFX9))<br>
- return {9, 0, 0};<br>
-<br>
- if (Features.test(FeatureSouthernIslands))<br>
- return {0, 0, 0};<br>
- return {7, 0, 0};<br>
-}<br>
-<br>
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {<br>
auto TargetTriple = STI->getTargetTriple();<br>
- auto ISAVersion = IsaInfo::getIsaVersion(STI->getFeatureBits());<br>
+ auto Version = getIsaVersion(STI->getCPU());<br>
<br>
Stream << TargetTriple.getArchName() << '-'<br>
<< TargetTriple.getVendorName() << '-'<br>
<< TargetTriple.getOSName() << '-'<br>
<< TargetTriple.getEnvironmentName() << '-'<br>
<< "gfx"<br>
- << ISAVersion.Major<br>
- << ISAVersion.Minor<br>
- << ISAVersion.Stepping;<br>
+ << Version.Major<br>
+ << Version.Minor<br>
+ << Version.Stepping;<br>
<br>
if (hasXNACK(*STI))<br>
Stream << "+xnack";<br>
@@ -210,49 +160,49 @@ bool hasCodeObjectV3(const MCSubtargetIn<br>
return STI->getFeatureBits().test(FeatureCodeObjectV3);<br>
}<br>
<br>
-unsigned getWavefrontSize(const FeatureBitset &Features) {<br>
- if (Features.test(FeatureWavefrontSize16))<br>
+unsigned getWavefrontSize(const MCSubtargetInfo *STI) {<br>
+ if (STI->getFeatureBits().test(FeatureWavefrontSize16))<br>
return 16;<br>
- if (Features.test(FeatureWavefrontSize32))<br>
+ if (STI->getFeatureBits().test(FeatureWavefrontSize32))<br>
return 32;<br>
<br>
return 64;<br>
}<br>
<br>
-unsigned getLocalMemorySize(const FeatureBitset &Features) {<br>
- if (Features.test(FeatureLocalMemorySize32768))<br>
+unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {<br>
+ if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))<br>
return 32768;<br>
- if (Features.test(FeatureLocalMemorySize65536))<br>
+ if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))<br>
return 65536;<br>
<br>
return 0;<br>
}<br>
<br>
-unsigned getEUsPerCU(const FeatureBitset &Features) {<br>
+unsigned getEUsPerCU(const MCSubtargetInfo *STI) {<br>
return 4;<br>
}<br>
<br>
-unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,<br>
+unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize) {<br>
- if (!Features.test(FeatureGCN))<br>
+ if (!STI->getFeatureBits().test(FeatureGCN))<br>
return 8;<br>
- unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);<br>
+ unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);<br>
if (N == 1)<br>
return 40;<br>
N = 40 / N;<br>
return std::min(N, 16u);<br>
}<br>
<br>
-unsigned getMaxWavesPerCU(const FeatureBitset &Features) {<br>
- return getMaxWavesPerEU() * getEUsPerCU(Features);<br>
+unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI) {<br>
+ return getMaxWavesPerEU() * getEUsPerCU(STI);<br>
}<br>
<br>
-unsigned getMaxWavesPerCU(const FeatureBitset &Features,<br>
+unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize) {<br>
- return getWavesPerWorkGroup(Features, FlatWorkGroupSize);<br>
+ return getWavesPerWorkGroup(STI, FlatWorkGroupSize);<br>
}<br>
<br>
-unsigned getMinWavesPerEU(const FeatureBitset &Features) {<br>
+unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {<br>
return 1;<br>
}<br>
<br>
@@ -261,89 +211,89 @@ unsigned getMaxWavesPerEU() {<br>
return 10;<br>
}<br>
<br>
-unsigned getMaxWavesPerEU(const FeatureBitset &Features,<br>
+unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize) {<br>
- return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),<br>
- getEUsPerCU(Features)) / getEUsPerCU(Features);<br>
+ return alignTo(getMaxWavesPerCU(STI, FlatWorkGroupSize),<br>
+ getEUsPerCU(STI)) / getEUsPerCU(STI);<br>
}<br>
<br>
-unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {<br>
+unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) {<br>
return 1;<br>
}<br>
<br>
-unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {<br>
+unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) {<br>
return 2048;<br>
}<br>
<br>
-unsigned getWavesPerWorkGroup(const FeatureBitset &Features,<br>
+unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize) {<br>
- return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /<br>
- getWavefrontSize(Features);<br>
+ return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) /<br>
+ getWavefrontSize(STI);<br>
}<br>
<br>
-unsigned getSGPRAllocGranule(const FeatureBitset &Features) {<br>
- IsaVersion Version = getIsaVersion(Features);<br>
+unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {<br>
+ IsaVersion Version = getIsaVersion(STI->getCPU());<br>
if (Version.Major >= 8)<br>
return 16;<br>
return 8;<br>
}<br>
<br>
-unsigned getSGPREncodingGranule(const FeatureBitset &Features) {<br>
+unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI) {<br>
return 8;<br>
}<br>
<br>
-unsigned getTotalNumSGPRs(const FeatureBitset &Features) {<br>
- IsaVersion Version = getIsaVersion(Features);<br>
+unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {<br>
+ IsaVersion Version = getIsaVersion(STI->getCPU());<br>
if (Version.Major >= 8)<br>
return 800;<br>
return 512;<br>
}<br>
<br>
-unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {<br>
- if (Features.test(FeatureSGPRInitBug))<br>
+unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI) {<br>
+ if (STI->getFeatureBits().test(FeatureSGPRInitBug))<br>
return FIXED_NUM_SGPRS_FOR_INIT_BUG;<br>
<br>
- IsaVersion Version = getIsaVersion(Features);<br>
+ IsaVersion Version = getIsaVersion(STI->getCPU());<br>
if (Version.Major >= 8)<br>
return 102;<br>
return 104;<br>
}<br>
<br>
-unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {<br>
+unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {<br>
assert(WavesPerEU != 0);<br>
<br>
if (WavesPerEU >= getMaxWavesPerEU())<br>
return 0;<br>
<br>
- unsigned MinNumSGPRs = getTotalNumSGPRs(Features) / (WavesPerEU + 1);<br>
- if (Features.test(FeatureTrapHandler))<br>
+ unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);<br>
+ if (STI->getFeatureBits().test(FeatureTrapHandler))<br>
MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);<br>
- MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(Features)) + 1;<br>
- return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));<br>
+ MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;<br>
+ return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));<br>
}<br>
<br>
-unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,<br>
+unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,<br>
bool Addressable) {<br>
assert(WavesPerEU != 0);<br>
<br>
- IsaVersion Version = getIsaVersion(Features);<br>
- unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);<br>
+ IsaVersion Version = getIsaVersion(STI->getCPU());<br>
+ unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);<br>
if (Version.Major >= 8 && !Addressable)<br>
AddressableNumSGPRs = 112;<br>
- unsigned MaxNumSGPRs = getTotalNumSGPRs(Features) / WavesPerEU;<br>
- if (Features.test(FeatureTrapHandler))<br>
+ unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;<br>
+ if (STI->getFeatureBits().test(FeatureTrapHandler))<br>
MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);<br>
- MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(Features));<br>
+ MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));<br>
return std::min(MaxNumSGPRs, AddressableNumSGPRs);<br>
}<br>
<br>
-unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed,<br>
+unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,<br>
bool FlatScrUsed, bool XNACKUsed) {<br>
unsigned ExtraSGPRs = 0;<br>
if (VCCUsed)<br>
ExtraSGPRs = 2;<br>
<br>
- IsaVersion Version = getIsaVersion(Features);<br>
+ IsaVersion Version = getIsaVersion(STI->getCPU());<br>
if (Version.Major < 8) {<br>
if (FlatScrUsed)<br>
ExtraSGPRs = 4;<br>
@@ -358,74 +308,74 @@ unsigned getNumExtraSGPRs(const FeatureB<br>
return ExtraSGPRs;<br>
}<br>
<br>
-unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed,<br>
+unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,<br>
bool FlatScrUsed) {<br>
- return getNumExtraSGPRs(Features, VCCUsed, FlatScrUsed,<br>
- Features[AMDGPU::FeatureXNACK]);<br>
+ return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,<br>
+ STI->getFeatureBits().test(AMDGPU::FeatureXNACK));<br>
}<br>
<br>
-unsigned getNumSGPRBlocks(const FeatureBitset &Features, unsigned NumSGPRs) {<br>
- NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(Features));<br>
+unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {<br>
+ NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(STI));<br>
// SGPRBlocks is actual number of SGPR blocks minus 1.<br>
- return NumSGPRs / getSGPREncodingGranule(Features) - 1;<br>
+ return NumSGPRs / getSGPREncodingGranule(STI) - 1;<br>
}<br>
<br>
-unsigned getVGPRAllocGranule(const FeatureBitset &Features) {<br>
+unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI) {<br>
return 4;<br>
}<br>
<br>
-unsigned getVGPREncodingGranule(const FeatureBitset &Features) {<br>
- return getVGPRAllocGranule(Features);<br>
+unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI) {<br>
+ return getVGPRAllocGranule(STI);<br>
}<br>
<br>
-unsigned getTotalNumVGPRs(const FeatureBitset &Features) {<br>
+unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {<br>
return 256;<br>
}<br>
<br>
-unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {<br>
- return getTotalNumVGPRs(Features);<br>
+unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) {<br>
+ return getTotalNumVGPRs(STI);<br>
}<br>
<br>
-unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {<br>
+unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {<br>
assert(WavesPerEU != 0);<br>
<br>
if (WavesPerEU >= getMaxWavesPerEU())<br>
return 0;<br>
unsigned MinNumVGPRs =<br>
- alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),<br>
- getVGPRAllocGranule(Features)) + 1;<br>
- return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));<br>
+ alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),<br>
+ getVGPRAllocGranule(STI)) + 1;<br>
+ return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));<br>
}<br>
<br>
-unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {<br>
+unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {<br>
assert(WavesPerEU != 0);<br>
<br>
- unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,<br>
- getVGPRAllocGranule(Features));<br>
- unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);<br>
+ unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,<br>
+ getVGPRAllocGranule(STI));<br>
+ unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);<br>
return std::min(MaxNumVGPRs, AddressableNumVGPRs);<br>
}<br>
<br>
-unsigned getNumVGPRBlocks(const FeatureBitset &Features, unsigned NumVGPRs) {<br>
- NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(Features));<br>
+unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs) {<br>
+ NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(STI));<br>
// VGPRBlocks is actual number of VGPR blocks minus 1.<br>
- return NumVGPRs / getVGPREncodingGranule(Features) - 1;<br>
+ return NumVGPRs / getVGPREncodingGranule(STI) - 1;<br>
}<br>
<br>
} // end namespace IsaInfo<br>
<br>
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,<br>
- const FeatureBitset &Features) {<br>
- IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);<br>
+ const MCSubtargetInfo *STI) {<br>
+ IsaVersion Version = getIsaVersion(STI->getCPU());<br>
<br>
memset(&Header, 0, sizeof(Header));<br>
<br>
Header.amd_kernel_code_version_major = 1;<br>
Header.amd_kernel_code_version_minor = 2;<br>
Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU<br>
- Header.amd_machine_version_major = ISA.Major;<br>
- Header.amd_machine_version_minor = ISA.Minor;<br>
- Header.amd_machine_version_stepping = ISA.Stepping;<br>
+ Header.amd_machine_version_major = Version.Major;<br>
+ Header.amd_machine_version_minor = Version.Minor;<br>
+ Header.amd_machine_version_stepping = Version.Stepping;<br>
Header.kernel_code_entry_byte_offset = sizeof(Header);<br>
// wavefront_size is specified as a power of 2: 2^6 = 64 threads.<br>
Header.wavefront_size = 6;<br>
@@ -513,7 +463,7 @@ std::pair<int, int> getIntegerPairAttrib<br>
return Ints;<br>
}<br>
<br>
-unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {<br>
+unsigned getVmcntBitMask(const IsaVersion &Version) {<br>
unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;<br>
if (Version.Major < 9)<br>
return VmcntLo;<br>
@@ -522,15 +472,15 @@ unsigned getVmcntBitMask(const IsaInfo::<br>
return VmcntLo | VmcntHi;<br>
}<br>
<br>
-unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {<br>
+unsigned getExpcntBitMask(const IsaVersion &Version) {<br>
return (1 << getExpcntBitWidth()) - 1;<br>
}<br>
<br>
-unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {<br>
+unsigned getLgkmcntBitMask(const IsaVersion &Version) {<br>
return (1 << getLgkmcntBitWidth()) - 1;<br>
}<br>
<br>
-unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {<br>
+unsigned getWaitcntBitMask(const IsaVersion &Version) {<br>
unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());<br>
unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());<br>
unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());<br>
@@ -542,7 +492,7 @@ unsigned getWaitcntBitMask(const IsaInfo<br>
return Waitcnt | VmcntHi;<br>
}<br>
<br>
-unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {<br>
+unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {<br>
unsigned VmcntLo =<br>
unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());<br>
if (Version.Major < 9)<br>
@@ -554,22 +504,22 @@ unsigned decodeVmcnt(const IsaInfo::IsaV<br>
return VmcntLo | VmcntHi;<br>
}<br>
<br>
-unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {<br>
+unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {<br>
return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());<br>
}<br>
<br>
-unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {<br>
+unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {<br>
return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());<br>
}<br>
<br>
-void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,<br>
+void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,<br>
unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {<br>
Vmcnt = decodeVmcnt(Version, Waitcnt);<br>
Expcnt = decodeExpcnt(Version, Waitcnt);<br>
Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);<br>
}<br>
<br>
-unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,<br>
+unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,<br>
unsigned Vmcnt) {<br>
Waitcnt =<br>
packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());<br>
@@ -580,17 +530,17 @@ unsigned encodeVmcnt(const IsaInfo::IsaV<br>
return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());<br>
}<br>
<br>
-unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,<br>
+unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,<br>
unsigned Expcnt) {<br>
return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());<br>
}<br>
<br>
-unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,<br>
+unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,<br>
unsigned Lgkmcnt) {<br>
return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());<br>
}<br>
<br>
-unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,<br>
+unsigned encodeWaitcnt(const IsaVersion &Version,<br>
unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {<br>
unsigned Waitcnt = getWaitcntBitMask(Version);<br>
Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=341982&r1=341981&r2=341982&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=341982&r1=341981&r2=341982&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Tue Sep 11 11:56:51 2018<br>
@@ -19,6 +19,7 @@<br>
#include "llvm/Support/AMDHSAKernelDescriptor.h"<br>
#include "llvm/Support/Compiler.h"<br>
#include "llvm/Support/ErrorHandling.h"<br>
+#include "llvm/Support/TargetParser.h"<br>
#include <cstdint><br>
#include <string><br>
#include <utility><br>
@@ -56,16 +57,6 @@ enum {<br>
TRAP_NUM_SGPRS = 16<br>
};<br>
<br>
-/// Instruction set architecture version.<br>
-struct IsaVersion {<br>
- unsigned Major;<br>
- unsigned Minor;<br>
- unsigned Stepping;<br>
-};<br>
-<br>
-/// \returns Isa version for given subtarget \p Features.<br>
-IsaVersion getIsaVersion(const FeatureBitset &Features);<br>
-<br>
/// Streams isa version string for given subtarget \p STI into \p Stream.<br>
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);<br>
<br>
@@ -73,114 +64,114 @@ void streamIsaVersion(const MCSubtargetI<br>
/// false otherwise.<br>
bool hasCodeObjectV3(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Wavefront size for given subtarget \p Features.<br>
-unsigned getWavefrontSize(const FeatureBitset &Features);<br>
+/// \returns Wavefront size for given subtarget \p STI.<br>
+unsigned getWavefrontSize(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Local memory size in bytes for given subtarget \p Features.<br>
-unsigned getLocalMemorySize(const FeatureBitset &Features);<br>
+/// \returns Local memory size in bytes for given subtarget \p STI.<br>
+unsigned getLocalMemorySize(const MCSubtargetInfo *STI);<br>
<br>
/// \returns Number of execution units per compute unit for given subtarget \p<br>
-/// Features.<br>
-unsigned getEUsPerCU(const FeatureBitset &Features);<br>
+/// STI.<br>
+unsigned getEUsPerCU(const MCSubtargetInfo *STI);<br>
<br>
/// \returns Maximum number of work groups per compute unit for given subtarget<br>
-/// \p Features and limited by given \p FlatWorkGroupSize.<br>
-unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,<br>
+/// \p STI and limited by given \p FlatWorkGroupSize.<br>
+unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize);<br>
<br>
/// \returns Maximum number of waves per compute unit for given subtarget \p<br>
-/// Features without any kind of limitation.<br>
-unsigned getMaxWavesPerCU(const FeatureBitset &Features);<br>
+/// STI without any kind of limitation.<br>
+unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI);<br>
<br>
/// \returns Maximum number of waves per compute unit for given subtarget \p<br>
-/// Features and limited by given \p FlatWorkGroupSize.<br>
-unsigned getMaxWavesPerCU(const FeatureBitset &Features,<br>
+/// STI and limited by given \p FlatWorkGroupSize.<br>
+unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize);<br>
<br>
/// \returns Minimum number of waves per execution unit for given subtarget \p<br>
-/// Features.<br>
-unsigned getMinWavesPerEU(const FeatureBitset &Features);<br>
+/// STI.<br>
+unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);<br>
<br>
/// \returns Maximum number of waves per execution unit for given subtarget \p<br>
-/// Features without any kind of limitation.<br>
+/// STI without any kind of limitation.<br>
unsigned getMaxWavesPerEU();<br>
<br>
/// \returns Maximum number of waves per execution unit for given subtarget \p<br>
-/// Features and limited by given \p FlatWorkGroupSize.<br>
-unsigned getMaxWavesPerEU(const FeatureBitset &Features,<br>
+/// STI and limited by given \p FlatWorkGroupSize.<br>
+unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize);<br>
<br>
-/// \returns Minimum flat work group size for given subtarget \p Features.<br>
-unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);<br>
+/// \returns Minimum flat work group size for given subtarget \p STI.<br>
+unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Maximum flat work group size for given subtarget \p Features.<br>
-unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);<br>
+/// \returns Maximum flat work group size for given subtarget \p STI.<br>
+unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Number of waves per work group for given subtarget \p Features and<br>
+/// \returns Number of waves per work group for given subtarget \p STI and<br>
/// limited by given \p FlatWorkGroupSize.<br>
-unsigned getWavesPerWorkGroup(const FeatureBitset &Features,<br>
+unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,<br>
unsigned FlatWorkGroupSize);<br>
<br>
-/// \returns SGPR allocation granularity for given subtarget \p Features.<br>
-unsigned getSGPRAllocGranule(const FeatureBitset &Features);<br>
+/// \returns SGPR allocation granularity for given subtarget \p STI.<br>
+unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns SGPR encoding granularity for given subtarget \p Features.<br>
-unsigned getSGPREncodingGranule(const FeatureBitset &Features);<br>
+/// \returns SGPR encoding granularity for given subtarget \p STI.<br>
+unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Total number of SGPRs for given subtarget \p Features.<br>
-unsigned getTotalNumSGPRs(const FeatureBitset &Features);<br>
+/// \returns Total number of SGPRs for given subtarget \p STI.<br>
+unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Addressable number of SGPRs for given subtarget \p Features.<br>
-unsigned getAddressableNumSGPRs(const FeatureBitset &Features);<br>
+/// \returns Addressable number of SGPRs for given subtarget \p STI.<br>
+unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);<br>
<br>
/// \returns Minimum number of SGPRs that meets the given number of waves per<br>
-/// execution unit requirement for given subtarget \p Features.<br>
-unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);<br>
+/// execution unit requirement for given subtarget \p STI.<br>
+unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);<br>
<br>
/// \returns Maximum number of SGPRs that meets the given number of waves per<br>
-/// execution unit requirement for given subtarget \p Features.<br>
-unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,<br>
+/// execution unit requirement for given subtarget \p STI.<br>
+unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,<br>
bool Addressable);<br>
<br>
/// \returns Number of extra SGPRs implicitly required by given subtarget \p<br>
-/// Features when the given special registers are used.<br>
-unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed,<br>
+/// STI when the given special registers are used.<br>
+unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,<br>
bool FlatScrUsed, bool XNACKUsed);<br>
<br>
/// \returns Number of extra SGPRs implicitly required by given subtarget \p<br>
-/// Features when the given special registers are used. XNACK is inferred from<br>
-/// \p Features.<br>
-unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed,<br>
+/// STI when the given special registers are used. XNACK is inferred from<br>
+/// \p STI.<br>
+unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,<br>
bool FlatScrUsed);<br>
<br>
-/// \returns Number of SGPR blocks needed for given subtarget \p Features when<br>
+/// \returns Number of SGPR blocks needed for given subtarget \p STI when<br>
/// \p NumSGPRs are used. \p NumSGPRs should already include any special<br>
/// register counts.<br>
-unsigned getNumSGPRBlocks(const FeatureBitset &Features, unsigned NumSGPRs);<br>
+unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);<br>
<br>
-/// \returns VGPR allocation granularity for given subtarget \p Features.<br>
-unsigned getVGPRAllocGranule(const FeatureBitset &Features);<br>
+/// \returns VGPR allocation granularity for given subtarget \p STI.<br>
+unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns VGPR encoding granularity for given subtarget \p Features.<br>
-unsigned getVGPREncodingGranule(const FeatureBitset &Features);<br>
+/// \returns VGPR encoding granularity for given subtarget \p STI.<br>
+unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Total number of VGPRs for given subtarget \p Features.<br>
-unsigned getTotalNumVGPRs(const FeatureBitset &Features);<br>
+/// \returns Total number of VGPRs for given subtarget \p STI.<br>
+unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);<br>
<br>
-/// \returns Addressable number of VGPRs for given subtarget \p Features.<br>
-unsigned getAddressableNumVGPRs(const FeatureBitset &Features);<br>
+/// \returns Addressable number of VGPRs for given subtarget \p STI.<br>
+unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);<br>
<br>
/// \returns Minimum number of VGPRs that meets given number of waves per<br>
-/// execution unit requirement for given subtarget \p Features.<br>
-unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);<br>
+/// execution unit requirement for given subtarget \p STI.<br>
+unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);<br>
<br>
/// \returns Maximum number of VGPRs that meets given number of waves per<br>
-/// execution unit requirement for given subtarget \p Features.<br>
-unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);<br>
+/// execution unit requirement for given subtarget \p STI.<br>
+unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);<br>
<br>
-/// \returns Number of VGPR blocks needed for given subtarget \p Features when<br>
+/// \returns Number of VGPR blocks needed for given subtarget \p STI when<br>
/// \p NumVGPRs are used.<br>
-unsigned </blockquote></div></div>