<div dir="ltr">Hi,<div>Here is a small ir that causes seg fault only when the llc is compiled with the "[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction" change.</div><div><div><br></div><div>To reproduce:</div><div>$ llvm-as test_case.ll -o test_case.bc</div><div>$ opt test_case.bc -ee-instrument -tbaa -scoped-noalias -simplifycfg -sroa -early-cse -lower-expect -forceattrs -tbaa -scoped-noalias -inferattrs -ipsccp -called-value-propagation -globalopt -mem2reg -deadargelim -instcombine -simplifycfg -globals-aa -prune-eh -inline -functionattrs -sroa -early-cse-memssa -speculative-execution -jump-threading -correlated-propagation -simplifycfg -instcombine -libcalls-shrinkwrap -pgo-memop-opt -tailcallelim -simplifycfg -reassociate -loop-rotate -licm -loop-unswitch -simplifycfg -instcombine -indvars -loop-idiom -loop-deletion -loop-unroll -mldst-motion -gvn -memcpyopt -sccp -bdce -instcombine -jump-threading -correlated-propagation -dse -licm -adce -simplifycfg -instcombine -barrier -elim-avail-extern -rpo-functionattrs -globalopt -globaldce -globals-aa -float2int -loop-rotate -loop-distribute -loop-vectorize -loop-load-elim -instcombine -simplifycfg -instcombine -loop-unroll -instcombine -licm -alignment-from-assumptions -strip-dead-prototypes -globaldce -constmerge -loop-sink -instsimplify -div-rem-pairs -simplifycfg</div></div><div><br></div><div>>>></div><div><div>; ModuleID = 'bugpoint-reduced-simplified.bc'</div><div>source_filename = "experimental/users/tamur/llvm/example.cc"</div><div>target datalayout = "e-m:e-i64:64-n32:64"</div><div>target triple = "powerpc64le-grtev4-linux-gnu"</div><div><br></div><div>; Function Attrs: nounwind</div><div>define void @_Test(i32 signext) local_unnamed_addr #0 align 2 {</div><div> %2 = ashr i32 %0, 31</div><div> %3 = sext i32 %2 to i64</div><div> %4 = zext i64 %3 to i128</div><div> %5 = shl nuw i128 %4, 64</div><div> %6 = or i128 %5, 0</div><div> %7 = or i128 undef, 0</div><div> %8 = mul i128 %7, %6</div><div> %9 = lshr i128 %8, 64</div><div> %10 = trunc i128 %9 to i64</div><div> %11 = load i64, i64* undef, align 8</div><div> %12 = and i64 %11, %10</div><div> %13 = call i64 @llvm.bswap.i64(i64 %12) #2</div><div> store i64 %13, i64* undef, align 8</div><div> br i1 undef, label %15, label %14</div><div><br></div><div>; <label>:14: ; preds = %1</div><div> br label %15</div><div><br></div><div>; <label>:15: ; preds = %14, %1</div><div> ret void</div><div>}</div><div><br></div><div>; Function Attrs: nounwind readnone speculatable</div><div>declare i64 @llvm.bswap.i64(i64) #1</div><div><br></div><div>attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "strict-float-cast-overflow"="false" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }</div><div>attributes #1 = { nounwind readnone speculatable }</div><div>attributes #2 = { nounwind }</div></div><div>>>></div><div><br></div><div>Please let me know if there is anything else I need to do.</div><div>Thanks,</div><div>Ali</div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, Aug 22, 2018 at 9:33 AM Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Ali is working on it and we'll see if we can get it to you today.<div><br></div><div>-eric<br><br><div class="gmail_quote"><div dir="ltr">On Wed, Aug 22, 2018 at 5:28 AM Nemanja Ivanovic <<a href="mailto:nemanja.i.ibm@gmail.com" target="_blank">nemanja.i.ibm@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><div>Thanks for reverting Eric,<br><br></div>I look forward to a test case so we can get this sorted out.<br></div></div><div dir="ltr">Nemanja<br></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Aug 21, 2018 at 7:03 PM Eric Christopher <<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">I went ahead and reverted this here:<div><br></div><div><div>Author: Eric Christopher <<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>></div><div>Date: Tue Aug 21 18:35:08 2018 +0000</div><div><br></div><div> Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction" due to it causing a compiler crash on valid.</div><div><br></div><div> This reverts commit r340016, testcase forthcoming.</div><div><br></div><div> git-svn-id: <a href="https://llvm.org/svn/llvm-project/llvm/trunk@340315" target="_blank">https://llvm.org/svn/llvm-project/llvm/trunk@340315</a> 91177308-0d34-0410-b5e6-96231b3b80d8</div></div><div><br></div><div>after talking with Nemanja.</div><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Aug 21, 2018 at 11:11 AM Eric Christopher <<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi Nemanja,<div><br></div><div>We're seeing a compiler crash on valid with this patch - while we're working up a testcase would you mind reverting?</div></div><div dir="ltr"><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Fri, Aug 17, 2018 at 5:36 AM Nemanja Ivanovic via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: nemanjai<br>
Date: Fri Aug 17 05:35:44 2018<br>
New Revision: 340016<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=340016&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=340016&view=rev</a><br>
Log:<br>
[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction<br>
<br>
Add a DAG combine for the PowerPC code generator to generate the Power9 extswsli<br>
extend sign and shift immediate instruction.<br>
<br>
Patch by RolandF.<br>
<br>
Differential revision: <a href="https://reviews.llvm.org/D49879" rel="noreferrer" target="_blank">https://reviews.llvm.org/D49879</a><br>
<br>
Added:<br>
llvm/trunk/llvm/<br>
llvm/trunk/llvm/test/<br>
llvm/trunk/llvm/test/CodeGen/<br>
llvm/trunk/llvm/test/CodeGen/PowerPC/<br>
llvm/trunk/llvm/test/CodeGen/PowerPC/extswsli.ll<br>
llvm/trunk/test/CodeGen/PowerPC/extswsli.ll<br>
Modified:<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td<br>
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=340016&r1=340015&r2=340016&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=340016&r1=340015&r2=340016&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Aug 17 05:35:44 2018<br>
@@ -1351,6 +1351,7 @@ const char *PPCTargetLowering::getTarget<br>
case PPCISD::QBFLT: return "PPCISD::QBFLT";<br>
case PPCISD::QVLFSb: return "PPCISD::QVLFSb";<br>
case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";<br>
+ case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";<br>
}<br>
return nullptr;<br>
}<br>
@@ -14102,7 +14103,30 @@ SDValue PPCTargetLowering::combineSHL(SD<br>
if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))<br>
return Value;<br>
<br>
- return SDValue();<br>
+ SDValue N0 = N->getOperand(0);<br>
+ ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1));<br>
+ if (!Subtarget.isISA3_0() ||<br>
+ N0.getOpcode() != ISD::SIGN_EXTEND ||<br>
+ N0.getOperand(0).getValueType() != MVT::i32 ||<br>
+ CN1 == nullptr)<br>
+ return SDValue();<br>
+<br>
+ // We can't save an operation here if the value is already extended, and<br>
+ // the existing shift is easier to combine.<br>
+ SDValue ExtsSrc = N0.getOperand(0);<br>
+ if (ExtsSrc.getOpcode() == ISD::TRUNCATE &&<br>
+ ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext)<br>
+ return SDValue();<br>
+<br>
+ SDLoc DL(N0);<br>
+ SDValue ShiftBy = SDValue(CN1, 0);<br>
+ // We want the shift amount to be i32 on the extswli, but the shift could<br>
+ // have an i64.<br>
+ if (ShiftBy.getValueType() == MVT::i64)<br>
+ ShiftBy = DCI.DAG.getConstant(CN1->getZExtValue(), DL, MVT::i32);<br>
+<br>
+ return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0),<br>
+ ShiftBy);<br>
}<br>
<br>
SDValue PPCTargetLowering::combineSRA(SDNode *N, DAGCombinerInfo &DCI) const {<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=340016&r1=340015&r2=340016&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=340016&r1=340015&r2=340016&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Fri Aug 17 05:35:44 2018<br>
@@ -149,6 +149,10 @@ namespace llvm {<br>
/// For vector types, only the last n bits are used. See vsld.<br>
SRL, SRA, SHL,<br>
<br>
+ /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign<br>
+ /// word and shift left immediate.<br>
+ EXTSWSLI,<br>
+<br>
/// The combination of sra[wd]i and addze used to implemented signed<br>
/// integer division by a power of 2. The first operand is the dividend,<br>
/// and the second is the constant shift amount (representing the<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=340016&r1=340015&r2=340016&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=340016&r1=340015&r2=340016&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Fri Aug 17 05:35:44 2018<br>
@@ -717,9 +717,10 @@ defm SRADI : XSForm_1rc<31, 413, (outs<br>
"sradi", "$rA, $rS, $SH", IIC_IntRotateDI,<br>
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;<br>
<br>
-defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),<br>
+defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins gprc:$rS, u6imm:$SH),<br>
"extswsli", "$rA, $rS, $SH", IIC_IntRotateDI,<br>
- []>, isPPC64;<br>
+ [(set i64:$rA, (PPCextswsli i32:$rS, (i32 imm:$SH)))]>,<br>
+ isPPC64, Requires<[IsISA3_0]>;<br>
<br>
// For fast-isel:<br>
let isCodeGenOnly = 1, Defs = [CARRY] in<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=340016&r1=340015&r2=340016&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=340016&r1=340015&r2=340016&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Fri Aug 17 05:35:44 2018<br>
@@ -114,6 +114,10 @@ def SDT_PPCqvlfsb : SDTypeProfile<1, 1,<br>
SDTCisVec<0>, SDTCisPtrTy<1><br>
]>;<br>
<br>
+def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli<br>
+ SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2><br>
+]>;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// PowerPC specific DAG Nodes.<br>
//<br>
@@ -218,6 +222,8 @@ def PPCsrl : SDNode<"PPCISD::SRL"<br>
def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;<br>
def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;<br>
<br>
+def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>;<br>
+<br>
// Move 2 i64 values into a VSX register<br>
def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",<br>
SDTypeProfile<1, 2,<br>
<br>
Added: llvm/trunk/llvm/test/CodeGen/PowerPC/extswsli.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/llvm/test/CodeGen/PowerPC/extswsli.ll?rev=340016&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/llvm/test/CodeGen/PowerPC/extswsli.ll?rev=340016&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/llvm/test/CodeGen/PowerPC/extswsli.ll (added)<br>
+++ llvm/trunk/llvm/test/CodeGen/PowerPC/extswsli.ll Fri Aug 17 05:35:44 2018<br>
@@ -0,0 +1,17 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \<br>
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s<br>
+<br>
+@z = external local_unnamed_addr global i32*, align 8<br>
+<br>
+; Function Attrs: norecurse nounwind readonly<br>
+define signext i32 @_Z2tcii(i32 signext %x, i32 signext %y) local_unnamed_addr #0 {<br>
+entry:<br>
+ %0 = load i32*, i32** @z, align 8<br>
+ %add = add nsw i32 %y, %x<br>
+ %idxprom = sext i32 %add to i64<br>
+ %arrayidx = getelementptr inbounds i32, i32* %0, i64 %idxprom<br>
+ %1 = load i32, i32* %arrayidx, align 4<br>
+ ret i32 %1<br>
+; CHECK-LABEL: @_Z2tcii<br>
+; CHECK: extswsli {{r[0-9]+}}, {{r[0-9]+}}, 2<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/extswsli.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/extswsli.ll?rev=340016&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/extswsli.ll?rev=340016&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/extswsli.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/extswsli.ll Fri Aug 17 05:35:44 2018<br>
@@ -0,0 +1,17 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \<br>
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s<br>
+<br>
+@z = external local_unnamed_addr global i32*, align 8<br>
+<br>
+; Function Attrs: norecurse nounwind readonly<br>
+define signext i32 @_Z2tcii(i32 signext %x, i32 signext %y) local_unnamed_addr #0 {<br>
+entry:<br>
+ %0 = load i32*, i32** @z, align 8<br>
+ %add = add nsw i32 %y, %x<br>
+ %idxprom = sext i32 %add to i64<br>
+ %arrayidx = getelementptr inbounds i32, i32* %0, i64 %idxprom<br>
+ %1 = load i32, i32* %arrayidx, align 4<br>
+ ret i32 %1<br>
+; CHECK-LABEL: @_Z2tcii<br>
+; CHECK: extswsli {{r[0-9]+}}, {{r[0-9]+}}, 2<br>
+}<br>
<br>
<br>
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