<div dir="ltr">(and lots of other bots it looks like)</div><br><div class="gmail_quote"><div dir="ltr">On Thu, Aug 16, 2018 at 7:39 PM Chandler Carruth <<a href="mailto:chandlerc@gmail.com">chandlerc@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Not sure the bot blame will work, but pretty sure this broke LTO bots:<div><a href="http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/12107/steps/test-stage2-compiler/logs/stdio" target="_blank">http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/12107/steps/test-stage2-compiler/logs/stdio</a><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/9867/steps/test-stage2-compiler/logs/stdio" target="_blank">http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/9867/steps/test-stage2-compiler/logs/stdio</a><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Aug 16, 2018 at 6:42 PM Aditya Nandakumar via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: aditya_nandakumar<br>
Date: Thu Aug 16 18:41:56 2018<br>
New Revision: 339977<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=339977&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=339977&view=rev</a><br>
Log:<br>
[GISel]: Add Opcodes for a few LLVM Intrinsics<br>
<br>
<a href="https://reviews.llvm.org/D50401" rel="noreferrer" target="_blank">https://reviews.llvm.org/D50401</a><br>
<br>
Add opcodes for llvm.intrinsic.trunc, round, and update the IRTranslator<br>
for the same.<br>
<br>
Reviewed by: dsanders.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/Support/TargetOpcodes.def<br>
llvm/trunk/include/llvm/Target/GenericOpcodes.td<br>
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp<br>
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll<br>
<br>
Modified: llvm/trunk/include/llvm/Support/TargetOpcodes.def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetOpcodes.def?rev=339977&r1=339976&r2=339977&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetOpcodes.def?rev=339977&r1=339976&r2=339977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Support/TargetOpcodes.def (original)<br>
+++ llvm/trunk/include/llvm/Support/TargetOpcodes.def Thu Aug 16 18:41:56 2018<br>
@@ -268,6 +268,12 @@ HANDLE_TARGET_OPCODE(G_INTTOPTR)<br>
/// COPY is the relevant instruction.<br>
HANDLE_TARGET_OPCODE(G_BITCAST)<br>
<br>
+/// INTRINSIC trunc intrinsic.<br>
+HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)<br>
+<br>
+/// INTRINSIC round intrinsic.<br>
+HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)<br>
+<br>
/// Generic load (including anyext load)<br>
HANDLE_TARGET_OPCODE(G_LOAD)<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=339977&r1=339976&r2=339977&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=339977&r1=339976&r2=339977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)<br>
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Thu Aug 16 18:41:56 2018<br>
@@ -513,6 +513,21 @@ def G_FLOG2 : GenericInstruction {<br>
}<br>
<br>
//------------------------------------------------------------------------------<br>
+// Opcodes for LLVM Intrinsics<br>
+//------------------------------------------------------------------------------<br>
+def G_INTRINSIC_TRUNC : GenericInstruction {<br>
+ let OutOperandList = (outs type0:$dst);<br>
+ let InOperandList = (ins type0:$src1);<br>
+ let hasSideEffects = 0;<br>
+}<br>
+<br>
+def G_INTRINSIC_ROUND : GenericInstruction {<br>
+ let OutOperandList = (outs type0:$dst);<br>
+ let InOperandList = (ins type0:$src1);<br>
+ let hasSideEffects = 0;<br>
+}<br>
+<br>
+//------------------------------------------------------------------------------<br>
// Memory ops<br>
//------------------------------------------------------------------------------<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=339977&r1=339976&r2=339977&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=339977&r1=339976&r2=339977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Aug 16 18:41:56 2018<br>
@@ -850,6 +850,16 @@ bool IRTranslator::translateKnownIntrins<br>
.addDef(getOrCreateVReg(CI))<br>
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));<br>
return true;<br>
+ case Intrinsic::trunc:<br>
+ MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)<br>
+ .addDef(getOrCreateVReg(CI))<br>
+ .addUse(getOrCreateVReg(*CI.getArgOperand(0)));<br>
+ return true;<br>
+ case Intrinsic::round:<br>
+ MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)<br>
+ .addDef(getOrCreateVReg(CI))<br>
+ .addUse(getOrCreateVReg(*CI.getArgOperand(0)));<br>
+ return true;<br>
case Intrinsic::fma:<br>
MIRBuilder.buildInstr(TargetOpcode::G_FMA)<br>
.addDef(getOrCreateVReg(CI))<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=339977&r1=339976&r2=339977&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=339977&r1=339976&r2=339977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Aug 16 18:41:56 2018<br>
@@ -1408,6 +1408,26 @@ define float @test_fabs_intrin(float %a)<br>
ret float %res<br>
}<br>
<br>
+declare float @llvm.trunc.f32(float)<br>
+define float @test_intrinsic_trunc(float %a) {<br>
+; CHECK-LABEL: name: test_intrinsic_trunc<br>
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0<br>
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]<br>
+; CHECK: $s0 = COPY [[RES]]<br>
+ %res = call float @llvm.trunc.f32(float %a)<br>
+ ret float %res<br>
+}<br>
+<br>
+declare float @llvm.round.f32(float)<br>
+define float @test_intrinsic_round(float %a) {<br>
+; CHECK-LABEL: name: test_intrinsic_round<br>
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0<br>
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]<br>
+; CHECK: $s0 = COPY [[RES]]<br>
+ %res = call float @llvm.round.f32(float %a)<br>
+ ret float %res<br>
+}<br>
+<br>
declare i32 @llvm.ctlz.i32(i32, i1)<br>
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {<br>
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef<br>
<br>
<br>
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</blockquote></div>
</blockquote></div>