<div dir="ltr">Sorry to dig up an old thread, but I enabled this backend to test changes I'm making to all backends and I get the following warning from TableGen for the AVR backend:<div><br></div><div><div>[1252/2117] Building AVRGenDisassemblerTables.inc...</div><div>Decoding Conflict:</div><div> 000011..........</div><div> 0000............</div><div> 00..............</div><div> ................</div><div> ADDRdRr 000011__________</div><div> LSLRd 000011__________</div><div>Decoding Conflict:</div><div> 000111..........</div><div> 0001............</div><div> 00..............</div><div> ................</div><div> ADCRdRr 000111__________</div><div> ROLRd 000111__________</div><div>Decoding Conflict:</div><div> 001000..........</div><div> 0010............</div><div> 00..............</div><div> ................</div><div> ANDRdRr 001000__________</div><div> TSTRd 001000__________</div><div>Decoding Conflict:</div><div> 0110............</div><div> 01..............</div><div> ................</div><div> ORIRdK 0110____________</div><div> SBRRdK 0110____________</div><div>Decoding Conflict:</div><div> 0111............</div><div> 01..............</div><div> ................</div><div> ANDIRdK 0111____________</div><div> CBRRdK 0111____________</div></div><div><br></div><div><br></div><div>Could you look into this and fix?</div></div><br><div class="gmail_quote"><div dir="ltr">On Sat, Oct 22, 2016 at 5:07 PM Dylan McKay via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dylanmckay<br>
Date: Sat Oct 22 18:57:59 2016<br>
New Revision: 284930<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=284930&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=284930&view=rev</a><br>
Log:<br>
[AVR] Add the machine code disassembler<br>
<br>
This adds a super basic implementation of a machine code disassembler.<br>
<br>
It doesn't support any operands with custom encoding.<br>
<br>
Added:<br>
llvm/trunk/lib/Target/AVR/Disassembler/<br>
llvm/trunk/lib/Target/AVR/Disassembler/AVRDisassembler.cpp<br>
llvm/trunk/lib/Target/AVR/Disassembler/CMakeLists.txt<br>
llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt<br>
- copied, changed from r284922, llvm/trunk/lib/Target/AVR/LLVMBuild.txt<br>
Modified:<br>
llvm/trunk/lib/Target/AVR/CMakeLists.txt<br>
llvm/trunk/lib/Target/AVR/LLVMBuild.txt<br>
<br>
Modified: llvm/trunk/lib/Target/AVR/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/CMakeLists.txt?rev=284930&r1=284929&r2=284930&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/CMakeLists.txt?rev=284930&r1=284929&r2=284930&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AVR/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/AVR/CMakeLists.txt Sat Oct 22 18:57:59 2016<br>
@@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS AVR.td)<br>
tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)<br>
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)<br>
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)<br>
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)<br>
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)<br>
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)<br>
tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)<br>
<br>
Added: llvm/trunk/lib/Target/AVR/Disassembler/AVRDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/Disassembler/AVRDisassembler.cpp?rev=284930&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/Disassembler/AVRDisassembler.cpp?rev=284930&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AVR/Disassembler/AVRDisassembler.cpp (added)<br>
+++ llvm/trunk/lib/Target/AVR/Disassembler/AVRDisassembler.cpp Sat Oct 22 18:57:59 2016<br>
@@ -0,0 +1,160 @@<br>
+//===- AVRDisassembler.cpp - Disassembler for AVR ---------------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file is part of the AVR Disassembler.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AVR.h"<br>
+#include "AVRRegisterInfo.h"<br>
+#include "AVRSubtarget.h"<br>
+#include "MCTargetDesc/AVRMCTargetDesc.h"<br>
+<br>
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"<br>
+#include "llvm/MC/MCFixedLenDisassembler.h"<br>
+#include "llvm/MC/MCInst.h"<br>
+#include "llvm/MC/MCContext.h"<br>
+#include "llvm/MC/MCAsmInfo.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "avr-disassembler"<br>
+<br>
+typedef MCDisassembler::DecodeStatus DecodeStatus;<br>
+<br>
+namespace {<br>
+<br>
+/// A disassembler class for AVR.<br>
+class AVRDisassembler : public MCDisassembler {<br>
+public:<br>
+ AVRDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)<br>
+ : MCDisassembler(STI, Ctx) {}<br>
+ virtual ~AVRDisassembler() {}<br>
+<br>
+ DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,<br>
+ ArrayRef<uint8_t> Bytes, uint64_t Address,<br>
+ raw_ostream &VStream,<br>
+ raw_ostream &CStream) const override;<br>
+};<br>
+}<br>
+<br>
+namespace llvm {<br>
+extern Target TheAVRTarget;<br>
+}<br>
+<br>
+static MCDisassembler *createAVRDisassembler(const Target &T,<br>
+ const MCSubtargetInfo &STI,<br>
+ MCContext &Ctx) {<br>
+ return new AVRDisassembler(STI, Ctx);<br>
+}<br>
+<br>
+<br>
+extern "C" void LLVMInitializeAVRDisassembler() {<br>
+ // Register the disassembler.<br>
+ TargetRegistry::RegisterMCDisassembler(TheAVRTarget,<br>
+ createAVRDisassembler);<br>
+}<br>
+<br>
+static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo,<br>
+ uint64_t Address, const void *Decoder) {<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+#include "AVRGenDisassemblerTables.inc"<br>
+<br>
+static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,<br>
+ uint64_t &Size, uint32_t &Insn) {<br>
+ if (Bytes.size() < 2) {<br>
+ Size = 0;<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+<br>
+ Size = 2;<br>
+ Insn = (Bytes[0] << 0) | (Bytes[1] << 8);<br>
+<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,<br>
+ uint64_t &Size, uint32_t &Insn) {<br>
+<br>
+ if (Bytes.size() < 4) {<br>
+ Size = 0;<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+<br>
+ Size = 4;<br>
+ Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);<br>
+<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+static const uint8_t *getDecoderTable(uint64_t Size) {<br>
+<br>
+ switch (Size) {<br>
+ case 2: return DecoderTable16;<br>
+ case 4: return DecoderTable32;<br>
+ default: llvm_unreachable("instructions must be 16 or 32-bits");<br>
+ }<br>
+}<br>
+<br>
+DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,<br>
+ ArrayRef<uint8_t> Bytes,<br>
+ uint64_t Address,<br>
+ raw_ostream &VStream,<br>
+ raw_ostream &CStream) const {<br>
+ uint32_t Insn;<br>
+<br>
+ DecodeStatus Result;<br>
+<br>
+ // Try decode a 16-bit instruction.<br>
+ {<br>
+ Result = readInstruction16(Bytes, Address, Size, Insn);<br>
+<br>
+ if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;<br>
+<br>
+ // Try to auto-decode a 16-bit instruction.<br>
+ Result = decodeInstruction(getDecoderTable(Size), Instr,<br>
+ Insn, Address, this, STI);<br>
+<br>
+ if (Result != MCDisassembler::Fail)<br>
+ return Result;<br>
+ }<br>
+<br>
+ // Try decode a 32-bit instruction.<br>
+ {<br>
+ Result = readInstruction32(Bytes, Address, Size, Insn);<br>
+<br>
+ if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;<br>
+<br>
+ Result = decodeInstruction(getDecoderTable(Size), Instr, Insn,<br>
+ Address, this, STI);<br>
+<br>
+ if (Result != MCDisassembler::Fail) {<br>
+ return Result;<br>
+ }<br>
+<br>
+ return MCDisassembler::Fail;<br>
+ }<br>
+}<br>
+<br>
+typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,<br>
+ const void *Decoder);<br>
+<br>
<br>
Added: llvm/trunk/lib/Target/AVR/Disassembler/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/Disassembler/CMakeLists.txt?rev=284930&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/Disassembler/CMakeLists.txt?rev=284930&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AVR/Disassembler/CMakeLists.txt (added)<br>
+++ llvm/trunk/lib/Target/AVR/Disassembler/CMakeLists.txt Sat Oct 22 18:57:59 2016<br>
@@ -0,0 +1,4 @@<br>
+add_llvm_library(LLVMAVRDisassembler<br>
+ AVRDisassembler.cpp<br>
+)<br>
+<br>
<br>
Copied: llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt (from r284922, llvm/trunk/lib/Target/AVR/LLVMBuild.txt)<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt?p2=llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt&p1=llvm/trunk/lib/Target/AVR/LLVMBuild.txt&r1=284922&r2=284930&rev=284930&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt?p2=llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt&p1=llvm/trunk/lib/Target/AVR/LLVMBuild.txt&r1=284922&r2=284930&rev=284930&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AVR/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/AVR/Disassembler/LLVMBuild.txt Sat Oct 22 18:57:59 2016<br>
@@ -1,4 +1,4 @@<br>
-;===- ./lib/Target/AVR/LLVMBuild.txt ---------------------------*- Conf -*--===;<br>
+;===- ./lib/Target/AVR/Disassembler/LLVMBuild.txt --------------*- Conf -*--===;<br>
;<br>
; The LLVM Compiler Infrastructure<br>
;<br>
@@ -15,20 +15,9 @@<br>
;<br>
;===------------------------------------------------------------------------===;<br>
<br>
-[common]<br>
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo<br>
-<br>
[component_0]<br>
-type = TargetGroup<br>
-name = AVR<br>
-parent = Target<br>
-has_asmprinter = 1<br>
-has_asmparser = 1<br>
-<br>
-[component_1]<br>
type = Library<br>
-name = AVRCodeGen<br>
+name = AVRDisassembler<br>
parent = AVR<br>
-required_libraries = AsmPrinter CodeGen Core MC AVRAsmPrinter AVRDesc AVRInfo SelectionDAG Support Target<br>
+required_libraries = MCDisassembler AVRInfo Support<br>
add_to_library_groups = AVR<br>
-<br>
<br>
Modified: llvm/trunk/lib/Target/AVR/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/LLVMBuild.txt?rev=284930&r1=284929&r2=284930&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/LLVMBuild.txt?rev=284930&r1=284929&r2=284930&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AVR/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/AVR/LLVMBuild.txt Sat Oct 22 18:57:59 2016<br>
@@ -16,7 +16,7 @@<br>
;===------------------------------------------------------------------------===;<br>
<br>
[common]<br>
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo<br>
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo<br>
<br>
[component_0]<br>
type = TargetGroup<br>
@@ -24,6 +24,7 @@ name = AVR<br>
parent = Target<br>
has_asmprinter = 1<br>
has_asmparser = 1<br>
+has_disassembler = 1<br>
<br>
[component_1]<br>
type = Library<br>
<br>
<br>
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</blockquote></div>