<div dir="ltr"><div>Hello Jonas,</div><div><br></div><div>This commit broke at least 3 builders:</div><div><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/9601">http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/9601</a></div><div><a href="http://lab.llvm.org:8011/builders/lld-perf-testsuite">http://lab.llvm.org:8011/builders/lld-perf-testsuite</a></div><div><a href="http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/">http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/</a></div><div>. . .</div><div>FAILED: lib/Target/SystemZ/CMakeFiles/LLVMSystemZCodeGen.dir/SystemZHazardRecognizer.cpp.o </div><div>/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/install/stage1/bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/Target/SystemZ -I/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/lib/Target/SystemZ -Iinclude -I/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/include -fPIC -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -std=c++11 -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -UNDEBUG -fno-exceptions -fno-rtti -MD -MT lib/Target/SystemZ/CMakeFiles/LLVMSystemZCodeGen.dir/SystemZHazardRecognizer.cpp.o -MF lib/Target/SystemZ/CMakeFiles/LLVMSystemZCodeGen.dir/SystemZHazardRecognizer.cpp.o.d -o lib/Target/SystemZ/CMakeFiles/LLVMSystemZCodeGen.dir/SystemZHazardRecognizer.cpp.o -c /home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/lib/Target/SystemZ/SystemZHazardRecognizer.cpp</div><div>/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/lib/Target/SystemZ/SystemZHazardRecognizer.cpp:105:11: error: implicit conversion turns string literal into bool: 'const char [39]' to 'bool' [-Werror,-Wstring-conversion]</div><div> "Current decoder group is already full!");</div><div> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~</div><div>/usr/include/assert.h:89:5: note: expanded from macro 'assert'</div><div> ((expr) \</div><div> ^~~~</div><div>1 error generated.</div><div><br></div><div>Please have a look?</div><div><br></div><div>Thanks</div><div><br></div><div>Galina</div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 31, 2018 at 6:00 AM, Jonas Paulsson via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: jonpa<br>
Date: Tue Jul 31 06:00:42 2018<br>
New Revision: 338368<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=338368&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=338368&view=rev</a><br>
Log:<br>
[SystemZ] Improve decoding in case of instructions with four register operands.<br>
<br>
Since z13, the max group size will be 2 if any μop has more than 3 register<br>
sources.<br>
<br>
This has been ignored sofar in the SystemZHazardRecognizer, but is now<br>
handled by recognizing those instructions and adjusting the tracking of<br>
decoding and the cost heuristic for grouping.<br>
<br>
Review: Ulrich Weigand<br>
<a href="https://reviews.llvm.org/D49847" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D49847</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.cpp<br>
llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.h<br>
llvm/trunk/lib/Target/SystemZ/<wbr>SystemZMachineScheduler.cpp<br>
llvm/trunk/test/CodeGen/<wbr>SystemZ/vec-cmp-cmp-logic-<wbr>select.ll<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZHazardRecognizer.cpp?rev=338368&r1=338367&r2=338368&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>SystemZ/<wbr>SystemZHazardRecognizer.cpp?<wbr>rev=338368&r1=338367&r2=<wbr>338368&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.cpp Tue Jul 31 06:00:42 2018<br>
@@ -81,6 +81,7 @@ getHazardType(SUnit *m, int Stalls) {<br>
<br>
void SystemZHazardRecognizer::<wbr>Reset() {<br>
CurrGroupSize = 0;<br>
+ CurrGroupHas4RegOps = false;<br>
clearProcResCounters();<br>
GrpCount = 0;<br>
LastFPdOpCycleIdx = UINT_MAX;<br>
@@ -99,6 +100,12 @@ SystemZHazardRecognizer::<wbr>fitsIntoCurrent<br>
if (SC->BeginGroup)<br>
return (CurrGroupSize == 0);<br>
<br>
+ // An instruction with 4 register operands will not fit in last slot.<br>
+ assert ((CurrGroupSize < 2 || !CurrGroupHas4RegOps) ||<br>
+ "Current decoder group is already full!");<br>
+ if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))<br>
+ return false;<br>
+<br>
// Since a full group is handled immediately in EmitInstruction(),<br>
// SU should fit into current group. NumSlots should be 1 or 0,<br>
// since it is not a cracked or expanded instruction.<br>
@@ -108,6 +115,23 @@ SystemZHazardRecognizer::<wbr>fitsIntoCurrent<br>
return true;<br>
}<br>
<br>
+bool SystemZHazardRecognizer::<wbr>has4RegOps(const MachineInstr *MI) const {<br>
+ const MachineFunction &MF = *MI->getParent()->getParent();<br>
+ const TargetRegisterInfo *TRI = &TII->getRegisterInfo();<br>
+ const MCInstrDesc &MID = MI->getDesc();<br>
+ unsigned Count = 0;<br>
+ for (unsigned OpIdx = 0; OpIdx < MID.getNumOperands(); OpIdx++) {<br>
+ const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF);<br>
+ if (RC == nullptr)<br>
+ continue;<br>
+ if (OpIdx >= MID.getNumDefs() &&<br>
+ MID.getOperandConstraint(<wbr>OpIdx, MCOI::TIED_TO) != -1)<br>
+ continue;<br>
+ Count++;<br>
+ }<br>
+ return Count >= 4;<br>
+}<br>
+<br>
void SystemZHazardRecognizer::<wbr>nextGroup() {<br>
if (CurrGroupSize == 0)<br>
return;<br>
@@ -119,6 +143,7 @@ void SystemZHazardRecognizer::<wbr>nextGroup(<br>
<br>
// Reset counter for next group.<br>
CurrGroupSize = 0;<br>
+ CurrGroupHas4RegOps = false;<br>
<br>
// Decrease counters for execution units by one.<br>
for (unsigned i = 0; i < SchedModel-><wbr>getNumProcResourceKinds(); ++i)<br>
@@ -172,6 +197,8 @@ void SystemZHazardRecognizer::<wbr>dumpSU(SUn<br>
OS << "/EndsGroup";<br>
if (SU->isUnbuffered)<br>
OS << "/Unbuffered";<br>
+ if (has4RegOps(SU->getInstr()))<br>
+ OS << "/4RegOps";<br>
}<br>
<br>
void SystemZHazardRecognizer::<wbr>dumpCurrGroup(std::string Msg) const {<br>
@@ -184,6 +211,7 @@ void SystemZHazardRecognizer::<wbr>dumpCurrGr<br>
dbgs() << "{ " << CurGroupDbg << " }";<br>
dbgs() << " (" << CurrGroupSize << " decoder slot"<br>
<< (CurrGroupSize > 1 ? "s":"")<br>
+ << (CurrGroupHas4RegOps ? ", 4RegOps" : "")<br>
<< ")\n";<br>
}<br>
}<br>
@@ -294,11 +322,14 @@ EmitInstruction(SUnit *SU) {<br>
// Insert SU into current group by increasing number of slots used<br>
// in current group.<br>
CurrGroupSize += getNumDecoderSlots(SU);<br>
- assert (CurrGroupSize <= 3);<br>
+ CurrGroupHas4RegOps |= has4RegOps(SU->getInstr());<br>
+ unsigned GroupLim =<br>
+ ((CurrGroupHas4RegOps && getNumDecoderSlots(SU) < 3) ? 2 : 3);<br>
+ assert (CurrGroupSize <= GroupLim && "SU does not fit into decoder group!");<br>
<br>
// Check if current group is now full/ended. If so, move on to next<br>
// group to be ready to evaluate more candidates.<br>
- if (CurrGroupSize == 3 || SC->EndGroup)<br>
+ if (CurrGroupSize == GroupLim || SC->EndGroup)<br>
nextGroup();<br>
}<br>
<br>
@@ -325,6 +356,10 @@ int SystemZHazardRecognizer::<wbr>groupingCos<br>
return -1;<br>
}<br>
<br>
+ // An instruction with 4 register operands will not fit in last slot.<br>
+ if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))<br>
+ return 1;<br>
+<br>
// Most instructions can be placed in any decoder slot.<br>
return 0;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZHazardRecognizer.h?rev=338368&r1=338367&r2=338368&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>SystemZ/<wbr>SystemZHazardRecognizer.h?rev=<wbr>338368&r1=338367&r2=338368&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.h (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/<wbr>SystemZHazardRecognizer.h Tue Jul 31 06:00:42 2018<br>
@@ -45,15 +45,17 @@ namespace llvm {<br>
/// SystemZHazardRecognizer maintains the state for one MBB during scheduling.<br>
class SystemZHazardRecognizer : public ScheduleHazardRecognizer {<br>
<br>
-#ifndef NDEBUG<br>
const SystemZInstrInfo *TII;<br>
-#endif<br>
const TargetSchedModel *SchedModel;<br>
<br>
/// Keep track of the number of decoder slots used in the current<br>
/// decoder group.<br>
unsigned CurrGroupSize;<br>
<br>
+ /// True if an instruction with four reg operands have been scheduled into<br>
+ /// the current decoder group.<br>
+ bool CurrGroupHas4RegOps;<br>
+<br>
/// The tracking of resources here are quite similar to the common<br>
/// code use of a critical resource. However, z13 differs in the way<br>
/// that it has two processor sides which may be interesting to<br>
@@ -73,6 +75,9 @@ class SystemZHazardRecognizer : public S<br>
/// Return true if MI fits into current decoder group.<br>
bool fitsIntoCurrentGroup(SUnit *SU) const;<br>
<br>
+ /// Return true if this instruction has four register operands.<br>
+ bool has4RegOps(const MachineInstr *MI) const;<br>
+<br>
/// Two decoder groups per cycle are formed (for z13), meaning 2x3<br>
/// instructions. This function returns a number between 0 and 5,<br>
/// representing the current decoder slot of the current cycle. If an SU<br>
@@ -105,11 +110,7 @@ class SystemZHazardRecognizer : public S<br>
public:<br>
SystemZHazardRecognizer(const SystemZInstrInfo *tii,<br>
const TargetSchedModel *SM)<br>
- :<br>
-#ifndef NDEBUG<br>
- TII(tii),<br>
-#endif<br>
- SchedModel(SM) {<br>
+ : TII(tii), SchedModel(SM) {<br>
Reset();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/<wbr>SystemZMachineScheduler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp?rev=338368&r1=338367&r2=338368&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>SystemZ/<wbr>SystemZMachineScheduler.cpp?<wbr>rev=338368&r1=338367&r2=<wbr>338368&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/SystemZ/<wbr>SystemZMachineScheduler.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/<wbr>SystemZMachineScheduler.cpp Tue Jul 31 06:00:42 2018<br>
@@ -169,8 +169,7 @@ SUnit *SystemZPostRASchedStrategy::<wbr>pickN<br>
return *Available.begin();<br>
}<br>
<br>
- // All nodes that are possible to schedule are stored by in the<br>
- // Available set.<br>
+ // All nodes that are possible to schedule are stored in the Available set.<br>
LLVM_DEBUG(dbgs() << "** Available: "; Available.dump(*HazardRec););<br>
<br>
Candidate Best;<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>SystemZ/vec-cmp-cmp-logic-<wbr>select.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll?rev=338368&r1=338367&r2=338368&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/SystemZ/vec-cmp-cmp-<wbr>logic-select.ll?rev=338368&r1=<wbr>338367&r2=338368&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>SystemZ/vec-cmp-cmp-logic-<wbr>select.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>SystemZ/vec-cmp-cmp-logic-<wbr>select.ll Tue Jul 31 06:00:42 2018<br>
@@ -688,8 +688,8 @@ define <8 x float> @fun30(<8 x float> %v<br>
; CHECK-NEXT: vpkg %v6, %v6, %v7<br>
; CHECK-NEXT: vpkg %v4, %v4, %v5<br>
; CHECK-NEXT: vn %v5, %v16, %v6<br>
-; CHECK-NEXT: vsel %v24, %v3, %v2, %v5<br>
-; CHECK-NEXT: vldeb %v17, %v17<br>
+; CHECK-DAG: vsel %v24, %v3, %v2, %v5<br>
+; CHECK-DAG: vldeb %v17, %v17<br>
; CHECK-NEXT: vldeb %v18, %v18<br>
; CHECK-NEXT: vfchdb %v17, %v18, %v17<br>
; CHECK-NEXT: vmrhf %v18, %v30, %v30<br>
<br>
<br>
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</blockquote></div><br></div>