<div dir="ltr">FYI, Simon reverted this change at r338369.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 31, 2018 at 1:51 PM, Andrea Di Biagio <span dir="ltr"><<a href="mailto:andrea.dibiagio@gmail.com" target="_blank">andrea.dibiagio@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">
<div>Hi Andrew,<br><br>Could you please revert the changes to:</div><div> llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.cpp</div><div>
llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.h <br></div><div><br></div><div>Those changes were not part of <a href="https://reviews.llvm.org/D49243" rel="noreferrer" target="_blank">D49243</a>, and are causing tons of tablegen warnings.</div><div><br></div><div>P.s.: next time please reference the differential revision URL, so that phabricator will automatically close the review for you.</div><div>Also, a small paragraph in the commit message would have been nice to have.</div><span class="HOEnZb"><font color="#888888"><div><br></div><div>-Andrea</div>
<br></font></span></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 31, 2018 at 1:33 PM, Andrew V. Tischenko via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: avt77<br>
Date: Tue Jul 31 05:33:48 2018<br>
New Revision: 338365<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=338365&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=338365&view=rev</a><br>
Log:<br>
[X86] Improved sched models for X86 BT*rr instructions.<br>
<a href="https://reviews.llvm.org/D49243" rel="noreferrer" target="_blank">https://reviews.llvm.org/D4924<wbr>3</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>chedBroadwell.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>chedHaswell.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>chedSandyBridge.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeClient.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeServer.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr><a href="http://chedule.td">chedule.td</a><br>
llvm/trunk/lib/Target/X86/X86S<wbr>cheduleAtom.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>cheduleBtVer2.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>cheduleSLM.td<br>
llvm/trunk/lib/Target/X86/X86S<wbr>cheduleZnver1.td<br>
llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.cpp<br>
llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.h<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86InstrInfo.td?rev=338365&<wbr>r1=338364&r2=338365&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86I<wbr>nstrInfo.td Tue Jul 31 05:33:48 2018<br>
@@ -1750,7 +1750,7 @@ def LAHF : I<0x9F, RawFrm, (outs),<br>
// Bit tests instructions: BT, BTS, BTR, BTC.<br>
<br>
let Defs = [EFLAGS] in {<br>
-let SchedRW = [WriteALU] in {<br>
+let SchedRW = [WriteBitTest] in {<br>
def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),<br>
"bt{w}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>,<br>
@@ -1783,7 +1783,7 @@ let mayLoad = 1, hasSideEffects = 0, Sch<br>
[]>, TB, NotMemoryFoldable;<br>
}<br>
<br>
-let SchedRW = [WriteALU] in {<br>
+let SchedRW = [WriteBitTest] in {<br>
def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),<br>
"bt{w}\t{$src2, $src1|$src1, $src2}",<br>
[(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,<br>
@@ -1818,7 +1818,7 @@ def BT64mi8 : RIi8<0xBA, MRM4m, (outs),<br>
} // SchedRW<br>
<br>
let hasSideEffects = 0 in {<br>
-let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in {<br>
+let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {<br>
def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),<br>
"btc{w}\t{$src2, $src1|$src1, $src2}", []>,<br>
OpSize16, TB, NotMemoryFoldable;<br>
@@ -1842,7 +1842,7 @@ def BTC64mr : RI<0xBB, MRMDestMem, (outs<br>
NotMemoryFoldable;<br>
}<br>
<br>
-let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in {<br>
+let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {<br>
def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),<br>
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;<br>
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),<br>
@@ -1861,7 +1861,7 @@ def BTC64mi8 : RIi8<0xBA, MRM7m, (outs),<br>
Requires<[In64BitMode]>;<br>
}<br>
<br>
-let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in {<br>
+let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {<br>
def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),<br>
"btr{w}\t{$src2, $src1|$src1, $src2}", []>,<br>
OpSize16, TB, NotMemoryFoldable;<br>
@@ -1885,7 +1885,7 @@ def BTR64mr : RI<0xB3, MRMDestMem, (outs<br>
NotMemoryFoldable;<br>
}<br>
<br>
-let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in {<br>
+let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {<br>
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),<br>
"btr{w}\t{$src2, $src1|$src1, $src2}", []>,<br>
OpSize16, TB;<br>
@@ -1908,7 +1908,7 @@ def BTR64mi8 : RIi8<0xBA, MRM6m, (outs),<br>
Requires<[In64BitMode]>;<br>
}<br>
<br>
-let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in {<br>
+let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {<br>
def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),<br>
"bts{w}\t{$src2, $src1|$src1, $src2}", []>,<br>
OpSize16, TB, NotMemoryFoldable;<br>
@@ -1932,7 +1932,7 @@ def BTS64mr : RI<0xAB, MRMDestMem, (outs<br>
NotMemoryFoldable;<br>
}<br>
<br>
-let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in {<br>
+let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in {<br>
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),<br>
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;<br>
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>chedBroadwell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86SchedBroadwell.td?rev=338<wbr>365&r1=338364&r2=338365&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>chedBroadwell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>chedBroadwell.td Tue Jul 31 05:33:48 2018<br>
@@ -137,6 +137,7 @@ def : WriteRes<WriteSETCCStore, [BWPort<br>
let NumMicroOps = 3;<br>
}<br>
def : WriteRes<WriteLAHFSAHF, [BWPort06]>;<br>
+def : WriteRes<WriteBitTest,[BWPort0<wbr>6]>; // Bit Test instrs<br>
<br>
// Bit counts.<br>
defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;<br>
@@ -603,14 +604,6 @@ def BWWriteResGroup6 : SchedWriteRes<[BW<br>
let ResourceCycles = [1];<br>
}<br>
def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;<br>
-def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)ri8",<br>
- "BT(16|32|64)rr",<br>
- "BTC(16|32|64)ri8",<br>
- "BTC(16|32|64)rr",<br>
- "BTR(16|32|64)ri8",<br>
- "BTR(16|32|64)rr",<br>
- "BTS(16|32|64)ri8",<br>
- "BTS(16|32|64)rr")>;<br>
<br>
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>chedHaswell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86SchedHaswell.td?rev=33836<wbr>5&r1=338364&r2=338365&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>chedHaswell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>chedHaswell.td Tue Jul 31 05:33:48 2018<br>
@@ -150,6 +150,7 @@ def : WriteRes<WriteSETCCStore, [HWPort<br>
let NumMicroOps = 3;<br>
}<br>
def : WriteRes<WriteLAHFSAHF, [HWPort06]>;<br>
+def : WriteRes<WriteBitTest,[HWPort0<wbr>6]>;<br>
<br>
// This is for simple LEAs with one or two input operands.<br>
// The complex ones can only execute on port 1, and they require two cycles on<br>
@@ -895,14 +896,6 @@ def HWWriteResGroup7 : SchedWriteRes<[HW<br>
let ResourceCycles = [1];<br>
}<br>
def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;<br>
-def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",<br>
- "BT(16|32|64)rr",<br>
- "BTC(16|32|64)ri8",<br>
- "BTC(16|32|64)rr",<br>
- "BTR(16|32|64)ri8",<br>
- "BTR(16|32|64)rr",<br>
- "BTS(16|32|64)ri8",<br>
- "BTS(16|32|64)rr")>;<br>
<br>
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>chedSandyBridge.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86SchedSandyBridge.td?rev=<wbr>338365&r1=338364&r2=338365&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>chedSandyBridge.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>chedSandyBridge.td Tue Jul 31 05:33:48 2018<br>
@@ -145,6 +145,7 @@ def : WriteRes<WriteSETCCStore, [SBPort<br>
let NumMicroOps = 3;<br>
}<br>
def : WriteRes<WriteLAHFSAHF, [SBPort05]>;<br>
+def : WriteRes<WriteBitTest,[SBPort0<wbr>5]>;<br>
<br>
// This is for simple LEAs with one or two input operands.<br>
// The complex ones can only execute on port 1, and they require two cycles on<br>
@@ -570,14 +571,6 @@ def SBWriteResGroup4 : SchedWriteRes<[SB<br>
let ResourceCycles = [1];<br>
}<br>
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;<br>
-def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",<br>
- "BT(16|32|64)rr",<br>
- "BTC(16|32|64)ri8",<br>
- "BTC(16|32|64)rr",<br>
- "BTR(16|32|64)ri8",<br>
- "BTR(16|32|64)rr",<br>
- "BTS(16|32|64)ri8",<br>
- "BTS(16|32|64)rr")>;<br>
<br>
def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeClient.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86SchedSkylakeClient.td?rev<wbr>=338365&r1=338364&r2=338365&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeClient.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeClient.td Tue Jul 31 05:33:48 2018<br>
@@ -136,6 +136,7 @@ def : WriteRes<WriteSETCCStore, [SKLPor<br>
let NumMicroOps = 3;<br>
}<br>
def : WriteRes<WriteLAHFSAHF, [SKLPort06]>;<br>
+def : WriteRes<WriteBitTest,[SKLPort<wbr>06]>; //<br>
<br>
// Bit counts.<br>
defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;<br>
@@ -605,14 +606,6 @@ def SKLWriteResGroup7 : SchedWriteRes<[S<br>
let ResourceCycles = [1];<br>
}<br>
def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;<br>
-def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8",<br>
- "BT(16|32|64)rr",<br>
- "BTC(16|32|64)ri8",<br>
- "BTC(16|32|64)rr",<br>
- "BTR(16|32|64)ri8",<br>
- "BTR(16|32|64)rr",<br>
- "BTS(16|32|64)ri8",<br>
- "BTS(16|32|64)rr")>;<br>
<br>
def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeServer.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86SchedSkylakeServer.td?rev<wbr>=338365&r1=338364&r2=338365&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeServer.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>chedSkylakeServer.td Tue Jul 31 05:33:48 2018<br>
@@ -136,6 +136,7 @@ def : WriteRes<WriteSETCCStore, [SKXPor<br>
let NumMicroOps = 3;<br>
}<br>
def : WriteRes<WriteLAHFSAHF, [SKXPort06]>;<br>
+def : WriteRes<WriteBitTest,[SKXPort<wbr>06]>; //<br>
<br>
// Integer shifts and rotates.<br>
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;<br>
@@ -618,14 +619,6 @@ def SKXWriteResGroup7 : SchedWriteRes<[S<br>
let ResourceCycles = [1];<br>
}<br>
def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;<br>
-def: InstRW<[SKXWriteResGroup7], (instregex "BT(16|32|64)ri8",<br>
- "BT(16|32|64)rr",<br>
- "BTC(16|32|64)ri8",<br>
- "BTC(16|32|64)rr",<br>
- "BTR(16|32|64)ri8",<br>
- "BTR(16|32|64)rr",<br>
- "BTS(16|32|64)ri8",<br>
- "BTS(16|32|64)rr")>;<br>
<br>
def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {<br>
let Latency = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr><a href="http://chedule.td">chedule.td</a><br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86Schedule.td?rev=338365&r1<wbr>=338364&r2=338365&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr><a href="http://chedule.td">chedule.td</a> (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr><a href="http://chedule.td">chedule.td</a> Tue Jul 31 05:33:48 2018<br>
@@ -142,6 +142,7 @@ def WriteFCMOV : SchedWrite; // X87 con<br>
def WriteSETCC : SchedWrite; // Set register based on condition code.<br>
def WriteSETCCStore : SchedWrite;<br>
def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH.<br>
+def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support<br>
<br>
// Integer shifts and rotates.<br>
defm WriteShift : X86SchedWritePair;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>cheduleAtom.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ScheduleAtom.td?rev=33836<wbr>5&r1=338364&r2=338365&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>cheduleAtom.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>cheduleAtom.td Tue Jul 31 05:33:48 2018<br>
@@ -108,6 +108,7 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort<br>
let Latency = 2;<br>
let ResourceCycles = [2];<br>
}<br>
+def : WriteRes<WriteBitTest,[AtomPor<wbr>t01]>;<br>
<br>
defm : X86WriteResUnsupported<WriteIM<wbr>ulH>;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>cheduleBtVer2.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ScheduleBtVer2.td?rev=338<wbr>365&r1=338364&r2=338365&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>cheduleBtVer2.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>cheduleBtVer2.td Tue Jul 31 05:33:48 2018<br>
@@ -188,6 +188,7 @@ defm : X86WriteRes<WriteFCMOV, [JFPU0, J<br>
def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.<br>
def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;<br>
def : WriteRes<WriteLAHFSAHF, [JALU01]>;<br>
+def : WriteRes<WriteBitTest,[JALU01]<wbr>>;<br>
<br>
// This is for simple LEAs with one or two input operands.<br>
def : WriteRes<WriteLEA, [JALU01]>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>cheduleSLM.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ScheduleSLM.td?rev=338365<wbr>&r1=338364&r2=338365&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>cheduleSLM.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>cheduleSLM.td Tue Jul 31 05:33:48 2018<br>
@@ -120,6 +120,7 @@ def : WriteRes<WriteSETCCStore, [SLM_IE<br>
let ResourceCycles = [2,1];<br>
}<br>
def : WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01]>;<br>
+def : WriteRes<WriteBitTest,[SLM_IEC<wbr>_RSV01]>;<br>
<br>
// This is for simple LEAs with one or two input operands.<br>
// The complex ones can only execute on port 1, and they require two cycles on<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86S<wbr>cheduleZnver1.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/X86ScheduleZnver1.td?rev=338<wbr>365&r1=338364&r2=338365&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86S<wbr>cheduleZnver1.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86S<wbr>cheduleZnver1.td Tue Jul 31 05:33:48 2018<br>
@@ -198,6 +198,7 @@ defm : ZnWriteResPair<WriteCMOV2, [ZnAL<br>
def : WriteRes<WriteSETCC, [ZnALU]>;<br>
def : WriteRes<WriteSETCCStore, [ZnALU, ZnAGU]>;<br>
defm : X86WriteRes<WriteLAHFSAHF, [ZnALU], 2, [1], 2>;<br>
+def : WriteRes<WriteBitTest,[ZnALU]><wbr>;<br>
<br>
// Bit counts.<br>
defm : ZnWriteResPair<WriteBSF, [ZnALU], 3>;<br>
<br>
Modified: llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/utils/TableGe<wbr>n/CodeGenSchedule.cpp?rev=<wbr>338365&r1=338364&r2=338365&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.cpp Tue Jul 31 05:33:48 2018<br>
@@ -21,6 +21,7 @@<br>
#include "llvm/ADT/SmallSet.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
#include "llvm/Support/Casting.h"<br>
+#include "llvm/Support/CommandLine.h"<br>
#include "llvm/Support/Debug.h"<br>
#include "llvm/Support/Regex.h"<br>
#include "llvm/Support/raw_ostream.h"<br>
@@ -33,6 +34,16 @@ using namespace llvm;<br>
<br>
#define DEBUG_TYPE "subtarget-emitter"<br>
<br>
+#ifdef EXPENSIVE_CHECKS<br>
+// FIXME: TableGen is failed iff EXPENSIVE_CHECKS defined<br>
+static constexpr bool OptCheckSchedClasses = true;<br>
+#else<br>
+// FIXME: the default value should be false<br>
+static cl::opt<bool> OptCheckSchedClasses(<br>
+ "check-sched-class-table", cl::init(true), cl::Hidden,<br>
+ cl::desc("Check sched class table on different types of inconsistencies"));<br>
+#endif<br>
+<br>
#ifndef NDEBUG<br>
static void dumpIdxVec(ArrayRef<unsigned> V) {<br>
for (unsigned Idx : V)<br>
@@ -223,6 +234,7 @@ CodeGenSchedModels::CodeGenSch<wbr>edModels(R<br>
collectOptionalProcessorInfo(<wbr>);<br>
<br>
checkCompleteness();<br>
+ checkSchedClasses();<br>
}<br>
<br>
void CodeGenSchedModels::collectRet<wbr>ireControlUnits() {<br>
@@ -699,6 +711,86 @@ void CodeGenSchedModels::collectSch<wbr>edCla<br>
}<br>
}<br>
<br>
+void CodeGenSchedModels::checkSched<wbr>Classes() {<br>
+ if (!OptCheckSchedClasses)<br>
+ return;<br>
+<br>
+ std::string str;<br>
+ raw_string_ostream OS(str);<br>
+<br>
+ // Check each instruction for each model to see if its overridden too often.<br>
+ // Iff YES it's a candidate for more fine-grained Sched Class.<br>
+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumVa<wbr>lue()) {<br>
+ StringRef InstName = Inst->TheDef->getName();<br>
+ unsigned SCIdx = getSchedClassIdx(*Inst);<br>
+ if (!SCIdx)<br>
+ continue;<br>
+ CodeGenSchedClass &SC = getSchedClass(SCIdx);<br>
+ if (SC.Writes.empty())<br>
+ continue;<br>
+ const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;<br>
+ if (RWDefs.empty())<br>
+ continue;<br>
+ // FIXME: what should be threshold here?<br>
+ if (RWDefs.size() > (ProcModels.size() / 2)) {<br>
+ // FIXME: this dump hangs the execution !!!<br>
+ // SC.dump(&Target.getSchedModels<wbr>());<br>
+ OS << "SchedRW machine model for inst '" << InstName << "' (";<br>
+ for (auto I : SC.Writes)<br>
+ OS << " " << SchedWrites[I].Name;<br>
+ for (auto I : SC.Reads)<br>
+ OS << " " << SchedReads[I].Name;<br>
+ OS << " ) should be updated /improvedbecause it's overriden " << RWDefs.size()<br>
+ << " times out of " << ProcModels.size() << " models:\n\t";<br>
+ for (Record *RWDef : RWDefs)<br>
+ OS << " " << getProcModel(RWDef->getValueAs<wbr>Def("SchedModel")).ModelName;<br>
+ PrintWarning(OS.str());<br>
+ str.clear();<br>
+ }<br>
+<br>
+ // TODO: here we should check latency/uop in SC vs. RWDef. Maybe we<br>
+ // should do it iff RWDefs.size() == 1 only.<br>
+ // Iff latency/uop are the same then warn about unnecessary redefine.<br>
+ if (RWDefs.size()) {<br>
+ for (Record *RWDef : RWDefs) {<br>
+ IdxVec Writes;<br>
+ IdxVec Reads;<br>
+ findRWs(RWDef->getValueAsListO<wbr>fDefs("OperandReadWrites"), Writes,<br>
+ Reads);<br>
+<br>
+ if ((Writes.size() == SC.Writes.size()) &&<br>
+ (Reads.size() == SC.Reads.size())) {<br>
+ // TODO: do we need sorting Write & Reads?<br>
+ for (unsigned I = 0, S = SC.Writes.size(); I < S; I++) {<br>
+ auto SCSchedW = SchedWrites[SC.Writes[I]];<br>
+ auto SchedW = SchedWrites[Writes[I]];<br>
+ if (!SCSchedW.TheDef || !SchedW.TheDef)<br>
+ continue;<br>
+ const RecordVal *R = SCSchedW.TheDef->getValue("Lat<wbr>ency");<br>
+ // FIXME: We should deal with default Latency here<br>
+ if (!R || !R->getValue())<br>
+ continue;<br>
+ auto SCLat = SCSchedW.TheDef->getValueAsInt<wbr>("Latency");<br>
+ auto SCuOp = SCSchedW.TheDef->getValueAsInt<wbr>("NumMicroOps");<br>
+ auto Lat = SchedW.TheDef->getValueAsInt("<wbr>Latency");<br>
+ auto uOp = SchedW.TheDef->getValueAsInt("<wbr>NumMicroOps");<br>
+ if ((SCLat == Lat) && (SCuOp == uOp))<br>
+ OS << "Overridden verion of inst '" << InstName<br>
+ << "' has the same latency & uOp values as the original one "<br>
+ "for model '"<br>
+ << getProcModel(RWDef->getValueAs<wbr>Def("SchedModel")).ModelName<br>
+ << "'\n";<br>
+ }<br>
+ if (!str.empty()) {<br>
+ PrintWarning(OS.str());<br>
+ str.clear();<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+}<br>
+<br>
// Get the SchedClass index for an instruction.<br>
unsigned<br>
CodeGenSchedModels::getSchedC<wbr>lassIdx(const CodeGenInstruction &Inst) const {<br>
<br>
Modified: llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.h?rev=338365&r1=338364&r2=338365&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/utils/TableGe<wbr>n/CodeGenSchedule.h?rev=<wbr>338365&r1=338364&r2=338365&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.h (original)<br>
+++ llvm/trunk/utils/TableGen/Code<wbr>GenSchedule.h Tue Jul 31 05:33:48 2018<br>
@@ -443,6 +443,8 @@ private:<br>
<br>
void collectSchedClasses();<br>
<br>
+ void checkSchedClasses();<br>
+<br>
void collectRetireControlUnits();<br>
<br>
void collectRegisterFiles();<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div></blockquote></div><br></div>